Tuomas Tynkkynen | 0c59d26 | 2015-05-13 17:58:35 +0300 | [diff] [blame] | 1 | NVIDIA Tegra124 DFLL FCPU clocksource |
| 2 | |
| 3 | This binding uses the common clock binding: |
| 4 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 5 | |
| 6 | The DFLL IP block on Tegra is a root clocksource designed for clocking |
| 7 | the fast CPU cluster. It consists of a free-running voltage controlled |
| 8 | oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop |
| 9 | control module that will automatically adjust the VDD_CPU voltage by |
| 10 | communicating with an off-chip PMIC either via an I2C bus or via PWM signals. |
| 11 | Currently only the I2C mode is supported by these bindings. |
| 12 | |
| 13 | Required properties: |
| 14 | - compatible : should be "nvidia,tegra124-dfll" |
| 15 | - reg : Defines the following set of registers, in the order listed: |
| 16 | - registers for the DFLL control logic. |
| 17 | - registers for the I2C output logic. |
| 18 | - registers for the integrated I2C master controller. |
| 19 | - look-up table RAM for voltage register values. |
| 20 | - interrupts: Should contain the DFLL block interrupt. |
| 21 | - clocks: Must contain an entry for each entry in clock-names. |
| 22 | See clock-bindings.txt for details. |
| 23 | - clock-names: Must include the following entries: |
| 24 | - soc: Clock source for the DFLL control logic. |
| 25 | - ref: The closed loop reference clock |
| 26 | - i2c: Clock source for the integrated I2C master. |
| 27 | - resets: Must contain an entry for each entry in reset-names. |
| 28 | See ../reset/reset.txt for details. |
| 29 | - reset-names: Must include the following entries: |
| 30 | - dvco: Reset control for the DFLL DVCO. |
| 31 | - #clock-cells: Must be 0. |
| 32 | - clock-output-names: Name of the clock output. |
| 33 | - vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL |
| 34 | hardware will start controlling. The regulator will be queried for |
| 35 | the I2C register, control values and supported voltages. |
| 36 | |
| 37 | Required properties for the control loop parameters: |
| 38 | - nvidia,sample-rate: Sample rate of the DFLL control loop. |
| 39 | - nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM. |
| 40 | - nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM. |
| 41 | - nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM. |
| 42 | - nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM. |
| 43 | - nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM. |
| 44 | |
| 45 | Optional properties for the control loop parameters: |
| 46 | - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM. |
| 47 | |
| 48 | Required properties for I2C mode: |
| 49 | - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode. |
| 50 | |
| 51 | Example: |
| 52 | |
Thierry Reding | f43521e | 2016-04-12 17:07:35 +0200 | [diff] [blame] | 53 | clock@70110000 { |
Tuomas Tynkkynen | 0c59d26 | 2015-05-13 17:58:35 +0300 | [diff] [blame] | 54 | compatible = "nvidia,tegra124-dfll"; |
| 55 | reg = <0 0x70110000 0 0x100>, /* DFLL control */ |
| 56 | <0 0x70110000 0 0x100>, /* I2C output control */ |
| 57 | <0 0x70110100 0 0x100>, /* Integrated I2C controller */ |
| 58 | <0 0x70110200 0 0x100>; /* Look-up table RAM */ |
| 59 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| 60 | clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, |
| 61 | <&tegra_car TEGRA124_CLK_DFLL_REF>, |
| 62 | <&tegra_car TEGRA124_CLK_I2C5>; |
| 63 | clock-names = "soc", "ref", "i2c"; |
| 64 | resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; |
| 65 | reset-names = "dvco"; |
| 66 | #clock-cells = <0>; |
| 67 | clock-output-names = "dfllCPU_out"; |
| 68 | vdd-cpu-supply = <&vdd_cpu>; |
| 69 | status = "okay"; |
| 70 | |
| 71 | nvidia,sample-rate = <12500>; |
| 72 | nvidia,droop-ctrl = <0x00000f00>; |
| 73 | nvidia,force-mode = <1>; |
| 74 | nvidia,cf = <10>; |
| 75 | nvidia,ci = <0>; |
| 76 | nvidia,cg = <2>; |
| 77 | |
| 78 | nvidia,i2c-fs-rate = <400000>; |
| 79 | }; |