Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * File: arch/blackfin/mach-bf533/ints-priority.c |
| 3 | * Based on: |
| 4 | * Author: Michael Hennerich |
| 5 | * |
| 6 | * Created: ? |
Simon Arlott | d2d50aa | 2007-06-11 15:31:30 +0800 | [diff] [blame] | 7 | * Description: Set up the interrupt priorities |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 8 | * |
| 9 | * Modified: |
| 10 | * Copyright 2004-2006 Analog Devices Inc. |
| 11 | * |
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2 of the License, or |
| 17 | * (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, see the file COPYING, or write |
| 26 | * to the Free Software Foundation, Inc., |
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 28 | */ |
| 29 | |
| 30 | #include <linux/module.h> |
Mike Frysinger | 1f83b8f | 2007-07-12 22:58:21 +0800 | [diff] [blame] | 31 | #include <linux/irq.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 32 | #include <asm/blackfin.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 33 | |
Mike Frysinger | 9216bbc | 2008-08-14 14:35:20 +0800 | [diff] [blame] | 34 | void __init program_IAR(void) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 35 | { |
| 36 | /* Program the IAR0 Register with the configured priority */ |
| 37 | bfin_write_SIC_IAR0(((CONFIG_PLLWAKE_ERROR - 7) << PLLWAKE_ERROR_POS) | |
| 38 | ((CONFIG_DMA_ERROR - 7) << DMA_ERROR_POS) | |
| 39 | ((CONFIG_PPI_ERROR - 7) << PPI_ERROR_POS) | |
| 40 | ((CONFIG_SPORT0_ERROR - 7) << SPORT0_ERROR_POS) | |
| 41 | ((CONFIG_SPI_ERROR - 7) << SPI_ERROR_POS) | |
| 42 | ((CONFIG_SPORT1_ERROR - 7) << SPORT1_ERROR_POS) | |
| 43 | ((CONFIG_UART_ERROR - 7) << UART_ERROR_POS) | |
| 44 | ((CONFIG_RTC_ERROR - 7) << RTC_ERROR_POS)); |
| 45 | |
| 46 | bfin_write_SIC_IAR1(((CONFIG_DMA0_PPI - 7) << DMA0_PPI_POS) | |
| 47 | ((CONFIG_DMA1_SPORT0RX - 7) << DMA1_SPORT0RX_POS) | |
| 48 | ((CONFIG_DMA2_SPORT0TX - 7) << DMA2_SPORT0TX_POS) | |
| 49 | ((CONFIG_DMA3_SPORT1RX - 7) << DMA3_SPORT1RX_POS) | |
| 50 | ((CONFIG_DMA4_SPORT1TX - 7) << DMA4_SPORT1TX_POS) | |
| 51 | ((CONFIG_DMA5_SPI - 7) << DMA5_SPI_POS) | |
| 52 | ((CONFIG_DMA6_UARTRX - 7) << DMA6_UARTRX_POS) | |
| 53 | ((CONFIG_DMA7_UARTTX - 7) << DMA7_UARTTX_POS)); |
| 54 | |
| 55 | bfin_write_SIC_IAR2(((CONFIG_TIMER0 - 7) << TIMER0_POS) | |
| 56 | ((CONFIG_TIMER1 - 7) << TIMER1_POS) | |
| 57 | ((CONFIG_TIMER2 - 7) << TIMER2_POS) | |
| 58 | ((CONFIG_PFA - 7) << PFA_POS) | |
| 59 | ((CONFIG_PFB - 7) << PFB_POS) | |
| 60 | ((CONFIG_MEMDMA0 - 7) << MEMDMA0_POS) | |
| 61 | ((CONFIG_MEMDMA1 - 7) << MEMDMA1_POS) | |
| 62 | ((CONFIG_WDTIMER - 7) << WDTIMER_POS)); |
| 63 | |
| 64 | SSYNC(); |
| 65 | } |