Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Russell King | 4baa992 | 2008-08-02 10:55:55 +0100 | [diff] [blame] | 2 | * arch/arm/include/asm/hardware/sa1111.h |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu> |
| 5 | * |
| 6 | * This file contains definitions for the SA-1111 Companion Chip. |
| 7 | * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.) |
| 8 | * |
| 9 | * Macro that calculates real address for registers in the SA-1111 |
| 10 | */ |
| 11 | |
| 12 | #ifndef _ASM_ARCH_SA1111 |
| 13 | #define _ASM_ARCH_SA1111 |
| 14 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 15 | #include <mach/bitfield.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
| 17 | /* |
| 18 | * The SA1111 is always located at virtual 0xf4000000, and is always |
| 19 | * "native" endian. |
| 20 | */ |
| 21 | |
| 22 | #define SA1111_VBASE 0xf4000000 |
| 23 | |
| 24 | /* Don't use these! */ |
| 25 | #define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE) |
| 26 | #define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE) |
| 27 | |
| 28 | #ifndef __ASSEMBLY__ |
| 29 | #define _SA1111(x) ((x) + sa1111->resource.start) |
| 30 | #endif |
| 31 | |
Nicolas Pitre | bc43fd4 | 2007-02-17 03:18:39 +0100 | [diff] [blame] | 32 | #define sa1111_writel(val,addr) __raw_writel(val, addr) |
| 33 | #define sa1111_readl(addr) __raw_readl(addr) |
| 34 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | /* |
| 36 | * 26 bits of the SA-1110 address bus are available to the SA-1111. |
| 37 | * Use these when feeding target addresses to the DMA engines. |
| 38 | */ |
| 39 | |
| 40 | #define SA1111_ADDR_WIDTH (26) |
| 41 | #define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1) |
| 42 | #define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK) |
| 43 | |
| 44 | /* |
| 45 | * Don't ask the (SAC) DMA engines to move less than this amount. |
| 46 | */ |
| 47 | |
| 48 | #define SA1111_SAC_DMA_MIN_XFER (0x800) |
| 49 | |
| 50 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | * System Bus Interface (SBI) |
| 52 | * |
| 53 | * Registers |
| 54 | * SKCR Control Register |
| 55 | * SMCR Shared Memory Controller Register |
| 56 | * SKID ID Register |
| 57 | */ |
| 58 | #define SA1111_SKCR 0x0000 |
| 59 | #define SA1111_SMCR 0x0004 |
| 60 | #define SA1111_SKID 0x0008 |
| 61 | |
| 62 | #define SKCR_PLL_BYPASS (1<<0) |
| 63 | #define SKCR_RCLKEN (1<<1) |
| 64 | #define SKCR_SLEEP (1<<2) |
| 65 | #define SKCR_DOZE (1<<3) |
| 66 | #define SKCR_VCO_OFF (1<<4) |
| 67 | #define SKCR_SCANTSTEN (1<<5) |
| 68 | #define SKCR_CLKTSTEN (1<<6) |
| 69 | #define SKCR_RDYEN (1<<7) |
| 70 | #define SKCR_SELAC (1<<8) |
| 71 | #define SKCR_OPPC (1<<9) |
| 72 | #define SKCR_PLLTSTEN (1<<10) |
| 73 | #define SKCR_USBIOTSTEN (1<<11) |
| 74 | /* |
| 75 | * Don't believe the specs! Take them, throw them outside. Leave them |
| 76 | * there for a week. Spit on them. Walk on them. Stamp on them. |
| 77 | * Pour gasoline over them and finally burn them. Now think about coding. |
| 78 | * - The October 1999 errata (278260-007) says its bit 13, 1 to enable. |
| 79 | * - The Feb 2001 errata (278260-010) says that the previous errata |
| 80 | * (278260-009) is wrong, and its bit actually 12, fixed in spec |
| 81 | * 278242-003. |
| 82 | * - The SA1111 manual (278242) says bit 12, but 0 to enable. |
| 83 | * - Reality is bit 13, 1 to enable. |
| 84 | * -- rmk |
| 85 | */ |
| 86 | #define SKCR_OE_EN (1<<13) |
| 87 | |
| 88 | #define SMCR_DTIM (1<<0) |
| 89 | #define SMCR_MBGE (1<<1) |
| 90 | #define SMCR_DRAC_0 (1<<2) |
| 91 | #define SMCR_DRAC_1 (1<<3) |
| 92 | #define SMCR_DRAC_2 (1<<4) |
| 93 | #define SMCR_DRAC Fld(3, 2) |
| 94 | #define SMCR_CLAT (1<<5) |
| 95 | |
| 96 | #define SKID_SIREV_MASK (0x000000f0) |
| 97 | #define SKID_MTREV_MASK (0x0000000f) |
| 98 | #define SKID_ID_MASK (0xffffff00) |
| 99 | #define SKID_SA1111_ID (0x690cc200) |
| 100 | |
| 101 | /* |
| 102 | * System Controller |
| 103 | * |
| 104 | * Registers |
| 105 | * SKPCR Power Control Register |
| 106 | * SKCDR Clock Divider Register |
| 107 | * SKAUD Audio Clock Divider Register |
| 108 | * SKPMC PS/2 Mouse Clock Divider Register |
| 109 | * SKPTC PS/2 Track Pad Clock Divider Register |
| 110 | * SKPEN0 PWM0 Enable Register |
| 111 | * SKPWM0 PWM0 Clock Register |
| 112 | * SKPEN1 PWM1 Enable Register |
| 113 | * SKPWM1 PWM1 Clock Register |
| 114 | */ |
| 115 | #define SA1111_SKPCR 0x0200 |
| 116 | #define SA1111_SKCDR 0x0204 |
| 117 | #define SA1111_SKAUD 0x0208 |
| 118 | #define SA1111_SKPMC 0x020c |
| 119 | #define SA1111_SKPTC 0x0210 |
| 120 | #define SA1111_SKPEN0 0x0214 |
| 121 | #define SA1111_SKPWM0 0x0218 |
| 122 | #define SA1111_SKPEN1 0x021c |
| 123 | #define SA1111_SKPWM1 0x0220 |
| 124 | |
| 125 | #define SKPCR_UCLKEN (1<<0) |
| 126 | #define SKPCR_ACCLKEN (1<<1) |
| 127 | #define SKPCR_I2SCLKEN (1<<2) |
| 128 | #define SKPCR_L3CLKEN (1<<3) |
| 129 | #define SKPCR_SCLKEN (1<<4) |
| 130 | #define SKPCR_PMCLKEN (1<<5) |
| 131 | #define SKPCR_PTCLKEN (1<<6) |
| 132 | #define SKPCR_DCLKEN (1<<7) |
| 133 | #define SKPCR_PWMCLKEN (1<<8) |
| 134 | |
Russell King | 2213536 | 2012-01-16 11:37:03 +0000 | [diff] [blame] | 135 | /* USB Host controller */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 136 | #define SA1111_USB 0x0400 |
| 137 | |
| 138 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | * Serial Audio Controller |
| 140 | * |
| 141 | * Registers |
| 142 | * SACR0 Serial Audio Common Control Register |
| 143 | * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register |
| 144 | * SACR2 Serial Audio AC-link Control Register |
| 145 | * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register |
| 146 | * SASR1 Serial Audio AC-link Interface & FIFO Status Register |
| 147 | * SASCR Serial Audio Status Clear Register |
| 148 | * L3_CAR L3 Control Bus Address Register |
| 149 | * L3_CDR L3 Control Bus Data Register |
| 150 | * ACCAR AC-link Command Address Register |
| 151 | * ACCDR AC-link Command Data Register |
| 152 | * ACSAR AC-link Status Address Register |
| 153 | * ACSDR AC-link Status Data Register |
| 154 | * SADTCS Serial Audio DMA Transmit Control/Status Register |
| 155 | * SADTSA Serial Audio DMA Transmit Buffer Start Address A |
| 156 | * SADTCA Serial Audio DMA Transmit Buffer Count Register A |
| 157 | * SADTSB Serial Audio DMA Transmit Buffer Start Address B |
| 158 | * SADTCB Serial Audio DMA Transmit Buffer Count Register B |
| 159 | * SADRCS Serial Audio DMA Receive Control/Status Register |
| 160 | * SADRSA Serial Audio DMA Receive Buffer Start Address A |
| 161 | * SADRCA Serial Audio DMA Receive Buffer Count Register A |
| 162 | * SADRSB Serial Audio DMA Receive Buffer Start Address B |
| 163 | * SADRCB Serial Audio DMA Receive Buffer Count Register B |
| 164 | * SAITR Serial Audio Interrupt Test Register |
| 165 | * SADR Serial Audio Data Register (16 x 32-bit) |
| 166 | */ |
| 167 | |
Nicolas Pitre | bc43fd4 | 2007-02-17 03:18:39 +0100 | [diff] [blame] | 168 | #define SA1111_SERAUDIO 0x0600 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | |
Nicolas Pitre | bc43fd4 | 2007-02-17 03:18:39 +0100 | [diff] [blame] | 170 | /* |
| 171 | * These are offsets from the above base. |
| 172 | */ |
| 173 | #define SA1111_SACR0 0x00 |
| 174 | #define SA1111_SACR1 0x04 |
| 175 | #define SA1111_SACR2 0x08 |
| 176 | #define SA1111_SASR0 0x0c |
| 177 | #define SA1111_SASR1 0x10 |
| 178 | #define SA1111_SASCR 0x18 |
| 179 | #define SA1111_L3_CAR 0x1c |
| 180 | #define SA1111_L3_CDR 0x20 |
| 181 | #define SA1111_ACCAR 0x24 |
| 182 | #define SA1111_ACCDR 0x28 |
| 183 | #define SA1111_ACSAR 0x2c |
| 184 | #define SA1111_ACSDR 0x30 |
| 185 | #define SA1111_SADTCS 0x34 |
| 186 | #define SA1111_SADTSA 0x38 |
| 187 | #define SA1111_SADTCA 0x3c |
| 188 | #define SA1111_SADTSB 0x40 |
| 189 | #define SA1111_SADTCB 0x44 |
| 190 | #define SA1111_SADRCS 0x48 |
| 191 | #define SA1111_SADRSA 0x4c |
| 192 | #define SA1111_SADRCA 0x50 |
| 193 | #define SA1111_SADRSB 0x54 |
| 194 | #define SA1111_SADRCB 0x58 |
| 195 | #define SA1111_SAITR 0x5c |
| 196 | #define SA1111_SADR 0x80 |
| 197 | |
| 198 | #ifndef CONFIG_ARCH_PXA |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | |
| 200 | #define SACR0_ENB (1<<0) |
| 201 | #define SACR0_BCKD (1<<2) |
| 202 | #define SACR0_RST (1<<3) |
| 203 | |
| 204 | #define SACR1_AMSL (1<<0) |
| 205 | #define SACR1_L3EN (1<<1) |
| 206 | #define SACR1_L3MB (1<<2) |
| 207 | #define SACR1_DREC (1<<3) |
| 208 | #define SACR1_DRPL (1<<4) |
| 209 | #define SACR1_ENLBF (1<<5) |
| 210 | |
| 211 | #define SACR2_TS3V (1<<0) |
| 212 | #define SACR2_TS4V (1<<1) |
| 213 | #define SACR2_WKUP (1<<2) |
| 214 | #define SACR2_DREC (1<<3) |
| 215 | #define SACR2_DRPL (1<<4) |
| 216 | #define SACR2_ENLBF (1<<5) |
| 217 | #define SACR2_RESET (1<<6) |
| 218 | |
| 219 | #define SASR0_TNF (1<<0) |
| 220 | #define SASR0_RNE (1<<1) |
| 221 | #define SASR0_BSY (1<<2) |
| 222 | #define SASR0_TFS (1<<3) |
| 223 | #define SASR0_RFS (1<<4) |
| 224 | #define SASR0_TUR (1<<5) |
| 225 | #define SASR0_ROR (1<<6) |
| 226 | #define SASR0_L3WD (1<<16) |
| 227 | #define SASR0_L3RD (1<<17) |
| 228 | |
| 229 | #define SASR1_TNF (1<<0) |
| 230 | #define SASR1_RNE (1<<1) |
| 231 | #define SASR1_BSY (1<<2) |
| 232 | #define SASR1_TFS (1<<3) |
| 233 | #define SASR1_RFS (1<<4) |
| 234 | #define SASR1_TUR (1<<5) |
| 235 | #define SASR1_ROR (1<<6) |
| 236 | #define SASR1_CADT (1<<16) |
| 237 | #define SASR1_SADR (1<<17) |
| 238 | #define SASR1_RSTO (1<<18) |
| 239 | #define SASR1_CLPM (1<<19) |
| 240 | #define SASR1_CRDY (1<<20) |
| 241 | #define SASR1_RS3V (1<<21) |
| 242 | #define SASR1_RS4V (1<<22) |
| 243 | |
| 244 | #define SASCR_TUR (1<<5) |
| 245 | #define SASCR_ROR (1<<6) |
| 246 | #define SASCR_DTS (1<<16) |
| 247 | #define SASCR_RDD (1<<17) |
| 248 | #define SASCR_STO (1<<18) |
| 249 | |
| 250 | #define SADTCS_TDEN (1<<0) |
| 251 | #define SADTCS_TDIE (1<<1) |
| 252 | #define SADTCS_TDBDA (1<<3) |
| 253 | #define SADTCS_TDSTA (1<<4) |
| 254 | #define SADTCS_TDBDB (1<<5) |
| 255 | #define SADTCS_TDSTB (1<<6) |
| 256 | #define SADTCS_TBIU (1<<7) |
| 257 | |
| 258 | #define SADRCS_RDEN (1<<0) |
| 259 | #define SADRCS_RDIE (1<<1) |
| 260 | #define SADRCS_RDBDA (1<<3) |
| 261 | #define SADRCS_RDSTA (1<<4) |
| 262 | #define SADRCS_RDBDB (1<<5) |
| 263 | #define SADRCS_RDSTB (1<<6) |
| 264 | #define SADRCS_RBIU (1<<7) |
| 265 | |
| 266 | #define SAD_CS_DEN (1<<0) |
| 267 | #define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */ |
| 268 | #define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */ |
| 269 | #define SAD_CS_DSTA (1<<4) |
| 270 | #define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */ |
| 271 | #define SAD_CS_DSTB (1<<6) |
| 272 | #define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */ |
| 273 | |
| 274 | #define SAITR_TFS (1<<0) |
| 275 | #define SAITR_RFS (1<<1) |
| 276 | #define SAITR_TUR (1<<2) |
| 277 | #define SAITR_ROR (1<<3) |
| 278 | #define SAITR_CADT (1<<4) |
| 279 | #define SAITR_SADR (1<<5) |
| 280 | #define SAITR_RSTO (1<<6) |
| 281 | #define SAITR_TDBDA (1<<8) |
| 282 | #define SAITR_TDBDB (1<<9) |
| 283 | #define SAITR_RDBDA (1<<10) |
| 284 | #define SAITR_RDBDB (1<<11) |
| 285 | |
Nicolas Pitre | bc43fd4 | 2007-02-17 03:18:39 +0100 | [diff] [blame] | 286 | #endif /* !CONFIG_ARCH_PXA */ |
| 287 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | /* |
| 289 | * General-Purpose I/O Interface |
| 290 | * |
| 291 | * Registers |
| 292 | * PA_DDR GPIO Block A Data Direction |
| 293 | * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write) |
| 294 | * PA_SDR GPIO Block A Sleep Direction |
| 295 | * PA_SSR GPIO Block A Sleep State |
| 296 | * PB_DDR GPIO Block B Data Direction |
| 297 | * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write) |
| 298 | * PB_SDR GPIO Block B Sleep Direction |
| 299 | * PB_SSR GPIO Block B Sleep State |
| 300 | * PC_DDR GPIO Block C Data Direction |
| 301 | * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write) |
| 302 | * PC_SDR GPIO Block C Sleep Direction |
| 303 | * PC_SSR GPIO Block C Sleep State |
| 304 | */ |
| 305 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | #define SA1111_GPIO 0x1000 |
| 307 | |
| 308 | #define SA1111_GPIO_PADDR (0x000) |
| 309 | #define SA1111_GPIO_PADRR (0x004) |
| 310 | #define SA1111_GPIO_PADWR (0x004) |
| 311 | #define SA1111_GPIO_PASDR (0x008) |
| 312 | #define SA1111_GPIO_PASSR (0x00c) |
| 313 | #define SA1111_GPIO_PBDDR (0x010) |
| 314 | #define SA1111_GPIO_PBDRR (0x014) |
| 315 | #define SA1111_GPIO_PBDWR (0x014) |
| 316 | #define SA1111_GPIO_PBSDR (0x018) |
| 317 | #define SA1111_GPIO_PBSSR (0x01c) |
| 318 | #define SA1111_GPIO_PCDDR (0x020) |
| 319 | #define SA1111_GPIO_PCDRR (0x024) |
| 320 | #define SA1111_GPIO_PCDWR (0x024) |
| 321 | #define SA1111_GPIO_PCSDR (0x028) |
| 322 | #define SA1111_GPIO_PCSSR (0x02c) |
| 323 | |
| 324 | #define GPIO_A0 (1 << 0) |
| 325 | #define GPIO_A1 (1 << 1) |
| 326 | #define GPIO_A2 (1 << 2) |
| 327 | #define GPIO_A3 (1 << 3) |
| 328 | |
| 329 | #define GPIO_B0 (1 << 8) |
| 330 | #define GPIO_B1 (1 << 9) |
| 331 | #define GPIO_B2 (1 << 10) |
| 332 | #define GPIO_B3 (1 << 11) |
| 333 | #define GPIO_B4 (1 << 12) |
| 334 | #define GPIO_B5 (1 << 13) |
| 335 | #define GPIO_B6 (1 << 14) |
| 336 | #define GPIO_B7 (1 << 15) |
| 337 | |
| 338 | #define GPIO_C0 (1 << 16) |
| 339 | #define GPIO_C1 (1 << 17) |
| 340 | #define GPIO_C2 (1 << 18) |
| 341 | #define GPIO_C3 (1 << 19) |
| 342 | #define GPIO_C4 (1 << 20) |
| 343 | #define GPIO_C5 (1 << 21) |
| 344 | #define GPIO_C6 (1 << 22) |
| 345 | #define GPIO_C7 (1 << 23) |
| 346 | |
| 347 | /* |
| 348 | * Interrupt Controller |
| 349 | * |
| 350 | * Registers |
| 351 | * INTTEST0 Test register 0 |
| 352 | * INTTEST1 Test register 1 |
| 353 | * INTEN0 Interrupt Enable register 0 |
| 354 | * INTEN1 Interrupt Enable register 1 |
| 355 | * INTPOL0 Interrupt Polarity selection 0 |
| 356 | * INTPOL1 Interrupt Polarity selection 1 |
| 357 | * INTTSTSEL Interrupt source selection |
| 358 | * INTSTATCLR0 Interrupt Status/Clear 0 |
| 359 | * INTSTATCLR1 Interrupt Status/Clear 1 |
| 360 | * INTSET0 Interrupt source set 0 |
| 361 | * INTSET1 Interrupt source set 1 |
| 362 | * WAKE_EN0 Wake-up source enable 0 |
| 363 | * WAKE_EN1 Wake-up source enable 1 |
| 364 | * WAKE_POL0 Wake-up polarity selection 0 |
| 365 | * WAKE_POL1 Wake-up polarity selection 1 |
| 366 | */ |
| 367 | #define SA1111_INTC 0x1600 |
| 368 | |
| 369 | /* |
| 370 | * These are offsets from the above base. |
| 371 | */ |
| 372 | #define SA1111_INTTEST0 0x0000 |
| 373 | #define SA1111_INTTEST1 0x0004 |
| 374 | #define SA1111_INTEN0 0x0008 |
| 375 | #define SA1111_INTEN1 0x000c |
| 376 | #define SA1111_INTPOL0 0x0010 |
| 377 | #define SA1111_INTPOL1 0x0014 |
| 378 | #define SA1111_INTTSTSEL 0x0018 |
| 379 | #define SA1111_INTSTATCLR0 0x001c |
| 380 | #define SA1111_INTSTATCLR1 0x0020 |
| 381 | #define SA1111_INTSET0 0x0024 |
| 382 | #define SA1111_INTSET1 0x0028 |
| 383 | #define SA1111_WAKEEN0 0x002c |
| 384 | #define SA1111_WAKEEN1 0x0030 |
| 385 | #define SA1111_WAKEPOL0 0x0034 |
| 386 | #define SA1111_WAKEPOL1 0x0038 |
| 387 | |
Russell King | 4f8d9ca | 2012-01-16 11:29:43 +0000 | [diff] [blame] | 388 | /* PS/2 Trackpad and Mouse Interfaces */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 389 | #define SA1111_KBD 0x0a00 |
| 390 | #define SA1111_MSE 0x0c00 |
| 391 | |
Russell King | ea8c00a | 2012-01-16 11:32:09 +0000 | [diff] [blame] | 392 | /* PCMCIA Interface */ |
| 393 | #define SA1111_PCMCIA 0x1600 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | |
| 396 | |
| 397 | |
| 398 | |
| 399 | extern struct bus_type sa1111_bus_type; |
| 400 | |
Russell King | e5c0fc4 | 2012-01-25 10:42:52 +0000 | [diff] [blame] | 401 | #define SA1111_DEVID_SBI (1 << 0) |
| 402 | #define SA1111_DEVID_SK (1 << 1) |
| 403 | #define SA1111_DEVID_USB (1 << 2) |
| 404 | #define SA1111_DEVID_SAC (1 << 3) |
| 405 | #define SA1111_DEVID_SSP (1 << 4) |
| 406 | #define SA1111_DEVID_PS2 (3 << 5) |
| 407 | #define SA1111_DEVID_PS2_KBD (1 << 5) |
| 408 | #define SA1111_DEVID_PS2_MSE (1 << 6) |
| 409 | #define SA1111_DEVID_GPIO (1 << 7) |
| 410 | #define SA1111_DEVID_INT (1 << 8) |
| 411 | #define SA1111_DEVID_PCMCIA (1 << 9) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | |
| 413 | struct sa1111_dev { |
| 414 | struct device dev; |
| 415 | unsigned int devid; |
| 416 | struct resource res; |
| 417 | void __iomem *mapbase; |
| 418 | unsigned int skpcr_mask; |
| 419 | unsigned int irq[6]; |
| 420 | u64 dma_mask; |
| 421 | }; |
| 422 | |
| 423 | #define SA1111_DEV(_d) container_of((_d), struct sa1111_dev, dev) |
| 424 | |
| 425 | #define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev) |
| 426 | #define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p) |
| 427 | |
| 428 | struct sa1111_driver { |
| 429 | struct device_driver drv; |
| 430 | unsigned int devid; |
| 431 | int (*probe)(struct sa1111_dev *); |
| 432 | int (*remove)(struct sa1111_dev *); |
| 433 | int (*suspend)(struct sa1111_dev *, pm_message_t); |
| 434 | int (*resume)(struct sa1111_dev *); |
Russell King | 6bd72f0 | 2012-01-26 11:01:18 +0000 | [diff] [blame] | 435 | void (*shutdown)(struct sa1111_dev *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | }; |
| 437 | |
| 438 | #define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) |
| 439 | |
| 440 | #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) |
| 441 | |
| 442 | /* |
Russell King | ae99ddb | 2012-01-26 13:25:47 +0000 | [diff] [blame] | 443 | * These frob the SKPCR register, and call platform specific |
| 444 | * enable/disable functions. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 445 | */ |
Russell King | ae99ddb | 2012-01-26 13:25:47 +0000 | [diff] [blame] | 446 | int sa1111_enable_device(struct sa1111_dev *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | void sa1111_disable_device(struct sa1111_dev *); |
| 448 | |
| 449 | unsigned int sa1111_pll_clock(struct sa1111_dev *); |
| 450 | |
| 451 | #define SA1111_AUDIO_ACLINK 0 |
| 452 | #define SA1111_AUDIO_I2S 1 |
| 453 | |
| 454 | void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode); |
| 455 | int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate); |
| 456 | int sa1111_get_audio_rate(struct sa1111_dev *sadev); |
| 457 | |
| 458 | int sa1111_check_dma_bug(dma_addr_t addr); |
| 459 | |
| 460 | int sa1111_driver_register(struct sa1111_driver *); |
| 461 | void sa1111_driver_unregister(struct sa1111_driver *); |
| 462 | |
| 463 | void sa1111_set_io_dir(struct sa1111_dev *sadev, unsigned int bits, unsigned int dir, unsigned int sleep_dir); |
| 464 | void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v); |
| 465 | void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v); |
| 466 | |
Eric Miao | 19851c5 | 2009-12-26 16:23:02 +0800 | [diff] [blame] | 467 | struct sa1111_platform_data { |
| 468 | int irq_base; /* base for cascaded on-chip IRQs */ |
Russell King | 07be45f | 2012-01-26 13:34:21 +0000 | [diff] [blame] | 469 | unsigned disable_devs; |
Russell King | ae99ddb | 2012-01-26 13:25:47 +0000 | [diff] [blame] | 470 | void *data; |
| 471 | int (*enable)(void *, unsigned); |
| 472 | void (*disable)(void *, unsigned); |
Eric Miao | 19851c5 | 2009-12-26 16:23:02 +0800 | [diff] [blame] | 473 | }; |
| 474 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 475 | #endif /* _ASM_ARCH_SA1111 */ |