Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 2 | /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver |
| 3 | * Copyright (C) 2004 Advanced Micro Devices |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 5 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ] |
| 7 | * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c] |
| 8 | * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ] |
| 9 | * Derived from the lance driver written 1993,1994,1995 by Donald Becker. |
| 10 | * Copyright 1993 United States Government as represented by the |
| 11 | * Director, National Security Agency.[ pcnet32.c ] |
| 12 | * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ] |
| 13 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
| 14 | * |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 15 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License as published by |
| 18 | * the Free Software Foundation; either version 2 of the License, or |
| 19 | * (at your option) any later version. |
| 20 | * |
| 21 | * This program is distributed in the hope that it will be useful, |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 24 | * GNU General Public License for more details. |
| 25 | * |
| 26 | * You should have received a copy of the GNU General Public License |
Jeff Kirsher | 0ab75ae | 2013-12-06 06:28:43 -0800 | [diff] [blame] | 27 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 28 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | Module Name: |
| 30 | |
| 31 | amd8111e.c |
| 32 | |
| 33 | Abstract: |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 34 | |
| 35 | AMD8111 based 10/100 Ethernet Controller Driver. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
| 37 | Environment: |
| 38 | |
| 39 | Kernel Mode |
| 40 | |
| 41 | Revision History: |
| 42 | 3.0.0 |
| 43 | Initial Revision. |
| 44 | 3.0.1 |
| 45 | 1. Dynamic interrupt coalescing. |
| 46 | 2. Removed prev_stats. |
| 47 | 3. MII support. |
| 48 | 4. Dynamic IPG support |
| 49 | 3.0.2 05/29/2003 |
| 50 | 1. Bug fix: Fixed failure to send jumbo packets larger than 4k. |
| 51 | 2. Bug fix: Fixed VLAN support failure. |
| 52 | 3. Bug fix: Fixed receive interrupt coalescing bug. |
| 53 | 4. Dynamic IPG support is disabled by default. |
| 54 | 3.0.3 06/05/2003 |
| 55 | 1. Bug fix: Fixed failure to close the interface if SMP is enabled. |
| 56 | 3.0.4 12/09/2003 |
| 57 | 1. Added set_mac_address routine for bonding driver support. |
| 58 | 2. Tested the driver for bonding support |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 59 | 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | indicated to the h/w. |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 61 | 4. Modified amd8111e_rx() routine to receive all the received packets |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | in the first interrupt. |
| 63 | 5. Bug fix: Corrected rx_errors reported in get_stats() function. |
| 64 | 3.0.5 03/22/2004 |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 65 | 1. Added NAPI support |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | |
| 67 | */ |
| 68 | |
| 69 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | #include <linux/module.h> |
| 71 | #include <linux/kernel.h> |
| 72 | #include <linux/types.h> |
| 73 | #include <linux/compiler.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | #include <linux/delay.h> |
Alexey Dobriyan | a6b7a40 | 2011-06-06 10:43:46 +0000 | [diff] [blame] | 75 | #include <linux/interrupt.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | #include <linux/ioport.h> |
| 77 | #include <linux/pci.h> |
| 78 | #include <linux/netdevice.h> |
| 79 | #include <linux/etherdevice.h> |
| 80 | #include <linux/skbuff.h> |
| 81 | #include <linux/ethtool.h> |
| 82 | #include <linux/mii.h> |
| 83 | #include <linux/if_vlan.h> |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 84 | #include <linux/ctype.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | #include <linux/crc32.h> |
Tobias Klauser | cac8c81 | 2005-05-16 19:15:11 +0200 | [diff] [blame] | 86 | #include <linux/dma-mapping.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | #include <asm/io.h> |
| 89 | #include <asm/byteorder.h> |
| 90 | #include <asm/uaccess.h> |
| 91 | |
| 92 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
| 93 | #define AMD8111E_VLAN_TAG_USED 1 |
| 94 | #else |
| 95 | #define AMD8111E_VLAN_TAG_USED 0 |
| 96 | #endif |
| 97 | |
| 98 | #include "amd8111e.h" |
| 99 | #define MODULE_NAME "amd8111e" |
Francois Romieu | 6ba33ac | 2008-07-06 20:55:12 -0700 | [diff] [blame] | 100 | #define MODULE_VERS "3.0.7" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | MODULE_AUTHOR("Advanced Micro Devices, Inc."); |
Francois Romieu | 6ba33ac | 2008-07-06 20:55:12 -0700 | [diff] [blame] | 102 | MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | MODULE_LICENSE("GPL"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | module_param_array(speed_duplex, int, NULL, 0); |
Joe Perches | 983960b | 2011-05-02 09:59:29 +0000 | [diff] [blame] | 105 | MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotiate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | module_param_array(coalesce, bool, NULL, 0); |
| 107 | MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable"); |
| 108 | module_param_array(dynamic_ipg, bool, NULL, 0); |
| 109 | MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable"); |
| 110 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 111 | /* This function will read the PHY registers. */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 112 | static int amd8111e_read_phy(struct amd8111e_priv *lp, |
| 113 | int phy_id, int reg, u32 *val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | { |
| 115 | void __iomem *mmio = lp->mmio; |
| 116 | unsigned int reg_val; |
| 117 | unsigned int repeat= REPEAT_CNT; |
| 118 | |
| 119 | reg_val = readl(mmio + PHY_ACCESS); |
| 120 | while (reg_val & PHY_CMD_ACTIVE) |
| 121 | reg_val = readl( mmio + PHY_ACCESS ); |
| 122 | |
| 123 | writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) | |
| 124 | ((reg & 0x1f) << 16), mmio +PHY_ACCESS); |
| 125 | do{ |
| 126 | reg_val = readl(mmio + PHY_ACCESS); |
| 127 | udelay(30); /* It takes 30 us to read/write data */ |
| 128 | } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); |
| 129 | if(reg_val & PHY_RD_ERR) |
| 130 | goto err_phy_read; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 131 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | *val = reg_val & 0xffff; |
| 133 | return 0; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 134 | err_phy_read: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | *val = 0; |
| 136 | return -EINVAL; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 137 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | } |
| 139 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 140 | /* This function will write into PHY registers. */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 141 | static int amd8111e_write_phy(struct amd8111e_priv *lp, |
| 142 | int phy_id, int reg, u32 val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | { |
Yoann Padioleau | 632155e | 2007-06-01 00:46:35 -0700 | [diff] [blame] | 144 | unsigned int repeat = REPEAT_CNT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | void __iomem *mmio = lp->mmio; |
| 146 | unsigned int reg_val; |
| 147 | |
| 148 | reg_val = readl(mmio + PHY_ACCESS); |
| 149 | while (reg_val & PHY_CMD_ACTIVE) |
| 150 | reg_val = readl( mmio + PHY_ACCESS ); |
| 151 | |
| 152 | writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) | |
| 153 | ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); |
| 154 | |
| 155 | do{ |
| 156 | reg_val = readl(mmio + PHY_ACCESS); |
| 157 | udelay(30); /* It takes 30 us to read/write the data */ |
| 158 | } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 159 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | if(reg_val & PHY_RD_ERR) |
| 161 | goto err_phy_write; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 162 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | return 0; |
| 164 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 165 | err_phy_write: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | return -EINVAL; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 167 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | } |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 169 | |
| 170 | /* This is the mii register read function provided to the mii interface. */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 171 | static int amd8111e_mdio_read(struct net_device *dev, int phy_id, int reg_num) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 172 | { |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 173 | struct amd8111e_priv *lp = netdev_priv(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | unsigned int reg_val; |
| 175 | |
| 176 | amd8111e_read_phy(lp,phy_id,reg_num,®_val); |
| 177 | return reg_val; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 178 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | } |
| 180 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 181 | /* This is the mii register write function provided to the mii interface. */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 182 | static void amd8111e_mdio_write(struct net_device *dev, |
| 183 | int phy_id, int reg_num, int val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 184 | { |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 185 | struct amd8111e_priv *lp = netdev_priv(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | |
| 187 | amd8111e_write_phy(lp, phy_id, reg_num, val); |
| 188 | } |
| 189 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 190 | /* This function will set PHY speed. During initialization sets |
| 191 | * the original speed to 100 full |
| 192 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | static void amd8111e_set_ext_phy(struct net_device *dev) |
| 194 | { |
| 195 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 196 | u32 bmcr,advert,tmp; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 197 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 198 | /* Determine mii register values to set the speed */ |
| 199 | advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE); |
| 200 | tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4); |
| 201 | switch (lp->ext_phy_option){ |
| 202 | |
| 203 | default: |
| 204 | case SPEED_AUTONEG: /* advertise all values */ |
| 205 | tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL| |
| 206 | ADVERTISE_100HALF|ADVERTISE_100FULL) ; |
| 207 | break; |
| 208 | case SPEED10_HALF: |
| 209 | tmp |= ADVERTISE_10HALF; |
| 210 | break; |
| 211 | case SPEED10_FULL: |
| 212 | tmp |= ADVERTISE_10FULL; |
| 213 | break; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 214 | case SPEED100_HALF: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | tmp |= ADVERTISE_100HALF; |
| 216 | break; |
| 217 | case SPEED100_FULL: |
| 218 | tmp |= ADVERTISE_100FULL; |
| 219 | break; |
| 220 | } |
| 221 | |
| 222 | if(advert != tmp) |
| 223 | amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp); |
| 224 | /* Restart auto negotiation */ |
| 225 | bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR); |
| 226 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
| 227 | amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr); |
| 228 | |
| 229 | } |
| 230 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 231 | /* This function will unmap skb->data space and will free |
| 232 | * all transmit and receive skbuffs. |
| 233 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | static int amd8111e_free_skbs(struct net_device *dev) |
| 235 | { |
| 236 | struct amd8111e_priv *lp = netdev_priv(dev); |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 237 | struct sk_buff *rx_skbuff; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | int i; |
| 239 | |
| 240 | /* Freeing transmit skbs */ |
| 241 | for(i = 0; i < NUM_TX_BUFFERS; i++){ |
| 242 | if(lp->tx_skbuff[i]){ |
| 243 | pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE); |
| 244 | dev_kfree_skb (lp->tx_skbuff[i]); |
| 245 | lp->tx_skbuff[i] = NULL; |
| 246 | lp->tx_dma_addr[i] = 0; |
| 247 | } |
| 248 | } |
| 249 | /* Freeing previously allocated receive buffers */ |
| 250 | for (i = 0; i < NUM_RX_BUFFERS; i++){ |
| 251 | rx_skbuff = lp->rx_skbuff[i]; |
| 252 | if(rx_skbuff != NULL){ |
| 253 | pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i], |
| 254 | lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE); |
| 255 | dev_kfree_skb(lp->rx_skbuff[i]); |
| 256 | lp->rx_skbuff[i] = NULL; |
| 257 | lp->rx_dma_addr[i] = 0; |
| 258 | } |
| 259 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 260 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | return 0; |
| 262 | } |
| 263 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 264 | /* This will set the receive buffer length corresponding |
| 265 | * to the mtu size of networkinterface. |
| 266 | */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 267 | static inline void amd8111e_set_rx_buff_len(struct net_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 268 | { |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 269 | struct amd8111e_priv *lp = netdev_priv(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 270 | unsigned int mtu = dev->mtu; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 271 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | if (mtu > ETH_DATA_LEN){ |
| 273 | /* MTU + ethernet header + FCS |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 274 | * + optional VLAN tag + skb reserve space 2 |
| 275 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | lp->rx_buff_len = mtu + ETH_HLEN + 10; |
| 277 | lp->options |= OPTION_JUMBO_ENABLE; |
| 278 | } else{ |
| 279 | lp->rx_buff_len = PKT_BUFF_SZ; |
| 280 | lp->options &= ~OPTION_JUMBO_ENABLE; |
| 281 | } |
| 282 | } |
| 283 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 284 | /* This function will free all the previously allocated buffers, |
| 285 | * determine new receive buffer length and will allocate new receive buffers. |
| 286 | * This function also allocates and initializes both the transmitter |
| 287 | * and receive hardware descriptors. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | */ |
| 289 | static int amd8111e_init_ring(struct net_device *dev) |
| 290 | { |
| 291 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 292 | int i; |
| 293 | |
| 294 | lp->rx_idx = lp->tx_idx = 0; |
| 295 | lp->tx_complete_idx = 0; |
| 296 | lp->tx_ring_idx = 0; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 297 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 298 | |
| 299 | if(lp->opened) |
| 300 | /* Free previously allocated transmit and receive skbs */ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 301 | amd8111e_free_skbs(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 302 | |
| 303 | else{ |
| 304 | /* allocate the tx and rx descriptors */ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 305 | if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR, |
| 307 | &lp->tx_ring_dma_addr)) == NULL) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 308 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 309 | goto err_no_mem; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 310 | |
| 311 | if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR, |
| 313 | &lp->rx_ring_dma_addr)) == NULL) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 314 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | goto err_free_tx_ring; |
| 316 | |
| 317 | } |
| 318 | /* Set new receive buff size */ |
| 319 | amd8111e_set_rx_buff_len(dev); |
| 320 | |
| 321 | /* Allocating receive skbs */ |
| 322 | for (i = 0; i < NUM_RX_BUFFERS; i++) { |
| 323 | |
Pradeep A Dalvi | 1d26643 | 2012-02-05 02:49:09 +0000 | [diff] [blame] | 324 | lp->rx_skbuff[i] = netdev_alloc_skb(dev, lp->rx_buff_len); |
| 325 | if (!lp->rx_skbuff[i]) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 326 | /* Release previos allocated skbs */ |
| 327 | for(--i; i >= 0 ;i--) |
| 328 | dev_kfree_skb(lp->rx_skbuff[i]); |
| 329 | goto err_free_rx_ring; |
| 330 | } |
| 331 | skb_reserve(lp->rx_skbuff[i],2); |
| 332 | } |
| 333 | /* Initilaizing receive descriptors */ |
| 334 | for (i = 0; i < NUM_RX_BUFFERS; i++) { |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 335 | lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 336 | lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE); |
| 337 | |
| 338 | lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]); |
| 339 | lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2); |
| 340 | wmb(); |
| 341 | lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT); |
| 342 | } |
| 343 | |
| 344 | /* Initializing transmit descriptors */ |
| 345 | for (i = 0; i < NUM_TX_RING_DR; i++) { |
| 346 | lp->tx_ring[i].buff_phy_addr = 0; |
| 347 | lp->tx_ring[i].tx_flags = 0; |
| 348 | lp->tx_ring[i].buff_count = 0; |
| 349 | } |
| 350 | |
| 351 | return 0; |
| 352 | |
| 353 | err_free_rx_ring: |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 354 | |
| 355 | pci_free_consistent(lp->pci_dev, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring, |
| 357 | lp->rx_ring_dma_addr); |
| 358 | |
| 359 | err_free_tx_ring: |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 360 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | pci_free_consistent(lp->pci_dev, |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 362 | sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 363 | lp->tx_ring_dma_addr); |
| 364 | |
| 365 | err_no_mem: |
| 366 | return -ENOMEM; |
| 367 | } |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 368 | |
| 369 | /* This function will set the interrupt coalescing according |
| 370 | * to the input arguments |
| 371 | */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 372 | static int amd8111e_set_coalesce(struct net_device *dev, enum coal_mode cmod) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 373 | { |
| 374 | unsigned int timeout; |
| 375 | unsigned int event_count; |
| 376 | |
| 377 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 378 | void __iomem *mmio = lp->mmio; |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 379 | struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 380 | |
| 381 | |
| 382 | switch(cmod) |
| 383 | { |
| 384 | case RX_INTR_COAL : |
| 385 | timeout = coal_conf->rx_timeout; |
| 386 | event_count = coal_conf->rx_event_count; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 387 | if( timeout > MAX_TIMEOUT || |
| 388 | event_count > MAX_EVENT_COUNT ) |
Julia Lawall | 022484c | 2010-08-05 10:22:20 +0000 | [diff] [blame] | 389 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 390 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 391 | timeout = timeout * DELAY_TIMER_CONV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 392 | writel(VAL0|STINTEN, mmio+INTEN0); |
| 393 | writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout, |
| 394 | mmio+DLY_INT_A); |
| 395 | break; |
| 396 | |
| 397 | case TX_INTR_COAL : |
| 398 | timeout = coal_conf->tx_timeout; |
| 399 | event_count = coal_conf->tx_event_count; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 400 | if( timeout > MAX_TIMEOUT || |
| 401 | event_count > MAX_EVENT_COUNT ) |
Julia Lawall | 022484c | 2010-08-05 10:22:20 +0000 | [diff] [blame] | 402 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 404 | |
| 405 | timeout = timeout * DELAY_TIMER_CONV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 406 | writel(VAL0|STINTEN,mmio+INTEN0); |
| 407 | writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout, |
| 408 | mmio+DLY_INT_B); |
| 409 | break; |
| 410 | |
| 411 | case DISABLE_COAL: |
| 412 | writel(0,mmio+STVAL); |
| 413 | writel(STINTEN, mmio+INTEN0); |
| 414 | writel(0, mmio +DLY_INT_B); |
| 415 | writel(0, mmio+DLY_INT_A); |
| 416 | break; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 417 | case ENABLE_COAL: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 418 | /* Start the timer */ |
| 419 | writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */ |
| 420 | writel(VAL0|STINTEN, mmio+INTEN0); |
| 421 | break; |
| 422 | default: |
| 423 | break; |
| 424 | |
| 425 | } |
| 426 | return 0; |
| 427 | |
| 428 | } |
| 429 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 430 | /* This function initializes the device registers and starts the device. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 431 | static int amd8111e_restart(struct net_device *dev) |
| 432 | { |
| 433 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 434 | void __iomem *mmio = lp->mmio; |
| 435 | int i,reg_val; |
| 436 | |
| 437 | /* stop the chip */ |
| 438 | writel(RUN, mmio + CMD0); |
| 439 | |
| 440 | if(amd8111e_init_ring(dev)) |
| 441 | return -ENOMEM; |
| 442 | |
| 443 | /* enable the port manager and set auto negotiation always */ |
| 444 | writel((u32) VAL1|EN_PMGR, mmio + CMD3 ); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 445 | writel((u32)XPHYANE|XPHYRST , mmio + CTRL2); |
| 446 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | amd8111e_set_ext_phy(dev); |
| 448 | |
| 449 | /* set control registers */ |
| 450 | reg_val = readl(mmio + CTRL1); |
| 451 | reg_val &= ~XMTSP_MASK; |
| 452 | writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 ); |
| 453 | |
| 454 | /* enable interrupt */ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 455 | writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN | |
| 457 | SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0); |
| 458 | |
| 459 | writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); |
| 460 | |
| 461 | /* initialize tx and rx ring base addresses */ |
| 462 | writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0); |
| 463 | writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0); |
| 464 | |
| 465 | writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0); |
| 466 | writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 467 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 468 | /* set default IPG to 96 */ |
| 469 | writew((u32)DEFAULT_IPG,mmio+IPG); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 470 | writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 471 | |
| 472 | if(lp->options & OPTION_JUMBO_ENABLE){ |
| 473 | writel((u32)VAL2|JUMBO, mmio + CMD3); |
| 474 | /* Reset REX_UFLO */ |
| 475 | writel( REX_UFLO, mmio + CMD2); |
| 476 | /* Should not set REX_UFLO for jumbo frames */ |
| 477 | writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2); |
| 478 | }else{ |
| 479 | writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2); |
| 480 | writel((u32)JUMBO, mmio + CMD3); |
| 481 | } |
| 482 | |
| 483 | #if AMD8111E_VLAN_TAG_USED |
| 484 | writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3); |
| 485 | #endif |
| 486 | writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 ); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 487 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | /* Setting the MAC address to the device */ |
Joe Perches | c857ff6 | 2011-11-16 09:38:05 +0000 | [diff] [blame] | 489 | for (i = 0; i < ETH_ALEN; i++) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 490 | writeb( dev->dev_addr[i], mmio + PADR + i ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | |
| 492 | /* Enable interrupt coalesce */ |
| 493 | if(lp->options & OPTION_INTR_COAL_ENABLE){ |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 494 | netdev_info(dev, "Interrupt Coalescing Enabled.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | amd8111e_set_coalesce(dev,ENABLE_COAL); |
| 496 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 497 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 498 | /* set RUN bit to start the chip */ |
| 499 | writel(VAL2 | RDMD0, mmio + CMD0); |
| 500 | writel(VAL0 | INTREN | RUN, mmio + CMD0); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 501 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 502 | /* To avoid PCI posting bug */ |
| 503 | readl(mmio+CMD0); |
| 504 | return 0; |
| 505 | } |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 506 | |
| 507 | /* This function clears necessary the device registers. */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 508 | static void amd8111e_init_hw_default(struct amd8111e_priv *lp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 509 | { |
| 510 | unsigned int reg_val; |
| 511 | unsigned int logic_filter[2] ={0,}; |
| 512 | void __iomem *mmio = lp->mmio; |
| 513 | |
| 514 | |
| 515 | /* stop the chip */ |
| 516 | writel(RUN, mmio + CMD0); |
| 517 | |
| 518 | /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */ |
| 519 | writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0); |
| 520 | |
| 521 | /* Clear RCV_RING_BASE_ADDR */ |
| 522 | writel(0, mmio + RCV_RING_BASE_ADDR0); |
| 523 | |
| 524 | /* Clear XMT_RING_BASE_ADDR */ |
| 525 | writel(0, mmio + XMT_RING_BASE_ADDR0); |
| 526 | writel(0, mmio + XMT_RING_BASE_ADDR1); |
| 527 | writel(0, mmio + XMT_RING_BASE_ADDR2); |
| 528 | writel(0, mmio + XMT_RING_BASE_ADDR3); |
| 529 | |
| 530 | /* Clear CMD0 */ |
| 531 | writel(CMD0_CLEAR,mmio + CMD0); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 532 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 533 | /* Clear CMD2 */ |
| 534 | writel(CMD2_CLEAR, mmio +CMD2); |
| 535 | |
| 536 | /* Clear CMD7 */ |
| 537 | writel(CMD7_CLEAR , mmio + CMD7); |
| 538 | |
| 539 | /* Clear DLY_INT_A and DLY_INT_B */ |
| 540 | writel(0x0, mmio + DLY_INT_A); |
| 541 | writel(0x0, mmio + DLY_INT_B); |
| 542 | |
| 543 | /* Clear FLOW_CONTROL */ |
| 544 | writel(0x0, mmio + FLOW_CONTROL); |
| 545 | |
| 546 | /* Clear INT0 write 1 to clear register */ |
| 547 | reg_val = readl(mmio + INT0); |
| 548 | writel(reg_val, mmio + INT0); |
| 549 | |
| 550 | /* Clear STVAL */ |
| 551 | writel(0x0, mmio + STVAL); |
| 552 | |
| 553 | /* Clear INTEN0 */ |
| 554 | writel( INTEN0_CLEAR, mmio + INTEN0); |
| 555 | |
| 556 | /* Clear LADRF */ |
| 557 | writel(0x0 , mmio + LADRF); |
| 558 | |
| 559 | /* Set SRAM_SIZE & SRAM_BOUNDARY registers */ |
| 560 | writel( 0x80010,mmio + SRAM_SIZE); |
| 561 | |
| 562 | /* Clear RCV_RING0_LEN */ |
| 563 | writel(0x0, mmio + RCV_RING_LEN0); |
| 564 | |
| 565 | /* Clear XMT_RING0/1/2/3_LEN */ |
| 566 | writel(0x0, mmio + XMT_RING_LEN0); |
| 567 | writel(0x0, mmio + XMT_RING_LEN1); |
| 568 | writel(0x0, mmio + XMT_RING_LEN2); |
| 569 | writel(0x0, mmio + XMT_RING_LEN3); |
| 570 | |
| 571 | /* Clear XMT_RING_LIMIT */ |
| 572 | writel(0x0, mmio + XMT_RING_LIMIT); |
| 573 | |
| 574 | /* Clear MIB */ |
| 575 | writew(MIB_CLEAR, mmio + MIB_ADDR); |
| 576 | |
| 577 | /* Clear LARF */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 578 | amd8111e_writeq(*(u64 *)logic_filter, mmio + LADRF); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 579 | |
| 580 | /* SRAM_SIZE register */ |
| 581 | reg_val = readl(mmio + SRAM_SIZE); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 582 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 583 | if(lp->options & OPTION_JUMBO_ENABLE) |
| 584 | writel( VAL2|JUMBO, mmio + CMD3); |
| 585 | #if AMD8111E_VLAN_TAG_USED |
| 586 | writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 ); |
| 587 | #endif |
| 588 | /* Set default value to CTRL1 Register */ |
| 589 | writel(CTRL1_DEFAULT, mmio + CTRL1); |
| 590 | |
| 591 | /* To avoid PCI posting bug */ |
| 592 | readl(mmio + CMD2); |
| 593 | |
| 594 | } |
| 595 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 596 | /* This function disables the interrupt and clears all the pending |
| 597 | * interrupts in INT0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 598 | */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 599 | static void amd8111e_disable_interrupt(struct amd8111e_priv *lp) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 600 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 601 | u32 intr0; |
| 602 | |
| 603 | /* Disable interrupt */ |
| 604 | writel(INTREN, lp->mmio + CMD0); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 605 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 606 | /* Clear INT0 */ |
| 607 | intr0 = readl(lp->mmio + INT0); |
| 608 | writel(intr0, lp->mmio + INT0); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 609 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 610 | /* To avoid PCI posting bug */ |
| 611 | readl(lp->mmio + INT0); |
| 612 | |
| 613 | } |
| 614 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 615 | /* This function stops the chip. */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 616 | static void amd8111e_stop_chip(struct amd8111e_priv *lp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | { |
| 618 | writel(RUN, lp->mmio + CMD0); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 619 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | /* To avoid PCI posting bug */ |
| 621 | readl(lp->mmio + CMD0); |
| 622 | } |
| 623 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 624 | /* This function frees the transmiter and receiver descriptor rings. */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 625 | static void amd8111e_free_ring(struct amd8111e_priv *lp) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 626 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 627 | /* Free transmit and receive descriptor rings */ |
| 628 | if(lp->rx_ring){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 629 | pci_free_consistent(lp->pci_dev, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 630 | sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR, |
| 631 | lp->rx_ring, lp->rx_ring_dma_addr); |
| 632 | lp->rx_ring = NULL; |
| 633 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 634 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 635 | if(lp->tx_ring){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 636 | pci_free_consistent(lp->pci_dev, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 637 | sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR, |
| 638 | lp->tx_ring, lp->tx_ring_dma_addr); |
| 639 | |
| 640 | lp->tx_ring = NULL; |
| 641 | } |
| 642 | |
| 643 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 645 | /* This function will free all the transmit skbs that are actually |
| 646 | * transmitted by the device. It will check the ownership of the |
| 647 | * skb before freeing the skb. |
| 648 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 649 | static int amd8111e_tx(struct net_device *dev) |
| 650 | { |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 651 | struct amd8111e_priv *lp = netdev_priv(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 652 | int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK; |
| 653 | int status; |
| 654 | /* Complete all the transmit packet */ |
| 655 | while (lp->tx_complete_idx != lp->tx_idx){ |
| 656 | tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK; |
| 657 | status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags); |
| 658 | |
| 659 | if(status & OWN_BIT) |
| 660 | break; /* It still hasn't been Txed */ |
| 661 | |
| 662 | lp->tx_ring[tx_index].buff_phy_addr = 0; |
| 663 | |
| 664 | /* We must free the original skb */ |
| 665 | if (lp->tx_skbuff[tx_index]) { |
| 666 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index], |
| 667 | lp->tx_skbuff[tx_index]->len, |
| 668 | PCI_DMA_TODEVICE); |
| 669 | dev_kfree_skb_irq (lp->tx_skbuff[tx_index]); |
| 670 | lp->tx_skbuff[tx_index] = NULL; |
| 671 | lp->tx_dma_addr[tx_index] = 0; |
| 672 | } |
| 673 | lp->tx_complete_idx++; |
| 674 | /*COAL update tx coalescing parameters */ |
| 675 | lp->coal_conf.tx_packets++; |
Al Viro | 05d2fec | 2007-08-22 21:42:28 -0400 | [diff] [blame] | 676 | lp->coal_conf.tx_bytes += |
| 677 | le16_to_cpu(lp->tx_ring[tx_index].buff_count); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 678 | |
| 679 | if (netif_queue_stopped(dev) && |
| 680 | lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){ |
| 681 | /* The ring is no longer full, clear tbusy. */ |
| 682 | /* lp->tx_full = 0; */ |
| 683 | netif_wake_queue (dev); |
| 684 | } |
| 685 | } |
| 686 | return 0; |
| 687 | } |
| 688 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 689 | /* This function handles the driver receive operation in polling mode */ |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 690 | static int amd8111e_rx_poll(struct napi_struct *napi, int budget) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 691 | { |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 692 | struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi); |
| 693 | struct net_device *dev = lp->amd8111e_net_dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 694 | int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK; |
| 695 | void __iomem *mmio = lp->mmio; |
| 696 | struct sk_buff *skb,*new_skb; |
| 697 | int min_pkt_len, status; |
| 698 | unsigned int intr0; |
| 699 | int num_rx_pkt = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 700 | short pkt_len; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 701 | #if AMD8111E_VLAN_TAG_USED |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 702 | short vtag; |
| 703 | #endif |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 704 | int rx_pkt_limit = budget; |
Liu Tao | dfa1b73 | 2005-05-12 19:40:38 -0400 | [diff] [blame] | 705 | unsigned long flags; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 706 | |
Eric W. Biederman | 278d538 | 2014-03-14 18:01:11 -0700 | [diff] [blame] | 707 | if (rx_pkt_limit <= 0) |
| 708 | goto rx_not_empty; |
| 709 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 710 | do{ |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 711 | /* process receive packets until we use the quota. |
| 712 | * If we own the next entry, it's a new packet. Send it up. |
| 713 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 714 | while(1) { |
| 715 | status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags); |
| 716 | if (status & OWN_BIT) |
| 717 | break; |
| 718 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 719 | /* There is a tricky error noted by John Murphy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 720 | * <murf@perftech.com> to Russ Nelson: Even with |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 721 | * full-sized * buffers it's possible for a |
| 722 | * jabber packet to use two buffers, with only |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 723 | * the last correctly noting the error. |
| 724 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 725 | if(status & ERR_BIT) { |
| 726 | /* reseting flags */ |
| 727 | lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; |
| 728 | goto err_next_pkt; |
| 729 | } |
| 730 | /* check for STP and ENP */ |
| 731 | if(!((status & STP_BIT) && (status & ENP_BIT))){ |
| 732 | /* reseting flags */ |
| 733 | lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; |
| 734 | goto err_next_pkt; |
| 735 | } |
| 736 | pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4; |
| 737 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 738 | #if AMD8111E_VLAN_TAG_USED |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 739 | vtag = status & TT_MASK; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 740 | /*MAC will strip vlan tag*/ |
Jiri Pirko | c8d9e6d | 2011-07-20 04:54:11 +0000 | [diff] [blame] | 741 | if (vtag != 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 742 | min_pkt_len =MIN_PKT_LEN - 4; |
| 743 | else |
| 744 | #endif |
| 745 | min_pkt_len =MIN_PKT_LEN; |
| 746 | |
| 747 | if (pkt_len < min_pkt_len) { |
| 748 | lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; |
| 749 | lp->drv_rx_errors++; |
| 750 | goto err_next_pkt; |
| 751 | } |
| 752 | if(--rx_pkt_limit < 0) |
| 753 | goto rx_not_empty; |
Pradeep A Dalvi | 1d26643 | 2012-02-05 02:49:09 +0000 | [diff] [blame] | 754 | new_skb = netdev_alloc_skb(dev, lp->rx_buff_len); |
| 755 | if (!new_skb) { |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 756 | /* if allocation fail, |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 757 | * ignore that pkt and go to next one |
| 758 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 759 | lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; |
| 760 | lp->drv_rx_errors++; |
| 761 | goto err_next_pkt; |
| 762 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 763 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 764 | skb_reserve(new_skb, 2); |
| 765 | skb = lp->rx_skbuff[rx_index]; |
| 766 | pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index], |
| 767 | lp->rx_buff_len-2, PCI_DMA_FROMDEVICE); |
| 768 | skb_put(skb, pkt_len); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 769 | lp->rx_skbuff[rx_index] = new_skb; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 770 | lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev, |
| 771 | new_skb->data, |
| 772 | lp->rx_buff_len-2, |
| 773 | PCI_DMA_FROMDEVICE); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 774 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | skb->protocol = eth_type_trans(skb, dev); |
| 776 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 777 | #if AMD8111E_VLAN_TAG_USED |
Jiri Pirko | c8d9e6d | 2011-07-20 04:54:11 +0000 | [diff] [blame] | 778 | if (vtag == TT_VLAN_TAGGED){ |
| 779 | u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info); |
Patrick McHardy | 86a9bad | 2013-04-19 02:04:30 +0000 | [diff] [blame] | 780 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); |
Jiri Pirko | c8d9e6d | 2011-07-20 04:54:11 +0000 | [diff] [blame] | 781 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | #endif |
Jiri Pirko | c8d9e6d | 2011-07-20 04:54:11 +0000 | [diff] [blame] | 783 | netif_receive_skb(skb); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | /*COAL update rx coalescing parameters*/ |
| 785 | lp->coal_conf.rx_packets++; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 786 | lp->coal_conf.rx_bytes += pkt_len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 787 | num_rx_pkt++; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 788 | |
| 789 | err_next_pkt: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 790 | lp->rx_ring[rx_index].buff_phy_addr |
| 791 | = cpu_to_le32(lp->rx_dma_addr[rx_index]); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 792 | lp->rx_ring[rx_index].buff_count = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 793 | cpu_to_le16(lp->rx_buff_len-2); |
| 794 | wmb(); |
| 795 | lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT); |
| 796 | rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK; |
| 797 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 798 | /* Check the interrupt status register for more packets in the |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 799 | * mean time. Process them since we have not used up our quota. |
| 800 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 801 | intr0 = readl(mmio + INT0); |
| 802 | /*Ack receive packets */ |
| 803 | writel(intr0 & RINT0,mmio + INT0); |
| 804 | |
| 805 | } while(intr0 & RINT0); |
| 806 | |
Chris Friesen | 48e5eca | 2008-10-28 15:50:54 -0700 | [diff] [blame] | 807 | if (rx_pkt_limit > 0) { |
| 808 | /* Receive descriptor is empty now */ |
| 809 | spin_lock_irqsave(&lp->lock, flags); |
Ben Hutchings | 288379f | 2009-01-19 16:43:59 -0800 | [diff] [blame] | 810 | __napi_complete(napi); |
Chris Friesen | 48e5eca | 2008-10-28 15:50:54 -0700 | [diff] [blame] | 811 | writel(VAL0|RINTEN0, mmio + INTEN0); |
| 812 | writel(VAL2 | RDMD0, mmio + CMD0); |
| 813 | spin_unlock_irqrestore(&lp->lock, flags); |
| 814 | } |
Liu Tao | dfa1b73 | 2005-05-12 19:40:38 -0400 | [diff] [blame] | 815 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 816 | rx_not_empty: |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 817 | return num_rx_pkt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 818 | } |
| 819 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 820 | /* This function will indicate the link status to the kernel. */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 821 | static int amd8111e_link_change(struct net_device *dev) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 822 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 823 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 824 | int status0,speed; |
| 825 | |
| 826 | /* read the link change */ |
| 827 | status0 = readl(lp->mmio + STAT0); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 828 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 829 | if(status0 & LINK_STATS){ |
| 830 | if(status0 & AUTONEG_COMPLETE) |
| 831 | lp->link_config.autoneg = AUTONEG_ENABLE; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 832 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 833 | lp->link_config.autoneg = AUTONEG_DISABLE; |
| 834 | |
| 835 | if(status0 & FULL_DPLX) |
| 836 | lp->link_config.duplex = DUPLEX_FULL; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 837 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 838 | lp->link_config.duplex = DUPLEX_HALF; |
| 839 | speed = (status0 & SPEED_MASK) >> 7; |
| 840 | if(speed == PHY_SPEED_10) |
| 841 | lp->link_config.speed = SPEED_10; |
| 842 | else if(speed == PHY_SPEED_100) |
| 843 | lp->link_config.speed = SPEED_100; |
| 844 | |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 845 | netdev_info(dev, "Link is Up. Speed is %s Mbps %s Duplex\n", |
| 846 | (lp->link_config.speed == SPEED_100) ? |
| 847 | "100" : "10", |
| 848 | (lp->link_config.duplex == DUPLEX_FULL) ? |
| 849 | "Full" : "Half"); |
| 850 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 851 | netif_carrier_on(dev); |
| 852 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 853 | else{ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 854 | lp->link_config.speed = SPEED_INVALID; |
| 855 | lp->link_config.duplex = DUPLEX_INVALID; |
| 856 | lp->link_config.autoneg = AUTONEG_INVALID; |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 857 | netdev_info(dev, "Link is Down.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 858 | netif_carrier_off(dev); |
| 859 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 860 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 861 | return 0; |
| 862 | } |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 863 | |
| 864 | /* This function reads the mib counters. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 865 | static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER) |
| 866 | { |
| 867 | unsigned int status; |
| 868 | unsigned int data; |
| 869 | unsigned int repeat = REPEAT_CNT; |
| 870 | |
| 871 | writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR); |
| 872 | do { |
| 873 | status = readw(mmio + MIB_ADDR); |
| 874 | udelay(2); /* controller takes MAX 2 us to get mib data */ |
| 875 | } |
| 876 | while (--repeat && (status & MIB_CMD_ACTIVE)); |
| 877 | |
| 878 | data = readl(mmio + MIB_DATA); |
| 879 | return data; |
| 880 | } |
| 881 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 882 | /* This function reads the mib registers and returns the hardware statistics. |
Eric Dumazet | c3227e5 | 2010-08-20 03:08:23 +0000 | [diff] [blame] | 883 | * It updates previous internal driver statistics with new values. |
| 884 | */ |
| 885 | static struct net_device_stats *amd8111e_get_stats(struct net_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 886 | { |
| 887 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 888 | void __iomem *mmio = lp->mmio; |
| 889 | unsigned long flags; |
Eric Dumazet | c3227e5 | 2010-08-20 03:08:23 +0000 | [diff] [blame] | 890 | struct net_device_stats *new_stats = &dev->stats; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 891 | |
Eric Dumazet | c3227e5 | 2010-08-20 03:08:23 +0000 | [diff] [blame] | 892 | if (!lp->opened) |
| 893 | return new_stats; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 894 | spin_lock_irqsave (&lp->lock, flags); |
| 895 | |
| 896 | /* stats.rx_packets */ |
| 897 | new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+ |
| 898 | amd8111e_read_mib(mmio, rcv_multicast_pkts)+ |
| 899 | amd8111e_read_mib(mmio, rcv_unicast_pkts); |
| 900 | |
| 901 | /* stats.tx_packets */ |
| 902 | new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets); |
| 903 | |
| 904 | /*stats.rx_bytes */ |
| 905 | new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets); |
| 906 | |
| 907 | /* stats.tx_bytes */ |
| 908 | new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets); |
| 909 | |
| 910 | /* stats.rx_errors */ |
| 911 | /* hw errors + errors driver reported */ |
| 912 | new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+ |
| 913 | amd8111e_read_mib(mmio, rcv_fragments)+ |
| 914 | amd8111e_read_mib(mmio, rcv_jabbers)+ |
| 915 | amd8111e_read_mib(mmio, rcv_alignment_errors)+ |
| 916 | amd8111e_read_mib(mmio, rcv_fcs_errors)+ |
| 917 | amd8111e_read_mib(mmio, rcv_miss_pkts)+ |
| 918 | lp->drv_rx_errors; |
| 919 | |
| 920 | /* stats.tx_errors */ |
| 921 | new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts); |
| 922 | |
| 923 | /* stats.rx_dropped*/ |
| 924 | new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts); |
| 925 | |
| 926 | /* stats.tx_dropped*/ |
| 927 | new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts); |
| 928 | |
| 929 | /* stats.multicast*/ |
| 930 | new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts); |
| 931 | |
| 932 | /* stats.collisions*/ |
| 933 | new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions); |
| 934 | |
| 935 | /* stats.rx_length_errors*/ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 936 | new_stats->rx_length_errors = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 937 | amd8111e_read_mib(mmio, rcv_undersize_pkts)+ |
| 938 | amd8111e_read_mib(mmio, rcv_oversize_pkts); |
| 939 | |
| 940 | /* stats.rx_over_errors*/ |
| 941 | new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); |
| 942 | |
| 943 | /* stats.rx_crc_errors*/ |
| 944 | new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors); |
| 945 | |
| 946 | /* stats.rx_frame_errors*/ |
| 947 | new_stats->rx_frame_errors = |
| 948 | amd8111e_read_mib(mmio, rcv_alignment_errors); |
| 949 | |
| 950 | /* stats.rx_fifo_errors */ |
| 951 | new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); |
| 952 | |
| 953 | /* stats.rx_missed_errors */ |
| 954 | new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); |
| 955 | |
| 956 | /* stats.tx_aborted_errors*/ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 957 | new_stats->tx_aborted_errors = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 958 | amd8111e_read_mib(mmio, xmt_excessive_collision); |
| 959 | |
| 960 | /* stats.tx_carrier_errors*/ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 961 | new_stats->tx_carrier_errors = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 962 | amd8111e_read_mib(mmio, xmt_loss_carrier); |
| 963 | |
| 964 | /* stats.tx_fifo_errors*/ |
| 965 | new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts); |
| 966 | |
| 967 | /* stats.tx_window_errors*/ |
| 968 | new_stats->tx_window_errors = |
| 969 | amd8111e_read_mib(mmio, xmt_late_collision); |
| 970 | |
| 971 | /* Reset the mibs for collecting new statistics */ |
| 972 | /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 973 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 974 | spin_unlock_irqrestore (&lp->lock, flags); |
| 975 | |
| 976 | return new_stats; |
| 977 | } |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 978 | |
Robert P. J. Day | 3a4fa0a | 2007-10-19 23:10:43 +0200 | [diff] [blame] | 979 | /* This function recalculate the interrupt coalescing mode on every interrupt |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 980 | * according to the datarate and the packet rate. |
| 981 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 982 | static int amd8111e_calc_coalesce(struct net_device *dev) |
| 983 | { |
| 984 | struct amd8111e_priv *lp = netdev_priv(dev); |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 985 | struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | int tx_pkt_rate; |
| 987 | int rx_pkt_rate; |
| 988 | int tx_data_rate; |
| 989 | int rx_data_rate; |
| 990 | int rx_pkt_size; |
| 991 | int tx_pkt_size; |
| 992 | |
| 993 | tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets; |
| 994 | coal_conf->tx_prev_packets = coal_conf->tx_packets; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 995 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 996 | tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes; |
| 997 | coal_conf->tx_prev_bytes = coal_conf->tx_bytes; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 998 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 999 | rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets; |
| 1000 | coal_conf->rx_prev_packets = coal_conf->rx_packets; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1001 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1002 | rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes; |
| 1003 | coal_conf->rx_prev_bytes = coal_conf->rx_bytes; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1004 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1005 | if(rx_pkt_rate < 800){ |
| 1006 | if(coal_conf->rx_coal_type != NO_COALESCE){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1007 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1008 | coal_conf->rx_timeout = 0x0; |
| 1009 | coal_conf->rx_event_count = 0; |
| 1010 | amd8111e_set_coalesce(dev,RX_INTR_COAL); |
| 1011 | coal_conf->rx_coal_type = NO_COALESCE; |
| 1012 | } |
| 1013 | } |
| 1014 | else{ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1015 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1016 | rx_pkt_size = rx_data_rate/rx_pkt_rate; |
| 1017 | if (rx_pkt_size < 128){ |
| 1018 | if(coal_conf->rx_coal_type != NO_COALESCE){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1019 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1020 | coal_conf->rx_timeout = 0; |
| 1021 | coal_conf->rx_event_count = 0; |
| 1022 | amd8111e_set_coalesce(dev,RX_INTR_COAL); |
| 1023 | coal_conf->rx_coal_type = NO_COALESCE; |
| 1024 | } |
| 1025 | |
| 1026 | } |
| 1027 | else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1028 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1029 | if(coal_conf->rx_coal_type != LOW_COALESCE){ |
| 1030 | coal_conf->rx_timeout = 1; |
| 1031 | coal_conf->rx_event_count = 4; |
| 1032 | amd8111e_set_coalesce(dev,RX_INTR_COAL); |
| 1033 | coal_conf->rx_coal_type = LOW_COALESCE; |
| 1034 | } |
| 1035 | } |
| 1036 | else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1037 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1038 | if(coal_conf->rx_coal_type != MEDIUM_COALESCE){ |
| 1039 | coal_conf->rx_timeout = 1; |
| 1040 | coal_conf->rx_event_count = 4; |
| 1041 | amd8111e_set_coalesce(dev,RX_INTR_COAL); |
| 1042 | coal_conf->rx_coal_type = MEDIUM_COALESCE; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1043 | } |
| 1044 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1045 | } |
| 1046 | else if(rx_pkt_size >= 1024){ |
| 1047 | if(coal_conf->rx_coal_type != HIGH_COALESCE){ |
| 1048 | coal_conf->rx_timeout = 2; |
| 1049 | coal_conf->rx_event_count = 3; |
| 1050 | amd8111e_set_coalesce(dev,RX_INTR_COAL); |
| 1051 | coal_conf->rx_coal_type = HIGH_COALESCE; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1052 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1053 | } |
| 1054 | } |
| 1055 | /* NOW FOR TX INTR COALESC */ |
| 1056 | if(tx_pkt_rate < 800){ |
| 1057 | if(coal_conf->tx_coal_type != NO_COALESCE){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1058 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1059 | coal_conf->tx_timeout = 0x0; |
| 1060 | coal_conf->tx_event_count = 0; |
| 1061 | amd8111e_set_coalesce(dev,TX_INTR_COAL); |
| 1062 | coal_conf->tx_coal_type = NO_COALESCE; |
| 1063 | } |
| 1064 | } |
| 1065 | else{ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1066 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1067 | tx_pkt_size = tx_data_rate/tx_pkt_rate; |
| 1068 | if (tx_pkt_size < 128){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1069 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1070 | if(coal_conf->tx_coal_type != NO_COALESCE){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1071 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1072 | coal_conf->tx_timeout = 0; |
| 1073 | coal_conf->tx_event_count = 0; |
| 1074 | amd8111e_set_coalesce(dev,TX_INTR_COAL); |
| 1075 | coal_conf->tx_coal_type = NO_COALESCE; |
| 1076 | } |
| 1077 | |
| 1078 | } |
| 1079 | else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1080 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1081 | if(coal_conf->tx_coal_type != LOW_COALESCE){ |
| 1082 | coal_conf->tx_timeout = 1; |
| 1083 | coal_conf->tx_event_count = 2; |
| 1084 | amd8111e_set_coalesce(dev,TX_INTR_COAL); |
| 1085 | coal_conf->tx_coal_type = LOW_COALESCE; |
| 1086 | |
| 1087 | } |
| 1088 | } |
| 1089 | else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1090 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1091 | if(coal_conf->tx_coal_type != MEDIUM_COALESCE){ |
| 1092 | coal_conf->tx_timeout = 2; |
| 1093 | coal_conf->tx_event_count = 5; |
| 1094 | amd8111e_set_coalesce(dev,TX_INTR_COAL); |
| 1095 | coal_conf->tx_coal_type = MEDIUM_COALESCE; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1096 | } |
| 1097 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1098 | } |
| 1099 | else if(tx_pkt_size >= 1024){ |
| 1100 | if (tx_pkt_size >= 1024){ |
| 1101 | if(coal_conf->tx_coal_type != HIGH_COALESCE){ |
| 1102 | coal_conf->tx_timeout = 4; |
| 1103 | coal_conf->tx_event_count = 8; |
| 1104 | amd8111e_set_coalesce(dev,TX_INTR_COAL); |
| 1105 | coal_conf->tx_coal_type = HIGH_COALESCE; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1106 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1107 | } |
| 1108 | } |
| 1109 | } |
| 1110 | return 0; |
| 1111 | |
| 1112 | } |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1113 | |
| 1114 | /* This is device interrupt function. It handles transmit, |
| 1115 | * receive,link change and hardware timer interrupts. |
| 1116 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1117 | static irqreturn_t amd8111e_interrupt(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1118 | { |
| 1119 | |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1120 | struct net_device *dev = (struct net_device *)dev_id; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1121 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1122 | void __iomem *mmio = lp->mmio; |
Liu Tao | dfa1b73 | 2005-05-12 19:40:38 -0400 | [diff] [blame] | 1123 | unsigned int intr0, intren0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1124 | unsigned int handled = 1; |
| 1125 | |
Liu Tao | dfa1b73 | 2005-05-12 19:40:38 -0400 | [diff] [blame] | 1126 | if(unlikely(dev == NULL)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1127 | return IRQ_NONE; |
| 1128 | |
Liu Tao | dfa1b73 | 2005-05-12 19:40:38 -0400 | [diff] [blame] | 1129 | spin_lock(&lp->lock); |
| 1130 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1131 | /* disabling interrupt */ |
| 1132 | writel(INTREN, mmio + CMD0); |
| 1133 | |
| 1134 | /* Read interrupt status */ |
| 1135 | intr0 = readl(mmio + INT0); |
Liu Tao | dfa1b73 | 2005-05-12 19:40:38 -0400 | [diff] [blame] | 1136 | intren0 = readl(mmio + INTEN0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1137 | |
| 1138 | /* Process all the INT event until INTR bit is clear. */ |
| 1139 | |
| 1140 | if (!(intr0 & INTR)){ |
| 1141 | handled = 0; |
| 1142 | goto err_no_interrupt; |
| 1143 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1144 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1145 | /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */ |
| 1146 | writel(intr0, mmio + INT0); |
| 1147 | |
| 1148 | /* Check if Receive Interrupt has occurred. */ |
Francois Romieu | 6ba33ac | 2008-07-06 20:55:12 -0700 | [diff] [blame] | 1149 | if (intr0 & RINT0) { |
Ben Hutchings | 288379f | 2009-01-19 16:43:59 -0800 | [diff] [blame] | 1150 | if (napi_schedule_prep(&lp->napi)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1151 | /* Disable receive interupts */ |
| 1152 | writel(RINTEN0, mmio + INTEN0); |
| 1153 | /* Schedule a polling routine */ |
Ben Hutchings | 288379f | 2009-01-19 16:43:59 -0800 | [diff] [blame] | 1154 | __napi_schedule(&lp->napi); |
Francois Romieu | 6ba33ac | 2008-07-06 20:55:12 -0700 | [diff] [blame] | 1155 | } else if (intren0 & RINTEN0) { |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1156 | netdev_dbg(dev, "************Driver bug! interrupt while in poll\n"); |
Liu Tao | dfa1b73 | 2005-05-12 19:40:38 -0400 | [diff] [blame] | 1157 | /* Fix by disable receive interrupts */ |
| 1158 | writel(RINTEN0, mmio + INTEN0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1159 | } |
| 1160 | } |
Francois Romieu | 6ba33ac | 2008-07-06 20:55:12 -0700 | [diff] [blame] | 1161 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1162 | /* Check if Transmit Interrupt has occurred. */ |
Francois Romieu | 6ba33ac | 2008-07-06 20:55:12 -0700 | [diff] [blame] | 1163 | if (intr0 & TINT0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1164 | amd8111e_tx(dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1165 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1166 | /* Check if Link Change Interrupt has occurred. */ |
| 1167 | if (intr0 & LCINT) |
| 1168 | amd8111e_link_change(dev); |
| 1169 | |
| 1170 | /* Check if Hardware Timer Interrupt has occurred. */ |
| 1171 | if (intr0 & STINT) |
| 1172 | amd8111e_calc_coalesce(dev); |
| 1173 | |
| 1174 | err_no_interrupt: |
| 1175 | writel( VAL0 | INTREN,mmio + CMD0); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1176 | |
Liu Tao | dfa1b73 | 2005-05-12 19:40:38 -0400 | [diff] [blame] | 1177 | spin_unlock(&lp->lock); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1178 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | return IRQ_RETVAL(handled); |
| 1180 | } |
| 1181 | |
| 1182 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1183 | static void amd8111e_poll(struct net_device *dev) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1184 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1185 | unsigned long flags; |
Jiri Kosina | b7e36bf | 2007-02-05 16:29:49 -0800 | [diff] [blame] | 1186 | local_irq_save(flags); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1187 | amd8111e_interrupt(0, dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1188 | local_irq_restore(flags); |
| 1189 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1190 | #endif |
| 1191 | |
| 1192 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1193 | /* This function closes the network interface and updates |
| 1194 | * the statistics so that most recent statistics will be |
| 1195 | * available after the interface is down. |
| 1196 | */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1197 | static int amd8111e_close(struct net_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1198 | { |
| 1199 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1200 | netif_stop_queue(dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1201 | |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 1202 | napi_disable(&lp->napi); |
| 1203 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1204 | spin_lock_irq(&lp->lock); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1205 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1206 | amd8111e_disable_interrupt(lp); |
| 1207 | amd8111e_stop_chip(lp); |
Chunbo Luo | e83603f | 2008-10-28 09:51:46 +0800 | [diff] [blame] | 1208 | |
| 1209 | /* Free transmit and receive skbs */ |
| 1210 | amd8111e_free_skbs(lp->amd8111e_net_dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1211 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1212 | netif_carrier_off(lp->amd8111e_net_dev); |
| 1213 | |
| 1214 | /* Delete ipg timer */ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1215 | if(lp->options & OPTION_DYN_IPG_ENABLE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1216 | del_timer_sync(&lp->ipg_data.ipg_timer); |
| 1217 | |
| 1218 | spin_unlock_irq(&lp->lock); |
| 1219 | free_irq(dev->irq, dev); |
Chunbo Luo | e83603f | 2008-10-28 09:51:46 +0800 | [diff] [blame] | 1220 | amd8111e_free_ring(lp); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1221 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1222 | /* Update the statistics before closing */ |
| 1223 | amd8111e_get_stats(dev); |
| 1224 | lp->opened = 0; |
| 1225 | return 0; |
| 1226 | } |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1227 | |
| 1228 | /* This function opens new interface.It requests irq for the device, |
| 1229 | * initializes the device,buffers and descriptors, and starts the device. |
| 1230 | */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1231 | static int amd8111e_open(struct net_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1232 | { |
| 1233 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1234 | |
Thomas Gleixner | 1fb9df5 | 2006-07-01 19:29:39 -0700 | [diff] [blame] | 1235 | if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED, |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1236 | dev->name, dev)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1237 | return -EAGAIN; |
| 1238 | |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 1239 | napi_enable(&lp->napi); |
| 1240 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1241 | spin_lock_irq(&lp->lock); |
| 1242 | |
| 1243 | amd8111e_init_hw_default(lp); |
| 1244 | |
| 1245 | if(amd8111e_restart(dev)){ |
| 1246 | spin_unlock_irq(&lp->lock); |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 1247 | napi_disable(&lp->napi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1248 | if (dev->irq) |
| 1249 | free_irq(dev->irq, dev); |
| 1250 | return -ENOMEM; |
| 1251 | } |
| 1252 | /* Start ipg timer */ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1253 | if(lp->options & OPTION_DYN_IPG_ENABLE){ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1254 | add_timer(&lp->ipg_data.ipg_timer); |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1255 | netdev_info(dev, "Dynamic IPG Enabled\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1256 | } |
| 1257 | |
| 1258 | lp->opened = 1; |
| 1259 | |
| 1260 | spin_unlock_irq(&lp->lock); |
| 1261 | |
| 1262 | netif_start_queue(dev); |
| 1263 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1264 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1265 | } |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1266 | |
| 1267 | /* This function checks if there is any transmit descriptors |
| 1268 | * available to queue more packet. |
| 1269 | */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1270 | static int amd8111e_tx_queue_avail(struct amd8111e_priv *lp) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1271 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1272 | int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK; |
Al Viro | ee41a82 | 2007-08-22 21:37:46 -0400 | [diff] [blame] | 1273 | if (lp->tx_skbuff[tx_index]) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1274 | return -1; |
| 1275 | else |
| 1276 | return 0; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1277 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1278 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1279 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1280 | /* This function will queue the transmit packets to the |
| 1281 | * descriptors and will trigger the send operation. It also |
| 1282 | * initializes the transmit descriptors with buffer physical address, |
| 1283 | * byte count, ownership to hardware etc. |
| 1284 | */ |
Stephen Hemminger | 61357325 | 2009-08-31 19:50:58 +0000 | [diff] [blame] | 1285 | static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb, |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1286 | struct net_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1287 | { |
| 1288 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1289 | int tx_index; |
| 1290 | unsigned long flags; |
| 1291 | |
| 1292 | spin_lock_irqsave(&lp->lock, flags); |
| 1293 | |
| 1294 | tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK; |
| 1295 | |
| 1296 | lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len); |
| 1297 | |
| 1298 | lp->tx_skbuff[tx_index] = skb; |
| 1299 | lp->tx_ring[tx_index].tx_flags = 0; |
| 1300 | |
| 1301 | #if AMD8111E_VLAN_TAG_USED |
Jiri Pirko | df8a39d | 2015-01-13 17:13:44 +0100 | [diff] [blame] | 1302 | if (skb_vlan_tag_present(skb)) { |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1303 | lp->tx_ring[tx_index].tag_ctrl_cmd |= |
| 1304 | cpu_to_le16(TCC_VLAN_INSERT); |
| 1305 | lp->tx_ring[tx_index].tag_ctrl_info = |
Jiri Pirko | df8a39d | 2015-01-13 17:13:44 +0100 | [diff] [blame] | 1306 | cpu_to_le16(skb_vlan_tag_get(skb)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1307 | |
| 1308 | } |
| 1309 | #endif |
| 1310 | lp->tx_dma_addr[tx_index] = |
| 1311 | pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); |
| 1312 | lp->tx_ring[tx_index].buff_phy_addr = |
Al Viro | ee41a82 | 2007-08-22 21:37:46 -0400 | [diff] [blame] | 1313 | cpu_to_le32(lp->tx_dma_addr[tx_index]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1314 | |
| 1315 | /* Set FCS and LTINT bits */ |
| 1316 | wmb(); |
| 1317 | lp->tx_ring[tx_index].tx_flags |= |
| 1318 | cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT); |
| 1319 | |
| 1320 | lp->tx_idx++; |
| 1321 | |
| 1322 | /* Trigger an immediate send poll. */ |
| 1323 | writel( VAL1 | TDMD0, lp->mmio + CMD0); |
| 1324 | writel( VAL2 | RDMD0,lp->mmio + CMD0); |
| 1325 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1326 | if(amd8111e_tx_queue_avail(lp) < 0){ |
| 1327 | netif_stop_queue(dev); |
| 1328 | } |
| 1329 | spin_unlock_irqrestore(&lp->lock, flags); |
Patrick McHardy | 6ed1065 | 2009-06-23 06:03:08 +0000 | [diff] [blame] | 1330 | return NETDEV_TX_OK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1331 | } |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1332 | /* This function returns all the memory mapped registers of the device. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1333 | static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf) |
| 1334 | { |
| 1335 | void __iomem *mmio = lp->mmio; |
| 1336 | /* Read only necessary registers */ |
| 1337 | buf[0] = readl(mmio + XMT_RING_BASE_ADDR0); |
| 1338 | buf[1] = readl(mmio + XMT_RING_LEN0); |
| 1339 | buf[2] = readl(mmio + RCV_RING_BASE_ADDR0); |
| 1340 | buf[3] = readl(mmio + RCV_RING_LEN0); |
| 1341 | buf[4] = readl(mmio + CMD0); |
| 1342 | buf[5] = readl(mmio + CMD2); |
| 1343 | buf[6] = readl(mmio + CMD3); |
| 1344 | buf[7] = readl(mmio + CMD7); |
| 1345 | buf[8] = readl(mmio + INT0); |
| 1346 | buf[9] = readl(mmio + INTEN0); |
| 1347 | buf[10] = readl(mmio + LADRF); |
| 1348 | buf[11] = readl(mmio + LADRF+4); |
| 1349 | buf[12] = readl(mmio + STAT0); |
| 1350 | } |
| 1351 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1352 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1353 | /* This function sets promiscuos mode, all-multi mode or the multicast address |
| 1354 | * list to the device. |
| 1355 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1356 | static void amd8111e_set_multicast_list(struct net_device *dev) |
| 1357 | { |
Jiri Pirko | 22bedad3 | 2010-04-01 21:22:57 +0000 | [diff] [blame] | 1358 | struct netdev_hw_addr *ha; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1359 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1360 | u32 mc_filter[2] ; |
Jiri Pirko | 0ddf477 | 2010-02-20 00:13:58 +0000 | [diff] [blame] | 1361 | int bit_num; |
| 1362 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1363 | if(dev->flags & IFF_PROMISC){ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1364 | writel( VAL2 | PROM, lp->mmio + CMD2); |
| 1365 | return; |
| 1366 | } |
| 1367 | else |
| 1368 | writel( PROM, lp->mmio + CMD2); |
Jiri Pirko | 4cd24ea | 2010-02-08 04:30:35 +0000 | [diff] [blame] | 1369 | if (dev->flags & IFF_ALLMULTI || |
| 1370 | netdev_mc_count(dev) > MAX_FILTER_SIZE) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1371 | /* get all multicast packet */ |
| 1372 | mc_filter[1] = mc_filter[0] = 0xffffffff; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1373 | lp->options |= OPTION_MULTICAST_ENABLE; |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1374 | amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1375 | return; |
| 1376 | } |
Jiri Pirko | 4cd24ea | 2010-02-08 04:30:35 +0000 | [diff] [blame] | 1377 | if (netdev_mc_empty(dev)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1378 | /* get only own packets */ |
| 1379 | mc_filter[1] = mc_filter[0] = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1380 | lp->options &= ~OPTION_MULTICAST_ENABLE; |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1381 | amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF); |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1382 | /* disable promiscuous mode */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1383 | writel(PROM, lp->mmio + CMD2); |
| 1384 | return; |
| 1385 | } |
| 1386 | /* load all the multicast addresses in the logic filter */ |
| 1387 | lp->options |= OPTION_MULTICAST_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1388 | mc_filter[1] = mc_filter[0] = 0; |
Jiri Pirko | 22bedad3 | 2010-04-01 21:22:57 +0000 | [diff] [blame] | 1389 | netdev_for_each_mc_addr(ha, dev) { |
| 1390 | bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1391 | mc_filter[bit_num >> 5] |= 1 << (bit_num & 31); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1392 | } |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1393 | amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1394 | |
| 1395 | /* To eliminate PCI posting bug */ |
| 1396 | readl(lp->mmio + CMD2); |
| 1397 | |
| 1398 | } |
| 1399 | |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1400 | static void amd8111e_get_drvinfo(struct net_device *dev, |
| 1401 | struct ethtool_drvinfo *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1402 | { |
| 1403 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1404 | struct pci_dev *pci_dev = lp->pci_dev; |
Rick Jones | 23020ab | 2011-11-09 09:58:07 +0000 | [diff] [blame] | 1405 | strlcpy(info->driver, MODULE_NAME, sizeof(info->driver)); |
| 1406 | strlcpy(info->version, MODULE_VERS, sizeof(info->version)); |
| 1407 | snprintf(info->fw_version, sizeof(info->fw_version), |
| 1408 | "%u", chip_version); |
| 1409 | strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1410 | } |
| 1411 | |
| 1412 | static int amd8111e_get_regs_len(struct net_device *dev) |
| 1413 | { |
| 1414 | return AMD8111E_REG_DUMP_LEN; |
| 1415 | } |
| 1416 | |
| 1417 | static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) |
| 1418 | { |
| 1419 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1420 | regs->version = 0; |
| 1421 | amd8111e_read_regs(lp, buf); |
| 1422 | } |
| 1423 | |
| 1424 | static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
| 1425 | { |
| 1426 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1427 | spin_lock_irq(&lp->lock); |
| 1428 | mii_ethtool_gset(&lp->mii_if, ecmd); |
| 1429 | spin_unlock_irq(&lp->lock); |
| 1430 | return 0; |
| 1431 | } |
| 1432 | |
| 1433 | static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
| 1434 | { |
| 1435 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1436 | int res; |
| 1437 | spin_lock_irq(&lp->lock); |
| 1438 | res = mii_ethtool_sset(&lp->mii_if, ecmd); |
| 1439 | spin_unlock_irq(&lp->lock); |
| 1440 | return res; |
| 1441 | } |
| 1442 | |
| 1443 | static int amd8111e_nway_reset(struct net_device *dev) |
| 1444 | { |
| 1445 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1446 | return mii_nway_restart(&lp->mii_if); |
| 1447 | } |
| 1448 | |
| 1449 | static u32 amd8111e_get_link(struct net_device *dev) |
| 1450 | { |
| 1451 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1452 | return mii_link_ok(&lp->mii_if); |
| 1453 | } |
| 1454 | |
| 1455 | static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info) |
| 1456 | { |
| 1457 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1458 | wol_info->supported = WAKE_MAGIC|WAKE_PHY; |
| 1459 | if (lp->options & OPTION_WOL_ENABLE) |
| 1460 | wol_info->wolopts = WAKE_MAGIC; |
| 1461 | } |
| 1462 | |
| 1463 | static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info) |
| 1464 | { |
| 1465 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1466 | if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY)) |
| 1467 | return -EINVAL; |
| 1468 | spin_lock_irq(&lp->lock); |
| 1469 | if (wol_info->wolopts & WAKE_MAGIC) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1470 | lp->options |= |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1471 | (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE); |
| 1472 | else if(wol_info->wolopts & WAKE_PHY) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1473 | lp->options |= |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1474 | (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE); |
| 1475 | else |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1476 | lp->options &= ~OPTION_WOL_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1477 | spin_unlock_irq(&lp->lock); |
| 1478 | return 0; |
| 1479 | } |
| 1480 | |
Jeff Garzik | 7282d49 | 2006-09-13 14:30:00 -0400 | [diff] [blame] | 1481 | static const struct ethtool_ops ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1482 | .get_drvinfo = amd8111e_get_drvinfo, |
| 1483 | .get_regs_len = amd8111e_get_regs_len, |
| 1484 | .get_regs = amd8111e_get_regs, |
| 1485 | .get_settings = amd8111e_get_settings, |
| 1486 | .set_settings = amd8111e_set_settings, |
| 1487 | .nway_reset = amd8111e_nway_reset, |
| 1488 | .get_link = amd8111e_get_link, |
| 1489 | .get_wol = amd8111e_get_wol, |
| 1490 | .set_wol = amd8111e_set_wol, |
| 1491 | }; |
| 1492 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1493 | /* This function handles all the ethtool ioctls. It gives driver info, |
| 1494 | * gets/sets driver speed, gets memory mapped register values, forces |
| 1495 | * auto negotiation, sets/gets WOL options for ethtool application. |
| 1496 | */ |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1497 | static int amd8111e_ioctl(struct net_device *dev , struct ifreq *ifr, int cmd) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1498 | { |
| 1499 | struct mii_ioctl_data *data = if_mii(ifr); |
| 1500 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1501 | int err; |
| 1502 | u32 mii_regval; |
| 1503 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1504 | switch(cmd) { |
| 1505 | case SIOCGMIIPHY: |
| 1506 | data->phy_id = lp->ext_phy_addr; |
| 1507 | |
| 1508 | /* fallthru */ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1509 | case SIOCGMIIREG: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1510 | |
| 1511 | spin_lock_irq(&lp->lock); |
| 1512 | err = amd8111e_read_phy(lp, data->phy_id, |
| 1513 | data->reg_num & PHY_REG_ADDR_MASK, &mii_regval); |
| 1514 | spin_unlock_irq(&lp->lock); |
| 1515 | |
| 1516 | data->val_out = mii_regval; |
| 1517 | return err; |
| 1518 | |
| 1519 | case SIOCSMIIREG: |
| 1520 | |
| 1521 | spin_lock_irq(&lp->lock); |
| 1522 | err = amd8111e_write_phy(lp, data->phy_id, |
| 1523 | data->reg_num & PHY_REG_ADDR_MASK, data->val_in); |
| 1524 | spin_unlock_irq(&lp->lock); |
| 1525 | |
| 1526 | return err; |
| 1527 | |
| 1528 | default: |
| 1529 | /* do nothing */ |
| 1530 | break; |
| 1531 | } |
| 1532 | return -EOPNOTSUPP; |
| 1533 | } |
| 1534 | static int amd8111e_set_mac_address(struct net_device *dev, void *p) |
| 1535 | { |
| 1536 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1537 | int i; |
| 1538 | struct sockaddr *addr = p; |
| 1539 | |
| 1540 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
| 1541 | spin_lock_irq(&lp->lock); |
| 1542 | /* Setting the MAC address to the device */ |
Joe Perches | c857ff6 | 2011-11-16 09:38:05 +0000 | [diff] [blame] | 1543 | for (i = 0; i < ETH_ALEN; i++) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1544 | writeb( dev->dev_addr[i], lp->mmio + PADR + i ); |
| 1545 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1546 | spin_unlock_irq(&lp->lock); |
| 1547 | |
| 1548 | return 0; |
| 1549 | } |
| 1550 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1551 | /* This function changes the mtu of the device. It restarts the device to |
| 1552 | * initialize the descriptor with new receive buffers. |
| 1553 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1554 | static int amd8111e_change_mtu(struct net_device *dev, int new_mtu) |
| 1555 | { |
| 1556 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1557 | int err; |
| 1558 | |
| 1559 | if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU)) |
| 1560 | return -EINVAL; |
| 1561 | |
| 1562 | if (!netif_running(dev)) { |
| 1563 | /* new_mtu will be used |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1564 | * when device starts netxt time |
| 1565 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1566 | dev->mtu = new_mtu; |
| 1567 | return 0; |
| 1568 | } |
| 1569 | |
| 1570 | spin_lock_irq(&lp->lock); |
| 1571 | |
| 1572 | /* stop the chip */ |
| 1573 | writel(RUN, lp->mmio + CMD0); |
| 1574 | |
| 1575 | dev->mtu = new_mtu; |
| 1576 | |
| 1577 | err = amd8111e_restart(dev); |
| 1578 | spin_unlock_irq(&lp->lock); |
| 1579 | if(!err) |
| 1580 | netif_start_queue(dev); |
| 1581 | return err; |
| 1582 | } |
| 1583 | |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1584 | static int amd8111e_enable_magicpkt(struct amd8111e_priv *lp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1585 | { |
| 1586 | writel( VAL1|MPPLBA, lp->mmio + CMD3); |
| 1587 | writel( VAL0|MPEN_SW, lp->mmio + CMD7); |
| 1588 | |
| 1589 | /* To eliminate PCI posting bug */ |
| 1590 | readl(lp->mmio + CMD7); |
| 1591 | return 0; |
| 1592 | } |
| 1593 | |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1594 | static int amd8111e_enable_link_change(struct amd8111e_priv *lp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1595 | { |
| 1596 | |
| 1597 | /* Adapter is already stoped/suspended/interrupt-disabled */ |
| 1598 | writel(VAL0|LCMODE_SW,lp->mmio + CMD7); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1599 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1600 | /* To eliminate PCI posting bug */ |
| 1601 | readl(lp->mmio + CMD7); |
| 1602 | return 0; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1603 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1604 | |
Varka Bhadram | 13a4fa4 | 2014-07-14 14:09:07 +0530 | [diff] [blame] | 1605 | /* This function is called when a packet transmission fails to complete |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1606 | * within a reasonable period, on the assumption that an interrupt have |
| 1607 | * failed or the interface is locked up. This function will reinitialize |
| 1608 | * the hardware. |
| 1609 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1610 | static void amd8111e_tx_timeout(struct net_device *dev) |
| 1611 | { |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1612 | struct amd8111e_priv *lp = netdev_priv(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1613 | int err; |
| 1614 | |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1615 | netdev_err(dev, "transmit timed out, resetting\n"); |
| 1616 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1617 | spin_lock_irq(&lp->lock); |
| 1618 | err = amd8111e_restart(dev); |
| 1619 | spin_unlock_irq(&lp->lock); |
| 1620 | if(!err) |
| 1621 | netif_wake_queue(dev); |
| 1622 | } |
| 1623 | static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1624 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1625 | struct net_device *dev = pci_get_drvdata(pci_dev); |
| 1626 | struct amd8111e_priv *lp = netdev_priv(dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1627 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1628 | if (!netif_running(dev)) |
| 1629 | return 0; |
| 1630 | |
| 1631 | /* disable the interrupt */ |
| 1632 | spin_lock_irq(&lp->lock); |
| 1633 | amd8111e_disable_interrupt(lp); |
| 1634 | spin_unlock_irq(&lp->lock); |
| 1635 | |
| 1636 | netif_device_detach(dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1637 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1638 | /* stop chip */ |
| 1639 | spin_lock_irq(&lp->lock); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1640 | if(lp->options & OPTION_DYN_IPG_ENABLE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1641 | del_timer_sync(&lp->ipg_data.ipg_timer); |
| 1642 | amd8111e_stop_chip(lp); |
| 1643 | spin_unlock_irq(&lp->lock); |
| 1644 | |
| 1645 | if(lp->options & OPTION_WOL_ENABLE){ |
| 1646 | /* enable wol */ |
| 1647 | if(lp->options & OPTION_WAKE_MAGIC_ENABLE) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1648 | amd8111e_enable_magicpkt(lp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1649 | if(lp->options & OPTION_WAKE_PHY_ENABLE) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1650 | amd8111e_enable_link_change(lp); |
| 1651 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1652 | pci_enable_wake(pci_dev, PCI_D3hot, 1); |
| 1653 | pci_enable_wake(pci_dev, PCI_D3cold, 1); |
| 1654 | |
| 1655 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1656 | else{ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1657 | pci_enable_wake(pci_dev, PCI_D3hot, 0); |
| 1658 | pci_enable_wake(pci_dev, PCI_D3cold, 0); |
| 1659 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1660 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1661 | pci_save_state(pci_dev); |
| 1662 | pci_set_power_state(pci_dev, PCI_D3hot); |
| 1663 | |
| 1664 | return 0; |
| 1665 | } |
| 1666 | static int amd8111e_resume(struct pci_dev *pci_dev) |
| 1667 | { |
| 1668 | struct net_device *dev = pci_get_drvdata(pci_dev); |
| 1669 | struct amd8111e_priv *lp = netdev_priv(dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1670 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1671 | if (!netif_running(dev)) |
| 1672 | return 0; |
| 1673 | |
| 1674 | pci_set_power_state(pci_dev, PCI_D0); |
| 1675 | pci_restore_state(pci_dev); |
| 1676 | |
| 1677 | pci_enable_wake(pci_dev, PCI_D3hot, 0); |
| 1678 | pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */ |
| 1679 | |
| 1680 | netif_device_attach(dev); |
| 1681 | |
| 1682 | spin_lock_irq(&lp->lock); |
| 1683 | amd8111e_restart(dev); |
| 1684 | /* Restart ipg timer */ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1685 | if(lp->options & OPTION_DYN_IPG_ENABLE) |
| 1686 | mod_timer(&lp->ipg_data.ipg_timer, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1687 | jiffies + IPG_CONVERGE_JIFFIES); |
| 1688 | spin_unlock_irq(&lp->lock); |
| 1689 | |
| 1690 | return 0; |
| 1691 | } |
| 1692 | |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1693 | static void amd8111e_config_ipg(struct net_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1694 | { |
| 1695 | struct amd8111e_priv *lp = netdev_priv(dev); |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1696 | struct ipg_info *ipg_data = &lp->ipg_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1697 | void __iomem *mmio = lp->mmio; |
| 1698 | unsigned int prev_col_cnt = ipg_data->col_cnt; |
| 1699 | unsigned int total_col_cnt; |
| 1700 | unsigned int tmp_ipg; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1701 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1702 | if(lp->link_config.duplex == DUPLEX_FULL){ |
| 1703 | ipg_data->ipg = DEFAULT_IPG; |
| 1704 | return; |
| 1705 | } |
| 1706 | |
| 1707 | if(ipg_data->ipg_state == SSTATE){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1708 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1709 | if(ipg_data->timer_tick == IPG_STABLE_TIME){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1710 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1711 | ipg_data->timer_tick = 0; |
| 1712 | ipg_data->ipg = MIN_IPG - IPG_STEP; |
| 1713 | ipg_data->current_ipg = MIN_IPG; |
| 1714 | ipg_data->diff_col_cnt = 0xFFFFFFFF; |
| 1715 | ipg_data->ipg_state = CSTATE; |
| 1716 | } |
| 1717 | else |
| 1718 | ipg_data->timer_tick++; |
| 1719 | } |
| 1720 | |
| 1721 | if(ipg_data->ipg_state == CSTATE){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1722 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1723 | /* Get the current collision count */ |
| 1724 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1725 | total_col_cnt = ipg_data->col_cnt = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1726 | amd8111e_read_mib(mmio, xmt_collisions); |
| 1727 | |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1728 | if ((total_col_cnt - prev_col_cnt) < |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1729 | (ipg_data->diff_col_cnt)){ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1730 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1731 | ipg_data->diff_col_cnt = |
| 1732 | total_col_cnt - prev_col_cnt ; |
| 1733 | |
| 1734 | ipg_data->ipg = ipg_data->current_ipg; |
| 1735 | } |
| 1736 | |
| 1737 | ipg_data->current_ipg += IPG_STEP; |
| 1738 | |
| 1739 | if (ipg_data->current_ipg <= MAX_IPG) |
| 1740 | tmp_ipg = ipg_data->current_ipg; |
| 1741 | else{ |
| 1742 | tmp_ipg = ipg_data->ipg; |
| 1743 | ipg_data->ipg_state = SSTATE; |
| 1744 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1745 | writew((u32)tmp_ipg, mmio + IPG); |
| 1746 | writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1747 | } |
| 1748 | mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES); |
| 1749 | return; |
| 1750 | |
| 1751 | } |
| 1752 | |
Bill Pemberton | 0cb0568 | 2012-12-03 09:23:54 -0500 | [diff] [blame] | 1753 | static void amd8111e_probe_ext_phy(struct net_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1754 | { |
| 1755 | struct amd8111e_priv *lp = netdev_priv(dev); |
| 1756 | int i; |
| 1757 | |
| 1758 | for (i = 0x1e; i >= 0; i--) { |
| 1759 | u32 id1, id2; |
| 1760 | |
| 1761 | if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1)) |
| 1762 | continue; |
| 1763 | if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2)) |
| 1764 | continue; |
| 1765 | lp->ext_phy_id = (id1 << 16) | id2; |
| 1766 | lp->ext_phy_addr = i; |
| 1767 | return; |
| 1768 | } |
| 1769 | lp->ext_phy_id = 0; |
| 1770 | lp->ext_phy_addr = 1; |
| 1771 | } |
| 1772 | |
Stephen Hemminger | 887e53d | 2009-01-07 18:09:58 -0800 | [diff] [blame] | 1773 | static const struct net_device_ops amd8111e_netdev_ops = { |
| 1774 | .ndo_open = amd8111e_open, |
| 1775 | .ndo_stop = amd8111e_close, |
| 1776 | .ndo_start_xmit = amd8111e_start_xmit, |
| 1777 | .ndo_tx_timeout = amd8111e_tx_timeout, |
| 1778 | .ndo_get_stats = amd8111e_get_stats, |
Jiri Pirko | afc4b13 | 2011-08-16 06:29:01 +0000 | [diff] [blame] | 1779 | .ndo_set_rx_mode = amd8111e_set_multicast_list, |
Stephen Hemminger | 887e53d | 2009-01-07 18:09:58 -0800 | [diff] [blame] | 1780 | .ndo_validate_addr = eth_validate_addr, |
| 1781 | .ndo_set_mac_address = amd8111e_set_mac_address, |
| 1782 | .ndo_do_ioctl = amd8111e_ioctl, |
| 1783 | .ndo_change_mtu = amd8111e_change_mtu, |
Stephen Hemminger | 887e53d | 2009-01-07 18:09:58 -0800 | [diff] [blame] | 1784 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1785 | .ndo_poll_controller = amd8111e_poll, |
| 1786 | #endif |
| 1787 | }; |
| 1788 | |
Bill Pemberton | 0cb0568 | 2012-12-03 09:23:54 -0500 | [diff] [blame] | 1789 | static int amd8111e_probe_one(struct pci_dev *pdev, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1790 | const struct pci_device_id *ent) |
| 1791 | { |
Yijing Wang | f9c7da5 | 2013-06-18 16:06:37 +0800 | [diff] [blame] | 1792 | int err, i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1793 | unsigned long reg_addr,reg_len; |
Varka Bhadram | 46c73ec | 2014-07-14 14:09:09 +0530 | [diff] [blame] | 1794 | struct amd8111e_priv *lp; |
| 1795 | struct net_device *dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1796 | |
| 1797 | err = pci_enable_device(pdev); |
| 1798 | if(err){ |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1799 | dev_err(&pdev->dev, "Cannot enable new PCI device\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1800 | return err; |
| 1801 | } |
| 1802 | |
| 1803 | if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){ |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1804 | dev_err(&pdev->dev, "Cannot find PCI base address\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1805 | err = -ENODEV; |
| 1806 | goto err_disable_pdev; |
| 1807 | } |
| 1808 | |
| 1809 | err = pci_request_regions(pdev, MODULE_NAME); |
| 1810 | if(err){ |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1811 | dev_err(&pdev->dev, "Cannot obtain PCI resources\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1812 | goto err_disable_pdev; |
| 1813 | } |
| 1814 | |
| 1815 | pci_set_master(pdev); |
| 1816 | |
| 1817 | /* Find power-management capability. */ |
Yijing Wang | f9c7da5 | 2013-06-18 16:06:37 +0800 | [diff] [blame] | 1818 | if (!pdev->pm_cap) { |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1819 | dev_err(&pdev->dev, "No Power Management capability\n"); |
Peter Senna Tschudin | 86e506e | 2012-10-05 12:10:51 +0000 | [diff] [blame] | 1820 | err = -ENODEV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1821 | goto err_free_reg; |
| 1822 | } |
| 1823 | |
| 1824 | /* Initialize DMA */ |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 1825 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) { |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1826 | dev_err(&pdev->dev, "DMA not supported\n"); |
Peter Senna Tschudin | 86e506e | 2012-10-05 12:10:51 +0000 | [diff] [blame] | 1827 | err = -ENODEV; |
Tobias Klauser | cac8c81 | 2005-05-16 19:15:11 +0200 | [diff] [blame] | 1828 | goto err_free_reg; |
| 1829 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1830 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1831 | reg_addr = pci_resource_start(pdev, 0); |
| 1832 | reg_len = pci_resource_len(pdev, 0); |
| 1833 | |
| 1834 | dev = alloc_etherdev(sizeof(struct amd8111e_priv)); |
| 1835 | if (!dev) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1836 | err = -ENOMEM; |
| 1837 | goto err_free_reg; |
| 1838 | } |
| 1839 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1840 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 1841 | |
| 1842 | #if AMD8111E_VLAN_TAG_USED |
Patrick McHardy | f646968 | 2013-04-19 02:04:27 +0000 | [diff] [blame] | 1843 | dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX ; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1844 | #endif |
| 1845 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1846 | lp = netdev_priv(dev); |
| 1847 | lp->pci_dev = pdev; |
| 1848 | lp->amd8111e_net_dev = dev; |
Yijing Wang | f9c7da5 | 2013-06-18 16:06:37 +0800 | [diff] [blame] | 1849 | lp->pm_cap = pdev->pm_cap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1850 | |
| 1851 | spin_lock_init(&lp->lock); |
| 1852 | |
Varka Bhadram | 711fec5 | 2014-07-14 14:09:05 +0530 | [diff] [blame] | 1853 | lp->mmio = devm_ioremap(&pdev->dev, reg_addr, reg_len); |
Al Viro | ee41a82 | 2007-08-22 21:37:46 -0400 | [diff] [blame] | 1854 | if (!lp->mmio) { |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1855 | dev_err(&pdev->dev, "Cannot map device registers\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1856 | err = -ENOMEM; |
| 1857 | goto err_free_dev; |
| 1858 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1859 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1860 | /* Initializing MAC address */ |
Joe Perches | c857ff6 | 2011-11-16 09:38:05 +0000 | [diff] [blame] | 1861 | for (i = 0; i < ETH_ALEN; i++) |
Joe Perches | 0795af5 | 2007-10-03 17:59:30 -0700 | [diff] [blame] | 1862 | dev->dev_addr[i] = readb(lp->mmio + PADR + i); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1863 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1864 | /* Setting user defined parametrs */ |
| 1865 | lp->ext_phy_option = speed_duplex[card_idx]; |
| 1866 | if(coalesce[card_idx]) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1867 | lp->options |= OPTION_INTR_COAL_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1868 | if(dynamic_ipg[card_idx++]) |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1869 | lp->options |= OPTION_DYN_IPG_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1870 | |
Stephen Hemminger | 887e53d | 2009-01-07 18:09:58 -0800 | [diff] [blame] | 1871 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1872 | /* Initialize driver entry points */ |
Stephen Hemminger | 887e53d | 2009-01-07 18:09:58 -0800 | [diff] [blame] | 1873 | dev->netdev_ops = &amd8111e_netdev_ops; |
Wilfried Klaebe | 7ad24ea | 2014-05-11 00:12:32 +0000 | [diff] [blame] | 1874 | dev->ethtool_ops = &ops; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1875 | dev->irq =pdev->irq; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1876 | dev->watchdog_timeo = AMD8111E_TX_TIMEOUT; |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 1877 | netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1878 | |
| 1879 | #if AMD8111E_VLAN_TAG_USED |
Patrick McHardy | f646968 | 2013-04-19 02:04:27 +0000 | [diff] [blame] | 1880 | dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1881 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1882 | /* Probe the external PHY */ |
| 1883 | amd8111e_probe_ext_phy(dev); |
| 1884 | |
| 1885 | /* setting mii default values */ |
| 1886 | lp->mii_if.dev = dev; |
| 1887 | lp->mii_if.mdio_read = amd8111e_mdio_read; |
| 1888 | lp->mii_if.mdio_write = amd8111e_mdio_write; |
| 1889 | lp->mii_if.phy_id = lp->ext_phy_addr; |
| 1890 | |
| 1891 | /* Set receive buffer length and set jumbo option*/ |
| 1892 | amd8111e_set_rx_buff_len(dev); |
| 1893 | |
| 1894 | |
| 1895 | err = register_netdev(dev); |
| 1896 | if (err) { |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1897 | dev_err(&pdev->dev, "Cannot register net device\n"); |
Varka Bhadram | 711fec5 | 2014-07-14 14:09:05 +0530 | [diff] [blame] | 1898 | goto err_free_dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1899 | } |
| 1900 | |
| 1901 | pci_set_drvdata(pdev, dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1902 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1903 | /* Initialize software ipg timer */ |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1904 | if(lp->options & OPTION_DYN_IPG_ENABLE){ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1905 | init_timer(&lp->ipg_data.ipg_timer); |
| 1906 | lp->ipg_data.ipg_timer.data = (unsigned long) dev; |
| 1907 | lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1908 | lp->ipg_data.ipg_timer.expires = jiffies + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1909 | IPG_CONVERGE_JIFFIES; |
| 1910 | lp->ipg_data.ipg = DEFAULT_IPG; |
| 1911 | lp->ipg_data.ipg_state = CSTATE; |
Joe Perches | 6403eab | 2011-06-03 11:51:20 +0000 | [diff] [blame] | 1912 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1913 | |
| 1914 | /* display driver and device information */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1915 | chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28; |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1916 | dev_info(&pdev->dev, "AMD-8111e Driver Version: %s\n", MODULE_VERS); |
| 1917 | dev_info(&pdev->dev, "[ Rev %x ] PCI 10/100BaseT Ethernet %pM\n", |
| 1918 | chip_version, dev->dev_addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1919 | if (lp->ext_phy_id) |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1920 | dev_info(&pdev->dev, "Found MII PHY ID 0x%08x at address 0x%02x\n", |
| 1921 | lp->ext_phy_id, lp->ext_phy_addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1922 | else |
Varka Bhadram | f7afbaa | 2014-07-14 14:09:06 +0530 | [diff] [blame] | 1923 | dev_info(&pdev->dev, "Couldn't detect MII PHY, assuming address 0x01\n"); |
| 1924 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1925 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1926 | |
| 1927 | err_free_dev: |
| 1928 | free_netdev(dev); |
| 1929 | |
| 1930 | err_free_reg: |
| 1931 | pci_release_regions(pdev); |
| 1932 | |
| 1933 | err_disable_pdev: |
| 1934 | pci_disable_device(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1935 | return err; |
| 1936 | |
| 1937 | } |
| 1938 | |
Varka Bhadram | 43519e6 | 2014-07-14 14:09:04 +0530 | [diff] [blame] | 1939 | static void amd8111e_remove_one(struct pci_dev *pdev) |
| 1940 | { |
| 1941 | struct net_device *dev = pci_get_drvdata(pdev); |
| 1942 | |
| 1943 | if (dev) { |
| 1944 | unregister_netdev(dev); |
Varka Bhadram | 43519e6 | 2014-07-14 14:09:04 +0530 | [diff] [blame] | 1945 | free_netdev(dev); |
| 1946 | pci_release_regions(pdev); |
| 1947 | pci_disable_device(pdev); |
| 1948 | } |
| 1949 | } |
| 1950 | |
Varka Bhadram | ba69a3d | 2014-07-14 14:09:08 +0530 | [diff] [blame] | 1951 | static const struct pci_device_id amd8111e_pci_tbl[] = { |
| 1952 | { |
| 1953 | .vendor = PCI_VENDOR_ID_AMD, |
| 1954 | .device = PCI_DEVICE_ID_AMD8111E_7462, |
| 1955 | }, |
| 1956 | { |
| 1957 | .vendor = 0, |
| 1958 | } |
| 1959 | }; |
| 1960 | MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl); |
| 1961 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1962 | static struct pci_driver amd8111e_driver = { |
| 1963 | .name = MODULE_NAME, |
| 1964 | .id_table = amd8111e_pci_tbl, |
| 1965 | .probe = amd8111e_probe_one, |
Bill Pemberton | 0cb0568 | 2012-12-03 09:23:54 -0500 | [diff] [blame] | 1966 | .remove = amd8111e_remove_one, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1967 | .suspend = amd8111e_suspend, |
| 1968 | .resume = amd8111e_resume |
| 1969 | }; |
| 1970 | |
Peter Hüwe | a46e6cc | 2013-05-21 12:58:10 +0000 | [diff] [blame] | 1971 | module_pci_driver(amd8111e_driver); |