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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001# SPDX-License-Identifier: GPL-2.0
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08002# Put here option for CPU selection and depending optimization
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08003choice
4 prompt "Processor family"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +01005 default M686 if X86_32
6 default GENERIC_CPU if X86_64
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08007 ---help---
H. Peter Anvineb068e72012-11-28 11:50:23 -08008 This is the processor type of your CPU. This information is
9 used for optimizing purposes. In order to compile a kernel
10 that can run on all supported x86 CPU types (albeit not
11 optimally fast), you can specify "486" here.
12
13 Note that the 386 is no longer supported, this includes
14 AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI 486DLC/DLC2,
H. Peter Anvin11af32b2012-11-29 13:28:39 -080015 UMC 486SX-S and the NexGen Nx586.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080016
17 The kernel will not necessarily run on earlier architectures than
18 the one you have chosen, e.g. a Pentium optimized kernel will run on
19 a PPro, but not necessarily on a i486.
20
21 Here are the settings recommended for greatest speed:
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080022 - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
Borislav Petkov221836e2015-10-19 10:41:17 +020023 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080024 - "586" for generic Pentium CPUs lacking the TSC
Borislav Petkov221836e2015-10-19 10:41:17 +020025 (time stamp counter) register.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080026 - "Pentium-Classic" for the Intel Pentium.
27 - "Pentium-MMX" for the Intel Pentium MMX.
28 - "Pentium-Pro" for the Intel Pentium Pro.
29 - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
30 - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
31 - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
32 - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
33 - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
Borislav Petkov221836e2015-10-19 10:41:17 +020034 - "Opteron/Athlon64/Hammer/K8" for all K8 and newer AMD CPUs.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080035 - "Crusoe" for the Transmeta Crusoe series.
36 - "Efficeon" for the Transmeta Efficeon series.
37 - "Winchip-C6" for original IDT Winchip.
Krzysztof Helt69d45dd2008-09-28 21:28:15 +020038 - "Winchip-2" for IDT Winchips with 3dNow! capabilities.
Borislav Petkov221836e2015-10-19 10:41:17 +020039 - "AMD Elan" for the 32-bit AMD Elan embedded CPU.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080040 - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
Jordan Crousef90b8112006-01-06 00:12:14 -080041 - "Geode GX/LX" For AMD Geode GX and LX processors.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080042 - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
Egry Gabor48a12042006-06-26 18:47:15 +020043 - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
Simon Arlott0949be32007-05-02 19:27:05 +020044 - "VIA C7" for VIA C7.
Borislav Petkov221836e2015-10-19 10:41:17 +020045 - "Intel P4" for the Pentium 4/Netburst microarchitecture.
46 - "Core 2/newer Xeon" for all core2 and newer Intel CPUs.
47 - "Intel Atom" for the Atom-microarchitecture CPUs.
48 - "Generic-x86-64" for a kernel which runs on any x86-64 CPU.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080049
Borislav Petkov221836e2015-10-19 10:41:17 +020050 See each option's help text for additional details. If you don't know
51 what to do, choose "486".
52
53config M486
54 bool "486"
55 depends on X86_32
56 ---help---
57 Select this for an 486-class CPU such as AMD/Cyrix/IBM/Intel
58 486DX/DX2/DX4 or SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080059
60config M586
61 bool "586/K5/5x86/6x86/6x86MX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010062 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010063 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080064 Select this for an 586 or 686 series processor such as the AMD K5,
65 the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
66 assume the RDTSC (Read Time Stamp Counter) instruction.
67
68config M586TSC
69 bool "Pentium-Classic"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010070 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010071 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080072 Select this for a Pentium Classic processor with the RDTSC (Read
73 Time Stamp Counter) instruction for benchmarking.
74
75config M586MMX
76 bool "Pentium-MMX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010077 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010078 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080079 Select this for a Pentium with the MMX graphics/multimedia
80 extended instructions.
81
82config M686
83 bool "Pentium-Pro"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010084 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010085 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080086 Select this for Intel Pentium Pro chips. This enables the use of
87 Pentium Pro extended instructions, and disables the init-time guard
88 against the f00f bug found in earlier Pentiums.
89
90config MPENTIUMII
91 bool "Pentium-II/Celeron(pre-Coppermine)"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010092 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010093 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080094 Select this for Intel chips based on the Pentium-II and
95 pre-Coppermine Celeron core. This option enables an unaligned
96 copy optimization, compiles the kernel with optimization flags
97 tailored for the chip, and applies any applicable Pentium Pro
98 optimizations.
99
100config MPENTIUMIII
101 bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100102 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100103 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800104 Select this for Intel chips based on the Pentium-III and
105 Celeron-Coppermine core. This option enables use of some
106 extended prefetch instructions in addition to the Pentium II
107 extensions.
108
109config MPENTIUMM
110 bool "Pentium M"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100111 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100112 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800113 Select this for Intel Pentium M (not Pentium-4 M)
114 notebook chips.
115
116config MPENTIUM4
Andi Kleenc55d92d2006-12-07 02:14:09 +0100117 bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100118 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100119 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800120 Select this for Intel Pentium 4 chips. This includes the
Oliver Pinter75e38082007-10-17 18:04:36 +0200121 Pentium 4, Pentium D, P4-based Celeron and Xeon, and
122 Pentium-4 M (not Pentium M) chips. This option enables compile
123 flags optimized for the chip, uses the correct cache line size, and
124 applies any applicable optimizations.
125
126 CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )
127
128 Select this for:
129 Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
130 -Willamette
131 -Northwood
132 -Mobile Pentium 4
133 -Mobile Pentium 4 M
134 -Extreme Edition (Gallatin)
135 -Prescott
136 -Prescott 2M
137 -Cedar Mill
138 -Presler
139 -Smithfiled
140 Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
141 -Foster
142 -Prestonia
143 -Gallatin
144 -Nocona
145 -Irwindale
146 -Cranford
147 -Potomac
148 -Paxville
149 -Dempsey
150
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800151
152config MK6
153 bool "K6/K6-II/K6-III"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100154 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100155 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800156 Select this for an AMD K6-family processor. Enables use of
157 some extended instructions, and passes appropriate optimization
158 flags to GCC.
159
160config MK7
161 bool "Athlon/Duron/K7"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100162 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100163 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800164 Select this for an AMD Athlon K7-family processor. Enables use of
165 some extended instructions, and passes appropriate optimization
166 flags to GCC.
167
168config MK8
169 bool "Opteron/Athlon64/Hammer/K8"
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100170 ---help---
Borislav Petkov36723bf2009-02-04 21:44:04 +0100171 Select this for an AMD Opteron or Athlon64 Hammer-family processor.
172 Enables use of some extended instructions, and passes appropriate
173 optimization flags to GCC.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800174
175config MCRUSOE
176 bool "Crusoe"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100177 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100178 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800179 Select this for a Transmeta Crusoe processor. Treats the processor
180 like a 586 with TSC, and sets some GCC optimization flags (like a
181 Pentium Pro with no alignment requirements).
182
183config MEFFICEON
184 bool "Efficeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100185 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100186 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800187 Select this for a Transmeta Efficeon processor.
188
189config MWINCHIPC6
190 bool "Winchip-C6"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100191 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100192 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800193 Select this for an IDT Winchip C6 chip. Linux and GCC
194 treat this chip as a 586TSC with some extended instructions
195 and alignment requirements.
196
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800197config MWINCHIP3D
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200198 bool "Winchip-2/Winchip-2A/Winchip-3"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100199 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100200 ---help---
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200201 Select this for an IDT Winchip-2, 2A or 3. Linux and GCC
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800202 treat this chip as a 586TSC with some extended instructions
David Sterba3dde6ad2007-05-09 07:12:20 +0200203 and alignment requirements. Also enable out of order memory
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800204 stores for this CPU, which can increase performance of some
205 operations.
206
Ian Campbellce9c99a2011-04-08 07:42:29 +0100207config MELAN
208 bool "AMD Elan"
209 depends on X86_32
210 ---help---
211 Select this for an AMD Elan processor.
212
213 Do not use this option for K6/Athlon/Opteron processors!
214
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800215config MGEODEGX1
216 bool "GeodeGX1"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100217 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100218 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800219 Select this for a Geode GX1 (Cyrix MediaGX) chip.
220
Jordan Crousef90b8112006-01-06 00:12:14 -0800221config MGEODE_LX
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100222 bool "Geode GX/LX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100223 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100224 ---help---
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100225 Select this for AMD Geode GX and LX processors.
Jordan Crousef90b8112006-01-06 00:12:14 -0800226
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800227config MCYRIXIII
228 bool "CyrixIII/VIA-C3"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100229 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100230 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800231 Select this for a Cyrix III or C3 chip. Presently Linux and GCC
232 treat this chip as a generic 586. Whilst the CPU is 686 class,
233 it lacks the cmov extension which gcc assumes is present when
234 generating 686 code.
235 Note that Nehemiah (Model 9) and above will not boot with this
236 kernel due to them lacking the 3DNow! instructions used in earlier
237 incarnations of the CPU.
238
239config MVIAC3_2
240 bool "VIA C3-2 (Nehemiah)"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100241 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100242 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800243 Select this for a VIA C3 "Nehemiah". Selecting this enables usage
244 of SSE and tells gcc to treat the CPU as a 686.
245 Note, this kernel will not boot on older (pre model 9) C3s.
246
Simon Arlott0949be32007-05-02 19:27:05 +0200247config MVIAC7
248 bool "VIA C7"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100249 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100250 ---help---
Simon Arlott0949be32007-05-02 19:27:05 +0200251 Select this for a VIA C7. Selecting this uses the correct cache
252 shift and tells gcc to treat the CPU as a 686.
253
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100254config MPSC
255 bool "Intel P4 / older Netburst based Xeon"
256 depends on X86_64
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100257 ---help---
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100258 Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
259 Xeon CPUs with Intel 64bit which is compatible with x86-64.
260 Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100261 Netburst core and shouldn't use this option. You can distinguish them
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100262 using the cpu family field
263 in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
264
265config MCORE2
266 bool "Core 2/newer Xeon"
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100267 ---help---
Borislav Petkov36723bf2009-02-04 21:44:04 +0100268
269 Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
270 53xx) CPUs. You can distinguish newer from older Xeons by the CPU
271 family in /proc/cpuinfo. Newer ones have 6 and older ones 15
272 (not a typo)
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100273
Tobias Doerffel366d19e2009-08-21 23:06:23 +0200274config MATOM
275 bool "Intel Atom"
276 ---help---
277
278 Select this for the Intel Atom platform. Intel Atom CPUs have an
279 in-order pipelining architecture and thus can benefit from
280 accordingly optimized code. Use a recent GCC with specific Atom
281 support in order to fully benefit from selecting this option.
282
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100283config GENERIC_CPU
284 bool "Generic-x86-64"
285 depends on X86_64
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100286 ---help---
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100287 Generic x86-64 CPU.
288 Run equally well on all x86-64 CPUs.
289
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800290endchoice
291
292config X86_GENERIC
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100293 bool "Generic x86 support"
294 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100295 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800296 Instead of just including optimizations for the selected
297 x86 variant (e.g. PII, Crusoe or Athlon), include some more
298 generic optimizations as well. This will make the kernel
299 perform better on x86 CPUs other than that selected.
300
301 This is really intended for distributors who need more
302 generic optimizations.
303
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800304#
305# Define implied options from the CPU selection here
Jan Beulich350f8f52009-11-13 11:54:40 +0000306config X86_INTERNODE_CACHE_SHIFT
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100307 int
Jan Beulich350f8f52009-11-13 11:54:40 +0000308 default "12" if X86_VSMP
Jan Beulich350f8f52009-11-13 11:54:40 +0000309 default X86_L1_CACHE_SHIFT
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100310
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800311config X86_L1_CACHE_SHIFT
312 int
Ingo Molnar0a2a18b72009-01-12 23:37:16 +0100313 default "7" if MPENTIUM4 || MPSC
Jan Beulich350f8f52009-11-13 11:54:40 +0000314 default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
H. Peter Anvineb068e72012-11-28 11:50:23 -0800315 default "4" if MELAN || M486 || MGEODEGX1
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200316 default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800317
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800318config X86_PPRO_FENCE
Nick Pigginfb0328e2008-01-30 13:32:31 +0100319 bool "PentiumPro memory ordering errata workaround"
H. Peter Anvineb068e72012-11-28 11:50:23 -0800320 depends on M686 || M586MMX || M586TSC || M586 || M486 || MGEODEGX1
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100321 ---help---
Borislav Petkov36723bf2009-02-04 21:44:04 +0100322 Old PentiumPro multiprocessor systems had errata that could cause
323 memory operations to violate the x86 ordering standard in rare cases.
324 Enabling this option will attempt to work around some (but not all)
Lucas De Marchi0d2eb442011-03-17 16:24:16 -0300325 occurrences of this problem, at the cost of much heavier spinlock and
Borislav Petkov36723bf2009-02-04 21:44:04 +0100326 memory barrier operations.
Nick Pigginfb0328e2008-01-30 13:32:31 +0100327
Borislav Petkov36723bf2009-02-04 21:44:04 +0100328 If unsure, say n here. Even distro kernels should think twice before
329 enabling this: there are few systems, and an unlikely bug.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800330
331config X86_F00F_BUG
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100332 def_bool y
H. Peter Anvineb068e72012-11-28 11:50:23 -0800333 depends on M586MMX || M586TSC || M586 || M486
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800334
Brian Gerst40d2e762010-03-21 09:00:43 -0400335config X86_INVD_BUG
336 def_bool y
H. Peter Anvineb068e72012-11-28 11:50:23 -0800337 depends on M486
Brian Gerst40d2e762010-03-21 09:00:43 -0400338
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800339config X86_ALIGNMENT_16
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100340 def_bool y
Ian Campbellce9c99a2011-04-08 07:42:29 +0100341 depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800342
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800343config X86_INTEL_USERCOPY
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100344 def_bool y
Andi Kleenc55d92d2006-12-07 02:14:09 +0100345 depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800346
347config X86_USE_PPRO_CHECKSUM
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100348 def_bool y
Jon Nettleton1eda75c2011-03-16 15:32:47 +0000349 depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800350
351config X86_USE_3DNOW
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100352 def_bool y
Paolo 'Blaisorblade' Giarrusso1b4ad242006-10-11 01:21:35 -0700353 depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800354
H. Peter Anvin959b3be2008-02-14 14:56:45 -0800355#
356# P6_NOPs are a relatively minor optimization that require a family >=
357# 6 processor, except that it is broken on certain VIA chips.
358# Furthermore, AMD chips prefer a totally different sequence of NOPs
Linus Torvalds14469a82008-09-05 09:30:14 -0700359# (which work on all CPUs). In addition, it looks like Virtual PC
360# does not understand them.
361#
362# As a result, disallow these if we're not compiling for X86_64 (these
363# NOPs do work on all x86-64 capable chips); the list of processors in
364# the right-hand clause are the cores that benefit from this optimization.
H. Peter Anvin959b3be2008-02-14 14:56:45 -0800365#
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800366config X86_P6_NOP
367 def_bool y
Linus Torvalds14469a82008-09-05 09:30:14 -0700368 depends on X86_64
369 depends on (MCORE2 || MPENTIUM4 || MPSC)
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800370
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800371config X86_TSC
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100372 def_bool y
H. Peter Anvinb5660ba2014-02-25 12:14:06 -0800373 depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
Andi Kleenc7f81c92007-05-02 19:27:20 +0200374
Jan Beulichf8096f92008-04-22 16:27:29 +0100375config X86_CMPXCHG64
376 def_bool y
Rusty Russelldb677ff2010-01-05 12:48:49 +1030377 depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MATOM
Jan Beulichf8096f92008-04-22 16:27:29 +0100378
Andi Kleenc7f81c92007-05-02 19:27:20 +0200379# this should be set for all -march=.. options where the compiler
380# generates cmov.
381config X86_CMOV
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100382 def_bool y
Matteo Croce98059e32009-10-01 17:11:10 +0200383 depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX)
Andi Kleenc7f81c92007-05-02 19:27:20 +0200384
H. Peter Anvinde32e042007-07-11 12:18:30 -0700385config X86_MINIMUM_CPU_FAMILY
Andi Kleenc7f81c92007-05-02 19:27:20 +0200386 int
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100387 default "64" if X86_64
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800388 default "6" if X86_32 && X86_P6_NOP
Linus Torvalds982d0072009-09-30 17:57:27 -0700389 default "5" if X86_32 && X86_CMPXCHG64
H. Peter Anvineb068e72012-11-28 11:50:23 -0800390 default "4"
Andi Kleenc7f81c92007-05-02 19:27:20 +0200391
Roland McGrath0a049bb2008-01-30 13:30:54 +0100392config X86_DEBUGCTLMSR
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100393 def_bool y
H. Peter Anvineb068e72012-11-28 11:50:23 -0800394 depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486) && !UML
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200395
396menuconfig PROCESSOR_SELECT
David Rientjes6a108a12011-01-20 14:44:16 -0800397 bool "Supported processor vendors" if EXPERT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100398 ---help---
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200399 This lets you choose what x86 vendor support code your kernel
400 will include.
401
Yinghai Lu879d7922008-09-09 16:40:37 -0700402config CPU_SUP_INTEL
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200403 default y
404 bool "Support Intel processors" if PROCESSOR_SELECT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100405 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200406 This enables detection, tunings and quirks for Intel processors
407
408 You need this enabled if you want your kernel to run on an
409 Intel CPU. Disabling this option on other types of CPUs
410 makes the kernel a tiny bit smaller. Disabling it on an Intel
411 CPU might render the kernel unbootable.
412
413 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200414
415config CPU_SUP_CYRIX_32
416 default y
417 bool "Support Cyrix processors" if PROCESSOR_SELECT
H. Peter Anvineb068e72012-11-28 11:50:23 -0800418 depends on M486 || M586 || M586TSC || M586MMX || (EXPERT && !64BIT)
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100419 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200420 This enables detection, tunings and quirks for Cyrix processors
421
422 You need this enabled if you want your kernel to run on a
423 Cyrix CPU. Disabling this option on other types of CPUs
424 makes the kernel a tiny bit smaller. Disabling it on a Cyrix
425 CPU might render the kernel unbootable.
426
427 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200428
Yinghai Luff731522008-09-07 17:58:56 -0700429config CPU_SUP_AMD
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200430 default y
431 bool "Support AMD processors" if PROCESSOR_SELECT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100432 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200433 This enables detection, tunings and quirks for AMD processors
434
435 You need this enabled if you want your kernel to run on an
436 AMD CPU. Disabling this option on other types of CPUs
437 makes the kernel a tiny bit smaller. Disabling it on an AMD
438 CPU might render the kernel unbootable.
439
440 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200441
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100442config CPU_SUP_CENTAUR
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200443 default y
444 bool "Support Centaur processors" if PROCESSOR_SELECT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100445 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200446 This enables detection, tunings and quirks for Centaur processors
447
448 You need this enabled if you want your kernel to run on a
449 Centaur CPU. Disabling this option on other types of CPUs
450 makes the kernel a tiny bit smaller. Disabling it on a Centaur
451 CPU might render the kernel unbootable.
452
453 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200454
455config CPU_SUP_TRANSMETA_32
456 default y
457 bool "Support Transmeta processors" if PROCESSOR_SELECT
458 depends on !64BIT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100459 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200460 This enables detection, tunings and quirks for Transmeta processors
461
462 You need this enabled if you want your kernel to run on a
463 Transmeta CPU. Disabling this option on other types of CPUs
464 makes the kernel a tiny bit smaller. Disabling it on a Transmeta
465 CPU might render the kernel unbootable.
466
467 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200468
469config CPU_SUP_UMC_32
470 default y
471 bool "Support UMC processors" if PROCESSOR_SELECT
H. Peter Anvineb068e72012-11-28 11:50:23 -0800472 depends on M486 || (EXPERT && !64BIT)
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100473 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200474 This enables detection, tunings and quirks for UMC processors
475
476 You need this enabled if you want your kernel to run on a
477 UMC CPU. Disabling this option on other types of CPUs
478 makes the kernel a tiny bit smaller. Disabling it on a UMC
479 CPU might render the kernel unbootable.
480
481 If unsure, say N.