Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 2 | # Put here option for CPU selection and depending optimization |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 3 | choice |
| 4 | prompt "Processor family" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 5 | default M686 if X86_32 |
| 6 | default GENERIC_CPU if X86_64 |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 7 | ---help--- |
H. Peter Anvin | eb068e7 | 2012-11-28 11:50:23 -0800 | [diff] [blame] | 8 | This is the processor type of your CPU. This information is |
| 9 | used for optimizing purposes. In order to compile a kernel |
| 10 | that can run on all supported x86 CPU types (albeit not |
| 11 | optimally fast), you can specify "486" here. |
| 12 | |
| 13 | Note that the 386 is no longer supported, this includes |
| 14 | AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI 486DLC/DLC2, |
H. Peter Anvin | 11af32b | 2012-11-29 13:28:39 -0800 | [diff] [blame] | 15 | UMC 486SX-S and the NexGen Nx586. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 16 | |
| 17 | The kernel will not necessarily run on earlier architectures than |
| 18 | the one you have chosen, e.g. a Pentium optimized kernel will run on |
| 19 | a PPro, but not necessarily on a i486. |
| 20 | |
| 21 | Here are the settings recommended for greatest speed: |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 22 | - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or |
Borislav Petkov | 221836e | 2015-10-19 10:41:17 +0200 | [diff] [blame] | 23 | SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 24 | - "586" for generic Pentium CPUs lacking the TSC |
Borislav Petkov | 221836e | 2015-10-19 10:41:17 +0200 | [diff] [blame] | 25 | (time stamp counter) register. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 26 | - "Pentium-Classic" for the Intel Pentium. |
| 27 | - "Pentium-MMX" for the Intel Pentium MMX. |
| 28 | - "Pentium-Pro" for the Intel Pentium Pro. |
| 29 | - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron. |
| 30 | - "Pentium-III" for the Intel Pentium III or Coppermine Celeron. |
| 31 | - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. |
| 32 | - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). |
| 33 | - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). |
Borislav Petkov | 221836e | 2015-10-19 10:41:17 +0200 | [diff] [blame] | 34 | - "Opteron/Athlon64/Hammer/K8" for all K8 and newer AMD CPUs. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 35 | - "Crusoe" for the Transmeta Crusoe series. |
| 36 | - "Efficeon" for the Transmeta Efficeon series. |
| 37 | - "Winchip-C6" for original IDT Winchip. |
Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 38 | - "Winchip-2" for IDT Winchips with 3dNow! capabilities. |
Borislav Petkov | 221836e | 2015-10-19 10:41:17 +0200 | [diff] [blame] | 39 | - "AMD Elan" for the 32-bit AMD Elan embedded CPU. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 40 | - "GeodeGX1" for Geode GX1 (Cyrix MediaGX). |
Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 41 | - "Geode GX/LX" For AMD Geode GX and LX processors. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 42 | - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. |
Egry Gabor | 48a1204 | 2006-06-26 18:47:15 +0200 | [diff] [blame] | 43 | - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). |
Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 44 | - "VIA C7" for VIA C7. |
Borislav Petkov | 221836e | 2015-10-19 10:41:17 +0200 | [diff] [blame] | 45 | - "Intel P4" for the Pentium 4/Netburst microarchitecture. |
| 46 | - "Core 2/newer Xeon" for all core2 and newer Intel CPUs. |
| 47 | - "Intel Atom" for the Atom-microarchitecture CPUs. |
| 48 | - "Generic-x86-64" for a kernel which runs on any x86-64 CPU. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 49 | |
Borislav Petkov | 221836e | 2015-10-19 10:41:17 +0200 | [diff] [blame] | 50 | See each option's help text for additional details. If you don't know |
| 51 | what to do, choose "486". |
| 52 | |
| 53 | config M486 |
| 54 | bool "486" |
| 55 | depends on X86_32 |
| 56 | ---help--- |
| 57 | Select this for an 486-class CPU such as AMD/Cyrix/IBM/Intel |
| 58 | 486DX/DX2/DX4 or SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 59 | |
| 60 | config M586 |
| 61 | bool "586/K5/5x86/6x86/6x86MX" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 62 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 63 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 64 | Select this for an 586 or 686 series processor such as the AMD K5, |
| 65 | the Cyrix 5x86, 6x86 and 6x86MX. This choice does not |
| 66 | assume the RDTSC (Read Time Stamp Counter) instruction. |
| 67 | |
| 68 | config M586TSC |
| 69 | bool "Pentium-Classic" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 70 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 71 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 72 | Select this for a Pentium Classic processor with the RDTSC (Read |
| 73 | Time Stamp Counter) instruction for benchmarking. |
| 74 | |
| 75 | config M586MMX |
| 76 | bool "Pentium-MMX" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 77 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 78 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 79 | Select this for a Pentium with the MMX graphics/multimedia |
| 80 | extended instructions. |
| 81 | |
| 82 | config M686 |
| 83 | bool "Pentium-Pro" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 84 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 85 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 86 | Select this for Intel Pentium Pro chips. This enables the use of |
| 87 | Pentium Pro extended instructions, and disables the init-time guard |
| 88 | against the f00f bug found in earlier Pentiums. |
| 89 | |
| 90 | config MPENTIUMII |
| 91 | bool "Pentium-II/Celeron(pre-Coppermine)" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 92 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 93 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 94 | Select this for Intel chips based on the Pentium-II and |
| 95 | pre-Coppermine Celeron core. This option enables an unaligned |
| 96 | copy optimization, compiles the kernel with optimization flags |
| 97 | tailored for the chip, and applies any applicable Pentium Pro |
| 98 | optimizations. |
| 99 | |
| 100 | config MPENTIUMIII |
| 101 | bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 102 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 103 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 104 | Select this for Intel chips based on the Pentium-III and |
| 105 | Celeron-Coppermine core. This option enables use of some |
| 106 | extended prefetch instructions in addition to the Pentium II |
| 107 | extensions. |
| 108 | |
| 109 | config MPENTIUMM |
| 110 | bool "Pentium M" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 111 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 112 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 113 | Select this for Intel Pentium M (not Pentium-4 M) |
| 114 | notebook chips. |
| 115 | |
| 116 | config MPENTIUM4 |
Andi Kleen | c55d92d | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 117 | bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 118 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 119 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 120 | Select this for Intel Pentium 4 chips. This includes the |
Oliver Pinter | 75e3808 | 2007-10-17 18:04:36 +0200 | [diff] [blame] | 121 | Pentium 4, Pentium D, P4-based Celeron and Xeon, and |
| 122 | Pentium-4 M (not Pentium M) chips. This option enables compile |
| 123 | flags optimized for the chip, uses the correct cache line size, and |
| 124 | applies any applicable optimizations. |
| 125 | |
| 126 | CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 ) |
| 127 | |
| 128 | Select this for: |
| 129 | Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename: |
| 130 | -Willamette |
| 131 | -Northwood |
| 132 | -Mobile Pentium 4 |
| 133 | -Mobile Pentium 4 M |
| 134 | -Extreme Edition (Gallatin) |
| 135 | -Prescott |
| 136 | -Prescott 2M |
| 137 | -Cedar Mill |
| 138 | -Presler |
| 139 | -Smithfiled |
| 140 | Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename: |
| 141 | -Foster |
| 142 | -Prestonia |
| 143 | -Gallatin |
| 144 | -Nocona |
| 145 | -Irwindale |
| 146 | -Cranford |
| 147 | -Potomac |
| 148 | -Paxville |
| 149 | -Dempsey |
| 150 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 151 | |
| 152 | config MK6 |
| 153 | bool "K6/K6-II/K6-III" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 154 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 155 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 156 | Select this for an AMD K6-family processor. Enables use of |
| 157 | some extended instructions, and passes appropriate optimization |
| 158 | flags to GCC. |
| 159 | |
| 160 | config MK7 |
| 161 | bool "Athlon/Duron/K7" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 162 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 163 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 164 | Select this for an AMD Athlon K7-family processor. Enables use of |
| 165 | some extended instructions, and passes appropriate optimization |
| 166 | flags to GCC. |
| 167 | |
| 168 | config MK8 |
| 169 | bool "Opteron/Athlon64/Hammer/K8" |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 170 | ---help--- |
Borislav Petkov | 36723bf | 2009-02-04 21:44:04 +0100 | [diff] [blame] | 171 | Select this for an AMD Opteron or Athlon64 Hammer-family processor. |
| 172 | Enables use of some extended instructions, and passes appropriate |
| 173 | optimization flags to GCC. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 174 | |
| 175 | config MCRUSOE |
| 176 | bool "Crusoe" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 177 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 178 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 179 | Select this for a Transmeta Crusoe processor. Treats the processor |
| 180 | like a 586 with TSC, and sets some GCC optimization flags (like a |
| 181 | Pentium Pro with no alignment requirements). |
| 182 | |
| 183 | config MEFFICEON |
| 184 | bool "Efficeon" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 185 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 186 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 187 | Select this for a Transmeta Efficeon processor. |
| 188 | |
| 189 | config MWINCHIPC6 |
| 190 | bool "Winchip-C6" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 191 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 192 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 193 | Select this for an IDT Winchip C6 chip. Linux and GCC |
| 194 | treat this chip as a 586TSC with some extended instructions |
| 195 | and alignment requirements. |
| 196 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 197 | config MWINCHIP3D |
Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 198 | bool "Winchip-2/Winchip-2A/Winchip-3" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 199 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 200 | ---help--- |
Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 201 | Select this for an IDT Winchip-2, 2A or 3. Linux and GCC |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 202 | treat this chip as a 586TSC with some extended instructions |
David Sterba | 3dde6ad | 2007-05-09 07:12:20 +0200 | [diff] [blame] | 203 | and alignment requirements. Also enable out of order memory |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 204 | stores for this CPU, which can increase performance of some |
| 205 | operations. |
| 206 | |
Ian Campbell | ce9c99a | 2011-04-08 07:42:29 +0100 | [diff] [blame] | 207 | config MELAN |
| 208 | bool "AMD Elan" |
| 209 | depends on X86_32 |
| 210 | ---help--- |
| 211 | Select this for an AMD Elan processor. |
| 212 | |
| 213 | Do not use this option for K6/Athlon/Opteron processors! |
| 214 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 215 | config MGEODEGX1 |
| 216 | bool "GeodeGX1" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 217 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 218 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 219 | Select this for a Geode GX1 (Cyrix MediaGX) chip. |
| 220 | |
Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 221 | config MGEODE_LX |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 222 | bool "Geode GX/LX" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 223 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 224 | ---help--- |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 225 | Select this for AMD Geode GX and LX processors. |
Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 226 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 227 | config MCYRIXIII |
| 228 | bool "CyrixIII/VIA-C3" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 229 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 230 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 231 | Select this for a Cyrix III or C3 chip. Presently Linux and GCC |
| 232 | treat this chip as a generic 586. Whilst the CPU is 686 class, |
| 233 | it lacks the cmov extension which gcc assumes is present when |
| 234 | generating 686 code. |
| 235 | Note that Nehemiah (Model 9) and above will not boot with this |
| 236 | kernel due to them lacking the 3DNow! instructions used in earlier |
| 237 | incarnations of the CPU. |
| 238 | |
| 239 | config MVIAC3_2 |
| 240 | bool "VIA C3-2 (Nehemiah)" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 241 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 242 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 243 | Select this for a VIA C3 "Nehemiah". Selecting this enables usage |
| 244 | of SSE and tells gcc to treat the CPU as a 686. |
| 245 | Note, this kernel will not boot on older (pre model 9) C3s. |
| 246 | |
Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 247 | config MVIAC7 |
| 248 | bool "VIA C7" |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 249 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 250 | ---help--- |
Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 251 | Select this for a VIA C7. Selecting this uses the correct cache |
| 252 | shift and tells gcc to treat the CPU as a 686. |
| 253 | |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 254 | config MPSC |
| 255 | bool "Intel P4 / older Netburst based Xeon" |
| 256 | depends on X86_64 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 257 | ---help--- |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 258 | Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey |
| 259 | Xeon CPUs with Intel 64bit which is compatible with x86-64. |
| 260 | Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 261 | Netburst core and shouldn't use this option. You can distinguish them |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 262 | using the cpu family field |
| 263 | in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. |
| 264 | |
| 265 | config MCORE2 |
| 266 | bool "Core 2/newer Xeon" |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 267 | ---help--- |
Borislav Petkov | 36723bf | 2009-02-04 21:44:04 +0100 | [diff] [blame] | 268 | |
| 269 | Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and |
| 270 | 53xx) CPUs. You can distinguish newer from older Xeons by the CPU |
| 271 | family in /proc/cpuinfo. Newer ones have 6 and older ones 15 |
| 272 | (not a typo) |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 273 | |
Tobias Doerffel | 366d19e | 2009-08-21 23:06:23 +0200 | [diff] [blame] | 274 | config MATOM |
| 275 | bool "Intel Atom" |
| 276 | ---help--- |
| 277 | |
| 278 | Select this for the Intel Atom platform. Intel Atom CPUs have an |
| 279 | in-order pipelining architecture and thus can benefit from |
| 280 | accordingly optimized code. Use a recent GCC with specific Atom |
| 281 | support in order to fully benefit from selecting this option. |
| 282 | |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 283 | config GENERIC_CPU |
| 284 | bool "Generic-x86-64" |
| 285 | depends on X86_64 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 286 | ---help--- |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 287 | Generic x86-64 CPU. |
| 288 | Run equally well on all x86-64 CPUs. |
| 289 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 290 | endchoice |
| 291 | |
| 292 | config X86_GENERIC |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 293 | bool "Generic x86 support" |
| 294 | depends on X86_32 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 295 | ---help--- |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 296 | Instead of just including optimizations for the selected |
| 297 | x86 variant (e.g. PII, Crusoe or Athlon), include some more |
| 298 | generic optimizations as well. This will make the kernel |
| 299 | perform better on x86 CPUs other than that selected. |
| 300 | |
| 301 | This is really intended for distributors who need more |
| 302 | generic optimizations. |
| 303 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 304 | # |
| 305 | # Define implied options from the CPU selection here |
Jan Beulich | 350f8f5 | 2009-11-13 11:54:40 +0000 | [diff] [blame] | 306 | config X86_INTERNODE_CACHE_SHIFT |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 307 | int |
Jan Beulich | 350f8f5 | 2009-11-13 11:54:40 +0000 | [diff] [blame] | 308 | default "12" if X86_VSMP |
Jan Beulich | 350f8f5 | 2009-11-13 11:54:40 +0000 | [diff] [blame] | 309 | default X86_L1_CACHE_SHIFT |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 310 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 311 | config X86_L1_CACHE_SHIFT |
| 312 | int |
Ingo Molnar | 0a2a18b7 | 2009-01-12 23:37:16 +0100 | [diff] [blame] | 313 | default "7" if MPENTIUM4 || MPSC |
Jan Beulich | 350f8f5 | 2009-11-13 11:54:40 +0000 | [diff] [blame] | 314 | default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
H. Peter Anvin | eb068e7 | 2012-11-28 11:50:23 -0800 | [diff] [blame] | 315 | default "4" if MELAN || M486 || MGEODEGX1 |
Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 316 | default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 317 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 318 | config X86_PPRO_FENCE |
Nick Piggin | fb0328e | 2008-01-30 13:32:31 +0100 | [diff] [blame] | 319 | bool "PentiumPro memory ordering errata workaround" |
H. Peter Anvin | eb068e7 | 2012-11-28 11:50:23 -0800 | [diff] [blame] | 320 | depends on M686 || M586MMX || M586TSC || M586 || M486 || MGEODEGX1 |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 321 | ---help--- |
Borislav Petkov | 36723bf | 2009-02-04 21:44:04 +0100 | [diff] [blame] | 322 | Old PentiumPro multiprocessor systems had errata that could cause |
| 323 | memory operations to violate the x86 ordering standard in rare cases. |
| 324 | Enabling this option will attempt to work around some (but not all) |
Lucas De Marchi | 0d2eb44 | 2011-03-17 16:24:16 -0300 | [diff] [blame] | 325 | occurrences of this problem, at the cost of much heavier spinlock and |
Borislav Petkov | 36723bf | 2009-02-04 21:44:04 +0100 | [diff] [blame] | 326 | memory barrier operations. |
Nick Piggin | fb0328e | 2008-01-30 13:32:31 +0100 | [diff] [blame] | 327 | |
Borislav Petkov | 36723bf | 2009-02-04 21:44:04 +0100 | [diff] [blame] | 328 | If unsure, say n here. Even distro kernels should think twice before |
| 329 | enabling this: there are few systems, and an unlikely bug. |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 330 | |
| 331 | config X86_F00F_BUG |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 332 | def_bool y |
H. Peter Anvin | eb068e7 | 2012-11-28 11:50:23 -0800 | [diff] [blame] | 333 | depends on M586MMX || M586TSC || M586 || M486 |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 334 | |
Brian Gerst | 40d2e76 | 2010-03-21 09:00:43 -0400 | [diff] [blame] | 335 | config X86_INVD_BUG |
| 336 | def_bool y |
H. Peter Anvin | eb068e7 | 2012-11-28 11:50:23 -0800 | [diff] [blame] | 337 | depends on M486 |
Brian Gerst | 40d2e76 | 2010-03-21 09:00:43 -0400 | [diff] [blame] | 338 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 339 | config X86_ALIGNMENT_16 |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 340 | def_bool y |
Ian Campbell | ce9c99a | 2011-04-08 07:42:29 +0100 | [diff] [blame] | 341 | depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1 |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 342 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 343 | config X86_INTEL_USERCOPY |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 344 | def_bool y |
Andi Kleen | c55d92d | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 345 | depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 346 | |
| 347 | config X86_USE_PPRO_CHECKSUM |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 348 | def_bool y |
Jon Nettleton | 1eda75c | 2011-03-16 15:32:47 +0000 | [diff] [blame] | 349 | depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 350 | |
| 351 | config X86_USE_3DNOW |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 352 | def_bool y |
Paolo 'Blaisorblade' Giarrusso | 1b4ad24 | 2006-10-11 01:21:35 -0700 | [diff] [blame] | 353 | depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 354 | |
H. Peter Anvin | 959b3be | 2008-02-14 14:56:45 -0800 | [diff] [blame] | 355 | # |
| 356 | # P6_NOPs are a relatively minor optimization that require a family >= |
| 357 | # 6 processor, except that it is broken on certain VIA chips. |
| 358 | # Furthermore, AMD chips prefer a totally different sequence of NOPs |
Linus Torvalds | 14469a8 | 2008-09-05 09:30:14 -0700 | [diff] [blame] | 359 | # (which work on all CPUs). In addition, it looks like Virtual PC |
| 360 | # does not understand them. |
| 361 | # |
| 362 | # As a result, disallow these if we're not compiling for X86_64 (these |
| 363 | # NOPs do work on all x86-64 capable chips); the list of processors in |
| 364 | # the right-hand clause are the cores that benefit from this optimization. |
H. Peter Anvin | 959b3be | 2008-02-14 14:56:45 -0800 | [diff] [blame] | 365 | # |
H. Peter Anvin | 7343b3b | 2008-02-14 14:52:05 -0800 | [diff] [blame] | 366 | config X86_P6_NOP |
| 367 | def_bool y |
Linus Torvalds | 14469a8 | 2008-09-05 09:30:14 -0700 | [diff] [blame] | 368 | depends on X86_64 |
| 369 | depends on (MCORE2 || MPENTIUM4 || MPSC) |
H. Peter Anvin | 7343b3b | 2008-02-14 14:52:05 -0800 | [diff] [blame] | 370 | |
Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 371 | config X86_TSC |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 372 | def_bool y |
H. Peter Anvin | b5660ba | 2014-02-25 12:14:06 -0800 | [diff] [blame] | 373 | depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64 |
Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 374 | |
Jan Beulich | f8096f9 | 2008-04-22 16:27:29 +0100 | [diff] [blame] | 375 | config X86_CMPXCHG64 |
| 376 | def_bool y |
Rusty Russell | db677ff | 2010-01-05 12:48:49 +1030 | [diff] [blame] | 377 | depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MATOM |
Jan Beulich | f8096f9 | 2008-04-22 16:27:29 +0100 | [diff] [blame] | 378 | |
Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 379 | # this should be set for all -march=.. options where the compiler |
| 380 | # generates cmov. |
| 381 | config X86_CMOV |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 382 | def_bool y |
Matteo Croce | 98059e3 | 2009-10-01 17:11:10 +0200 | [diff] [blame] | 383 | depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX) |
Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 384 | |
H. Peter Anvin | de32e04 | 2007-07-11 12:18:30 -0700 | [diff] [blame] | 385 | config X86_MINIMUM_CPU_FAMILY |
Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 386 | int |
Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 387 | default "64" if X86_64 |
H. Peter Anvin | 7343b3b | 2008-02-14 14:52:05 -0800 | [diff] [blame] | 388 | default "6" if X86_32 && X86_P6_NOP |
Linus Torvalds | 982d007 | 2009-09-30 17:57:27 -0700 | [diff] [blame] | 389 | default "5" if X86_32 && X86_CMPXCHG64 |
H. Peter Anvin | eb068e7 | 2012-11-28 11:50:23 -0800 | [diff] [blame] | 390 | default "4" |
Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 391 | |
Roland McGrath | 0a049bb | 2008-01-30 13:30:54 +0100 | [diff] [blame] | 392 | config X86_DEBUGCTLMSR |
Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 393 | def_bool y |
H. Peter Anvin | eb068e7 | 2012-11-28 11:50:23 -0800 | [diff] [blame] | 394 | depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486) && !UML |
Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 395 | |
| 396 | menuconfig PROCESSOR_SELECT |
David Rientjes | 6a108a1 | 2011-01-20 14:44:16 -0800 | [diff] [blame] | 397 | bool "Supported processor vendors" if EXPERT |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 398 | ---help--- |
Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 399 | This lets you choose what x86 vendor support code your kernel |
| 400 | will include. |
| 401 | |
Yinghai Lu | 879d792 | 2008-09-09 16:40:37 -0700 | [diff] [blame] | 402 | config CPU_SUP_INTEL |
Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 403 | default y |
| 404 | bool "Support Intel processors" if PROCESSOR_SELECT |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 405 | ---help--- |
Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 406 | This enables detection, tunings and quirks for Intel processors |
| 407 | |
| 408 | You need this enabled if you want your kernel to run on an |
| 409 | Intel CPU. Disabling this option on other types of CPUs |
| 410 | makes the kernel a tiny bit smaller. Disabling it on an Intel |
| 411 | CPU might render the kernel unbootable. |
| 412 | |
| 413 | If unsure, say N. |
Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 414 | |
| 415 | config CPU_SUP_CYRIX_32 |
| 416 | default y |
| 417 | bool "Support Cyrix processors" if PROCESSOR_SELECT |
H. Peter Anvin | eb068e7 | 2012-11-28 11:50:23 -0800 | [diff] [blame] | 418 | depends on M486 || M586 || M586TSC || M586MMX || (EXPERT && !64BIT) |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 419 | ---help--- |
Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 420 | This enables detection, tunings and quirks for Cyrix processors |
| 421 | |
| 422 | You need this enabled if you want your kernel to run on a |
| 423 | Cyrix CPU. Disabling this option on other types of CPUs |
| 424 | makes the kernel a tiny bit smaller. Disabling it on a Cyrix |
| 425 | CPU might render the kernel unbootable. |
| 426 | |
| 427 | If unsure, say N. |
Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 428 | |
Yinghai Lu | ff73152 | 2008-09-07 17:58:56 -0700 | [diff] [blame] | 429 | config CPU_SUP_AMD |
Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 430 | default y |
| 431 | bool "Support AMD processors" if PROCESSOR_SELECT |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 432 | ---help--- |
Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 433 | This enables detection, tunings and quirks for AMD processors |
| 434 | |
| 435 | You need this enabled if you want your kernel to run on an |
| 436 | AMD CPU. Disabling this option on other types of CPUs |
| 437 | makes the kernel a tiny bit smaller. Disabling it on an AMD |
| 438 | CPU might render the kernel unbootable. |
| 439 | |
| 440 | If unsure, say N. |
Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 441 | |
Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 442 | config CPU_SUP_CENTAUR |
Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 443 | default y |
| 444 | bool "Support Centaur processors" if PROCESSOR_SELECT |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 445 | ---help--- |
Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 446 | This enables detection, tunings and quirks for Centaur processors |
| 447 | |
| 448 | You need this enabled if you want your kernel to run on a |
| 449 | Centaur CPU. Disabling this option on other types of CPUs |
| 450 | makes the kernel a tiny bit smaller. Disabling it on a Centaur |
| 451 | CPU might render the kernel unbootable. |
| 452 | |
| 453 | If unsure, say N. |
Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 454 | |
| 455 | config CPU_SUP_TRANSMETA_32 |
| 456 | default y |
| 457 | bool "Support Transmeta processors" if PROCESSOR_SELECT |
| 458 | depends on !64BIT |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 459 | ---help--- |
Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 460 | This enables detection, tunings and quirks for Transmeta processors |
| 461 | |
| 462 | You need this enabled if you want your kernel to run on a |
| 463 | Transmeta CPU. Disabling this option on other types of CPUs |
| 464 | makes the kernel a tiny bit smaller. Disabling it on a Transmeta |
| 465 | CPU might render the kernel unbootable. |
| 466 | |
| 467 | If unsure, say N. |
Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 468 | |
| 469 | config CPU_SUP_UMC_32 |
| 470 | default y |
| 471 | bool "Support UMC processors" if PROCESSOR_SELECT |
H. Peter Anvin | eb068e7 | 2012-11-28 11:50:23 -0800 | [diff] [blame] | 472 | depends on M486 || (EXPERT && !64BIT) |
Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 473 | ---help--- |
Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 474 | This enables detection, tunings and quirks for UMC processors |
| 475 | |
| 476 | You need this enabled if you want your kernel to run on a |
| 477 | UMC CPU. Disabling this option on other types of CPUs |
| 478 | makes the kernel a tiny bit smaller. Disabling it on a UMC |
| 479 | CPU might render the kernel unbootable. |
| 480 | |
| 481 | If unsure, say N. |