Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 1 | /* |
Robert Richter | 6852fd9 | 2008-07-22 21:09:08 +0200 | [diff] [blame] | 2 | * @file op_model_amd.c |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 3 | * athlon / K7 / K8 / Family 10h model-specific MSR operations |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 5 | * @remark Copyright 2002-2009 OProfile authors |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * @remark Read the file COPYING |
| 7 | * |
| 8 | * @author John Levon |
| 9 | * @author Philippe Elie |
| 10 | * @author Graydon Hoare |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 11 | * @author Robert Richter <robert.richter@amd.com> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 12 | * @author Barry Kasindorf |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 13 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | |
| 15 | #include <linux/oprofile.h> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 16 | #include <linux/device.h> |
| 17 | #include <linux/pci.h> |
| 18 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <asm/ptrace.h> |
| 20 | #include <asm/msr.h> |
Don Zickus | 3e4ff11 | 2006-06-26 13:57:01 +0200 | [diff] [blame] | 21 | #include <asm/nmi.h> |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 22 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include "op_x86_model.h" |
| 24 | #include "op_counter.h" |
| 25 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 26 | #define NUM_COUNTERS 4 |
| 27 | #define NUM_CONTROLS 4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 29 | #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0) |
| 30 | #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0) |
| 31 | #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | #define CTR_OVERFLOWED(n) (!((n) & (1U<<31))) |
| 33 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 34 | #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0) |
| 35 | #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0) |
| 36 | #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | #define CTRL_SET_ACTIVE(n) (n |= (1<<22)) |
| 38 | #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22)) |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 39 | #define CTRL_CLEAR_LO(x) (x &= (1<<21)) |
| 40 | #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | #define CTRL_SET_ENABLE(val) (val |= 1<<20) |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 42 | #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16)) |
| 43 | #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | #define CTRL_SET_UM(val, m) (val |= (m << 8)) |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 45 | #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff)) |
| 46 | #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf)) |
| 47 | #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9)) |
| 48 | #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 50 | static unsigned long reset_value[NUM_COUNTERS]; |
| 51 | |
| 52 | #ifdef CONFIG_OPROFILE_IBS |
| 53 | |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 54 | /* IbsFetchCtl bits/masks */ |
| 55 | #define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */ |
| 56 | #define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */ |
| 57 | #define IBS_FETCH_LOW_MAX_CNT_MASK 0x0000FFFFUL /* MaxCnt mask */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 58 | |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 59 | /*IbsOpCtl bits */ |
| 60 | #define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */ |
| 61 | #define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 62 | |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 63 | #define IBS_FETCH_SIZE 6 |
| 64 | #define IBS_OP_SIZE 12 |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 65 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 66 | static int has_ibs; /* AMD Family10h and later */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 67 | |
| 68 | struct op_ibs_config { |
| 69 | unsigned long op_enabled; |
| 70 | unsigned long fetch_enabled; |
| 71 | unsigned long max_cnt_fetch; |
| 72 | unsigned long max_cnt_op; |
| 73 | unsigned long rand_en; |
| 74 | unsigned long dispatched_ops; |
| 75 | }; |
| 76 | |
| 77 | static struct op_ibs_config ibs_config; |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 78 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 79 | #endif |
| 80 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 81 | /* functions for op_amd_spec */ |
Robert Richter | dfa1542 | 2008-07-22 21:08:49 +0200 | [diff] [blame] | 82 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 83 | static void op_amd_fill_in_addresses(struct op_msrs * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | { |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 85 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 87 | for (i = 0; i < NUM_COUNTERS; i++) { |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 88 | if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) |
| 89 | msrs->counters[i].addr = MSR_K7_PERFCTR0 + i; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 90 | else |
| 91 | msrs->counters[i].addr = 0; |
| 92 | } |
| 93 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 94 | for (i = 0; i < NUM_CONTROLS; i++) { |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 95 | if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) |
| 96 | msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 97 | else |
| 98 | msrs->controls[i].addr = 0; |
| 99 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | } |
| 101 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 102 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 103 | static void op_amd_setup_ctrs(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | { |
| 105 | unsigned int low, high; |
| 106 | int i; |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 107 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | /* clear all counters */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 109 | for (i = 0 ; i < NUM_CONTROLS; ++i) { |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 110 | if (unlikely(!CTRL_IS_RESERVED(msrs, i))) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 111 | continue; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | CTRL_READ(low, high, msrs, i); |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 113 | CTRL_CLEAR_LO(low); |
| 114 | CTRL_CLEAR_HI(high); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | CTRL_WRITE(low, high, msrs, i); |
| 116 | } |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 117 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | /* avoid a false detection of ctr overflows in NMI handler */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 119 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 120 | if (unlikely(!CTR_IS_RESERVED(msrs, i))) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 121 | continue; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 122 | CTR_WRITE(1, msrs, i); |
| 123 | } |
| 124 | |
| 125 | /* enable active counters */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 126 | for (i = 0; i < NUM_COUNTERS; ++i) { |
| 127 | if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) { |
| 128 | reset_value[i] = counter_config[i].count; |
| 129 | |
| 130 | CTR_WRITE(counter_config[i].count, msrs, i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | |
| 132 | CTRL_READ(low, high, msrs, i); |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 133 | CTRL_CLEAR_LO(low); |
| 134 | CTRL_CLEAR_HI(high); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | CTRL_SET_ENABLE(low); |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 136 | CTRL_SET_USR(low, counter_config[i].user); |
| 137 | CTRL_SET_KERN(low, counter_config[i].kernel); |
| 138 | CTRL_SET_UM(low, counter_config[i].unit_mask); |
| 139 | CTRL_SET_EVENT_LOW(low, counter_config[i].event); |
| 140 | CTRL_SET_EVENT_HIGH(high, counter_config[i].event); |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 141 | CTRL_SET_HOST_ONLY(high, 0); |
| 142 | CTRL_SET_GUEST_ONLY(high, 0); |
| 143 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | CTRL_WRITE(low, high, msrs, i); |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 145 | } else { |
| 146 | reset_value[i] = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | } |
| 148 | } |
| 149 | } |
| 150 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 151 | #ifdef CONFIG_OPROFILE_IBS |
| 152 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 153 | static inline int |
| 154 | op_amd_handle_ibs(struct pt_regs * const regs, |
| 155 | struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | { |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 157 | u32 low, high; |
| 158 | u64 msr; |
| 159 | struct op_entry entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 161 | if (!has_ibs) |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 162 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 164 | if (ibs_config.fetch_enabled) { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 165 | rdmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 166 | if (high & IBS_FETCH_HIGH_VALID_BIT) { |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 167 | rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 168 | oprofile_write_reserve(&entry, regs, msr, |
| 169 | IBS_FETCH_CODE, IBS_FETCH_SIZE); |
| 170 | oprofile_add_data(&entry, (u32)msr); |
| 171 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
| 172 | oprofile_add_data(&entry, low); |
| 173 | oprofile_add_data(&entry, high); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 174 | rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 175 | oprofile_add_data(&entry, (u32)msr); |
| 176 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
| 177 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 178 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 179 | /* reenable the IRQ */ |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 180 | high &= ~IBS_FETCH_HIGH_VALID_BIT; |
| 181 | high |= IBS_FETCH_HIGH_ENABLE; |
| 182 | low &= IBS_FETCH_LOW_MAX_CNT_MASK; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 183 | wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
| 184 | } |
| 185 | } |
| 186 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 187 | if (ibs_config.op_enabled) { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 188 | rdmsr(MSR_AMD64_IBSOPCTL, low, high); |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 189 | if (low & IBS_OP_LOW_VALID_BIT) { |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 190 | rdmsrl(MSR_AMD64_IBSOPRIP, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 191 | oprofile_write_reserve(&entry, regs, msr, |
| 192 | IBS_OP_CODE, IBS_OP_SIZE); |
| 193 | oprofile_add_data(&entry, (u32)msr); |
| 194 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 195 | rdmsrl(MSR_AMD64_IBSOPDATA, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 196 | oprofile_add_data(&entry, (u32)msr); |
| 197 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 198 | rdmsrl(MSR_AMD64_IBSOPDATA2, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 199 | oprofile_add_data(&entry, (u32)msr); |
| 200 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 201 | rdmsrl(MSR_AMD64_IBSOPDATA3, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 202 | oprofile_add_data(&entry, (u32)msr); |
| 203 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 204 | rdmsrl(MSR_AMD64_IBSDCLINAD, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 205 | oprofile_add_data(&entry, (u32)msr); |
| 206 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 207 | rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 208 | oprofile_add_data(&entry, (u32)msr); |
| 209 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
| 210 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 211 | |
| 212 | /* reenable the IRQ */ |
Robert Richter | 543a157 | 2008-07-22 21:09:04 +0200 | [diff] [blame] | 213 | high = 0; |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 214 | low &= ~IBS_OP_LOW_VALID_BIT; |
| 215 | low |= IBS_OP_LOW_ENABLE; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 216 | wrmsr(MSR_AMD64_IBSOPCTL, low, high); |
| 217 | } |
| 218 | } |
| 219 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | return 1; |
| 221 | } |
| 222 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 223 | #endif |
| 224 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 225 | static int op_amd_check_ctrs(struct pt_regs * const regs, |
| 226 | struct op_msrs const * const msrs) |
| 227 | { |
| 228 | unsigned int low, high; |
| 229 | int i; |
| 230 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 231 | for (i = 0 ; i < NUM_COUNTERS; ++i) { |
| 232 | if (!reset_value[i]) |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 233 | continue; |
| 234 | CTR_READ(low, high, msrs, i); |
| 235 | if (CTR_OVERFLOWED(low)) { |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 236 | oprofile_add_sample(regs, i); |
| 237 | CTR_WRITE(reset_value[i], msrs, i); |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 238 | } |
| 239 | } |
| 240 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 241 | #ifdef CONFIG_OPROFILE_IBS |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 242 | op_amd_handle_ibs(regs, msrs); |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 243 | #endif |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 244 | |
| 245 | /* See op_model_ppro.c */ |
| 246 | return 1; |
| 247 | } |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 248 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 249 | static void op_amd_start(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | { |
| 251 | unsigned int low, high; |
| 252 | int i; |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 253 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
| 254 | if (reset_value[i]) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 255 | CTRL_READ(low, high, msrs, i); |
| 256 | CTRL_SET_ACTIVE(low); |
| 257 | CTRL_WRITE(low, high, msrs, i); |
| 258 | } |
| 259 | } |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 260 | |
| 261 | #ifdef CONFIG_OPROFILE_IBS |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 262 | if (has_ibs && ibs_config.fetch_enabled) { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 263 | low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF; |
Suravee Suthikulpanit | 5f87dfb | 2008-10-15 08:15:51 -0500 | [diff] [blame] | 264 | high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */ |
| 265 | + IBS_FETCH_HIGH_ENABLE; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 266 | wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
| 267 | } |
| 268 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 269 | if (has_ibs && ibs_config.op_enabled) { |
Suravee Suthikulpanit | 5f87dfb | 2008-10-15 08:15:51 -0500 | [diff] [blame] | 270 | low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF) |
| 271 | + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */ |
| 272 | + IBS_OP_LOW_ENABLE; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 273 | high = 0; |
| 274 | wrmsr(MSR_AMD64_IBSOPCTL, low, high); |
| 275 | } |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 276 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 280 | static void op_amd_stop(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | { |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 282 | unsigned int low, high; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | int i; |
| 284 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 285 | /* |
| 286 | * Subtle: stop on all counters to avoid race with setting our |
| 287 | * pm callback |
| 288 | */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 289 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
| 290 | if (!reset_value[i]) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 291 | continue; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | CTRL_READ(low, high, msrs, i); |
| 293 | CTRL_SET_INACTIVE(low); |
| 294 | CTRL_WRITE(low, high, msrs, i); |
| 295 | } |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 296 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 297 | #ifdef CONFIG_OPROFILE_IBS |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 298 | if (has_ibs && ibs_config.fetch_enabled) { |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 299 | /* clear max count and enable */ |
| 300 | low = 0; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 301 | high = 0; |
| 302 | wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
| 303 | } |
| 304 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 305 | if (has_ibs && ibs_config.op_enabled) { |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 306 | /* clear max count and enable */ |
| 307 | low = 0; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 308 | high = 0; |
| 309 | wrmsr(MSR_AMD64_IBSOPCTL, low, high); |
| 310 | } |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 311 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | } |
| 313 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 314 | static void op_amd_shutdown(struct op_msrs const * const msrs) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 315 | { |
| 316 | int i; |
| 317 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 318 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 319 | if (CTR_IS_RESERVED(msrs, i)) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 320 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); |
| 321 | } |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 322 | for (i = 0 ; i < NUM_CONTROLS ; ++i) { |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 323 | if (CTRL_IS_RESERVED(msrs, i)) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 324 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); |
| 325 | } |
| 326 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 327 | |
Robert Richter | 9fa6812 | 2008-11-24 14:21:03 +0100 | [diff] [blame] | 328 | #ifdef CONFIG_OPROFILE_IBS |
Robert Richter | a4c408a | 2008-07-22 21:09:02 +0200 | [diff] [blame] | 329 | |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 330 | static u8 ibs_eilvt_off; |
| 331 | |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 332 | static inline void apic_init_ibs_nmi_per_cpu(void *arg) |
| 333 | { |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 334 | ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | static inline void apic_clear_ibs_nmi_per_cpu(void *arg) |
| 338 | { |
| 339 | setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1); |
| 340 | } |
| 341 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 342 | static int init_ibs_nmi(void) |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 343 | { |
| 344 | #define IBSCTL_LVTOFFSETVAL (1 << 8) |
| 345 | #define IBSCTL 0x1cc |
| 346 | struct pci_dev *cpu_cfg; |
| 347 | int nodes; |
| 348 | u32 value = 0; |
| 349 | |
| 350 | /* per CPU setup */ |
Robert Richter | ebb535d | 2008-07-22 21:08:59 +0200 | [diff] [blame] | 351 | on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 352 | |
| 353 | nodes = 0; |
| 354 | cpu_cfg = NULL; |
| 355 | do { |
| 356 | cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD, |
| 357 | PCI_DEVICE_ID_AMD_10H_NB_MISC, |
| 358 | cpu_cfg); |
| 359 | if (!cpu_cfg) |
| 360 | break; |
| 361 | ++nodes; |
| 362 | pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off |
| 363 | | IBSCTL_LVTOFFSETVAL); |
| 364 | pci_read_config_dword(cpu_cfg, IBSCTL, &value); |
| 365 | if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) { |
Robert Richter | 83bd924 | 2008-12-15 15:09:50 +0100 | [diff] [blame] | 366 | pci_dev_put(cpu_cfg); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 367 | printk(KERN_DEBUG "Failed to setup IBS LVT offset, " |
| 368 | "IBSCTL = 0x%08x", value); |
| 369 | return 1; |
| 370 | } |
| 371 | } while (1); |
| 372 | |
| 373 | if (!nodes) { |
| 374 | printk(KERN_DEBUG "No CPU node configured for IBS"); |
| 375 | return 1; |
| 376 | } |
| 377 | |
| 378 | #ifdef CONFIG_NUMA |
| 379 | /* Sanity check */ |
| 380 | /* Works only for 64bit with proper numa implementation. */ |
| 381 | if (nodes != num_possible_nodes()) { |
| 382 | printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, " |
| 383 | "found: %d, expected %d", |
| 384 | nodes, num_possible_nodes()); |
| 385 | return 1; |
| 386 | } |
| 387 | #endif |
| 388 | return 0; |
| 389 | } |
| 390 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 391 | /* uninitialize the APIC for the IBS interrupts if needed */ |
| 392 | static void clear_ibs_nmi(void) |
| 393 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 394 | if (has_ibs) |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 395 | on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1); |
| 396 | } |
| 397 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 398 | /* initialize the APIC for the IBS interrupts if available */ |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 399 | static void ibs_init(void) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 400 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 401 | has_ibs = boot_cpu_has(X86_FEATURE_IBS); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 402 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 403 | if (!has_ibs) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 404 | return; |
| 405 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 406 | if (init_ibs_nmi()) { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 407 | has_ibs = 0; |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 408 | return; |
| 409 | } |
| 410 | |
| 411 | printk(KERN_INFO "oprofile: AMD IBS detected\n"); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 412 | } |
| 413 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 414 | static void ibs_exit(void) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 415 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 416 | if (!has_ibs) |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 417 | return; |
| 418 | |
| 419 | clear_ibs_nmi(); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 420 | } |
| 421 | |
Robert Richter | 25ad2913 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 422 | static int (*create_arch_files)(struct super_block *sb, struct dentry *root); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 423 | |
Robert Richter | 25ad2913 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 424 | static int setup_ibs_files(struct super_block *sb, struct dentry *root) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 425 | { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 426 | struct dentry *dir; |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 427 | int ret = 0; |
| 428 | |
| 429 | /* architecture specific files */ |
| 430 | if (create_arch_files) |
| 431 | ret = create_arch_files(sb, root); |
| 432 | |
| 433 | if (ret) |
| 434 | return ret; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 435 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 436 | if (!has_ibs) |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 437 | return ret; |
| 438 | |
| 439 | /* model specific files */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 440 | |
| 441 | /* setup some reasonable defaults */ |
| 442 | ibs_config.max_cnt_fetch = 250000; |
| 443 | ibs_config.fetch_enabled = 0; |
| 444 | ibs_config.max_cnt_op = 250000; |
| 445 | ibs_config.op_enabled = 0; |
| 446 | ibs_config.dispatched_ops = 1; |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 447 | |
| 448 | dir = oprofilefs_mkdir(sb, root, "ibs_fetch"); |
| 449 | oprofilefs_create_ulong(sb, dir, "enable", |
| 450 | &ibs_config.fetch_enabled); |
| 451 | oprofilefs_create_ulong(sb, dir, "max_count", |
| 452 | &ibs_config.max_cnt_fetch); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 453 | oprofilefs_create_ulong(sb, dir, "rand_enable", |
| 454 | &ibs_config.rand_en); |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 455 | |
Robert Richter | ccd755c | 2008-07-29 16:57:10 +0200 | [diff] [blame] | 456 | dir = oprofilefs_mkdir(sb, root, "ibs_op"); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 457 | oprofilefs_create_ulong(sb, dir, "enable", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 458 | &ibs_config.op_enabled); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 459 | oprofilefs_create_ulong(sb, dir, "max_count", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 460 | &ibs_config.max_cnt_op); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 461 | oprofilefs_create_ulong(sb, dir, "dispatched_ops", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 462 | &ibs_config.dispatched_ops); |
Robert Richter | fc2bd73 | 2008-07-22 21:09:00 +0200 | [diff] [blame] | 463 | |
| 464 | return 0; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 465 | } |
| 466 | |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 467 | static int op_amd_init(struct oprofile_operations *ops) |
| 468 | { |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 469 | ibs_init(); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 470 | create_arch_files = ops->create_files; |
| 471 | ops->create_files = setup_ibs_files; |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 472 | return 0; |
| 473 | } |
| 474 | |
| 475 | static void op_amd_exit(void) |
| 476 | { |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 477 | ibs_exit(); |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 478 | } |
| 479 | |
Robert Richter | 9fa6812 | 2008-11-24 14:21:03 +0100 | [diff] [blame] | 480 | #else |
| 481 | |
| 482 | /* no IBS support */ |
| 483 | |
| 484 | static int op_amd_init(struct oprofile_operations *ops) |
| 485 | { |
| 486 | return 0; |
| 487 | } |
| 488 | |
| 489 | static void op_amd_exit(void) {} |
| 490 | |
| 491 | #endif /* CONFIG_OPROFILE_IBS */ |
Robert Richter | a4c408a | 2008-07-22 21:09:02 +0200 | [diff] [blame] | 492 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 493 | struct op_x86_model_spec const op_amd_spec = { |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 494 | .init = op_amd_init, |
| 495 | .exit = op_amd_exit, |
| 496 | .num_counters = NUM_COUNTERS, |
| 497 | .num_controls = NUM_CONTROLS, |
| 498 | .fill_in_addresses = &op_amd_fill_in_addresses, |
| 499 | .setup_ctrs = &op_amd_setup_ctrs, |
| 500 | .check_ctrs = &op_amd_check_ctrs, |
| 501 | .start = &op_amd_start, |
| 502 | .stop = &op_amd_stop, |
| 503 | .shutdown = &op_amd_shutdown |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 504 | }; |