Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Local APIC handling, local APIC timers |
| 3 | * |
Ingo Molnar | 8f47e16 | 2009-01-31 02:03:42 +0100 | [diff] [blame] | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * Fixes |
| 7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
| 8 | * thanks to Eric Gilmore |
| 9 | * and Rolf G. Tews |
| 10 | * for testing these extensively. |
| 11 | * Maciej W. Rozycki : Various updates and fixes. |
| 12 | * Mikael Pettersson : Power Management for UP-APIC. |
| 13 | * Pavel Machek and |
| 14 | * Mikael Pettersson : PM converted to driver model. |
| 15 | */ |
| 16 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 17 | #include <linux/perf_event.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/kernel_stat.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 19 | #include <linux/mc146818rtc.h> |
Thomas Gleixner | 70a2002 | 2008-01-30 13:30:18 +0100 | [diff] [blame] | 20 | #include <linux/acpi_pmtmr.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 21 | #include <linux/clockchips.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/bootmem.h> |
Frederic Weisbecker | bcbc4f2 | 2008-12-09 23:54:20 +0100 | [diff] [blame] | 24 | #include <linux/ftrace.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 25 | #include <linux/ioport.h> |
| 26 | #include <linux/module.h> |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 27 | #include <linux/syscore_ops.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 28 | #include <linux/delay.h> |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 29 | #include <linux/timex.h> |
Ralf Baechle | 334955e | 2011-06-01 19:04:57 +0100 | [diff] [blame] | 30 | #include <linux/i8253.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 31 | #include <linux/dmar.h> |
| 32 | #include <linux/init.h> |
| 33 | #include <linux/cpu.h> |
| 34 | #include <linux/dmi.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 35 | #include <linux/smp.h> |
| 36 | #include <linux/mm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
Suresh Siddha | 8a8f422 | 2012-03-30 11:47:08 -0700 | [diff] [blame] | 38 | #include <asm/irq_remapping.h> |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 39 | #include <asm/perf_event.h> |
Thomas Gleixner | 736deca | 2009-08-19 12:35:53 +0200 | [diff] [blame] | 40 | #include <asm/x86_init.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | #include <asm/pgalloc.h> |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 42 | #include <linux/atomic.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 43 | #include <asm/mpspec.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 44 | #include <asm/i8259.h> |
Andi Kleen | 73dea47 | 2006-02-03 21:50:50 +0100 | [diff] [blame] | 45 | #include <asm/proto.h> |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 46 | #include <asm/apic.h> |
Henrik Kretzschmar | 7167d08 | 2011-02-22 15:38:05 +0100 | [diff] [blame] | 47 | #include <asm/io_apic.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 48 | #include <asm/desc.h> |
| 49 | #include <asm/hpet.h> |
| 50 | #include <asm/idle.h> |
| 51 | #include <asm/mtrr.h> |
Ralf Baechle | 16f871b | 2011-06-01 19:05:06 +0100 | [diff] [blame] | 52 | #include <asm/time.h> |
Jaswinder Singh Rajput | 2bc1379 | 2009-01-11 20:34:47 +0530 | [diff] [blame] | 53 | #include <asm/smp.h> |
Andi Kleen | be71b85 | 2009-02-12 13:49:38 +0100 | [diff] [blame] | 54 | #include <asm/mce.h> |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 55 | #include <asm/tsc.h> |
Sheng Yang | 2904ed8 | 2010-12-21 14:18:48 +0800 | [diff] [blame] | 56 | #include <asm/hypervisor.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 58 | unsigned int num_processors; |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 59 | |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 60 | unsigned disabled_cpus __cpuinitdata; |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 61 | |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 62 | /* Processor that is doing the boot up */ |
| 63 | unsigned int boot_cpu_physical_apicid = -1U; |
Glauber Costa | 5af5573 | 2008-03-25 13:28:56 -0300 | [diff] [blame] | 64 | |
Cyrill Gorcunov | 80e5609 | 2008-08-24 02:01:42 -0700 | [diff] [blame] | 65 | /* |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 66 | * The highest APIC ID seen during enumeration. |
Cyrill Gorcunov | 80e5609 | 2008-08-24 02:01:42 -0700 | [diff] [blame] | 67 | */ |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 68 | unsigned int max_physical_apicid; |
| 69 | |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 70 | /* |
| 71 | * Bitmask of physically existing CPUs: |
| 72 | */ |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 73 | physid_mask_t phys_cpu_present_map; |
| 74 | |
| 75 | /* |
| 76 | * Map cpu index to physical APIC ID |
| 77 | */ |
Vlad Zolotarov | 0816b0f | 2012-06-11 12:56:52 +0300 | [diff] [blame] | 78 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); |
| 79 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 80 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
| 81 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); |
Cyrill Gorcunov | 80e5609 | 2008-08-24 02:01:42 -0700 | [diff] [blame] | 82 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 83 | #ifdef CONFIG_X86_32 |
Tejun Heo | 4c321ff | 2011-01-23 14:37:30 +0100 | [diff] [blame] | 84 | |
Tejun Heo | 4c321ff | 2011-01-23 14:37:30 +0100 | [diff] [blame] | 85 | /* |
| 86 | * On x86_32, the mapping between cpu and logical apicid may vary |
| 87 | * depending on apic in use. The following early percpu variable is |
| 88 | * used for the mapping. This is where the behaviors of x86_64 and 32 |
| 89 | * actually diverge. Let's keep it ugly for now. |
| 90 | */ |
Vlad Zolotarov | 0816b0f | 2012-06-11 12:56:52 +0300 | [diff] [blame] | 91 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); |
Tejun Heo | 4c321ff | 2011-01-23 14:37:30 +0100 | [diff] [blame] | 92 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 93 | /* |
| 94 | * Knob to control our willingness to enable the local APIC. |
| 95 | * |
| 96 | * +1=force-enable |
| 97 | */ |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 98 | static int force_enable_local_apic __initdata; |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 99 | /* |
| 100 | * APIC command line parameters |
| 101 | */ |
| 102 | static int __init parse_lapic(char *arg) |
| 103 | { |
| 104 | force_enable_local_apic = 1; |
| 105 | return 0; |
| 106 | } |
| 107 | early_param("lapic", parse_lapic); |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 108 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
| 109 | static int enabled_via_apicbase; |
| 110 | |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 111 | /* |
| 112 | * Handle interrupt mode configuration register (IMCR). |
| 113 | * This register controls whether the interrupt signals |
| 114 | * that reach the BSP come from the master PIC or from the |
| 115 | * local APIC. Before entering Symmetric I/O Mode, either |
| 116 | * the BIOS or the operating system must switch out of |
| 117 | * PIC Mode by changing the IMCR. |
| 118 | */ |
Alexander van Heukelum | 5cda395 | 2009-04-13 17:39:24 +0200 | [diff] [blame] | 119 | static inline void imcr_pic_to_apic(void) |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 120 | { |
| 121 | /* select IMCR register */ |
| 122 | outb(0x70, 0x22); |
| 123 | /* NMI and 8259 INTR go through APIC */ |
| 124 | outb(0x01, 0x23); |
| 125 | } |
| 126 | |
Alexander van Heukelum | 5cda395 | 2009-04-13 17:39:24 +0200 | [diff] [blame] | 127 | static inline void imcr_apic_to_pic(void) |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 128 | { |
| 129 | /* select IMCR register */ |
| 130 | outb(0x70, 0x22); |
| 131 | /* NMI and 8259 INTR go directly to BSP */ |
| 132 | outb(0x00, 0x23); |
| 133 | } |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 134 | #endif |
| 135 | |
| 136 | #ifdef CONFIG_X86_64 |
Chris Wright | bc1d99c | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 137 | static int apic_calibrate_pmtmr __initdata; |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 138 | static __init int setup_apicpmtimer(char *s) |
| 139 | { |
| 140 | apic_calibrate_pmtmr = 1; |
| 141 | notsc_setup(NULL); |
| 142 | return 0; |
| 143 | } |
| 144 | __setup("apicpmtimer", setup_apicpmtimer); |
| 145 | #endif |
| 146 | |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 147 | int x2apic_mode; |
Yinghai Lu | 06cd9a7 | 2009-02-16 17:29:58 -0800 | [diff] [blame] | 148 | #ifdef CONFIG_X86_X2APIC |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 149 | /* x2apic enabled before OS handover */ |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 150 | int x2apic_preenabled; |
| 151 | static int x2apic_disabled; |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 152 | static int nox2apic; |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 153 | static __init int setup_nox2apic(char *str) |
| 154 | { |
Suresh Siddha | 39d83a5 | 2009-04-20 13:02:29 -0700 | [diff] [blame] | 155 | if (x2apic_enabled()) { |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 156 | int apicid = native_apic_msr_read(APIC_ID); |
Suresh Siddha | 39d83a5 | 2009-04-20 13:02:29 -0700 | [diff] [blame] | 157 | |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 158 | if (apicid >= 255) { |
| 159 | pr_warning("Apicid: %08x, cannot enforce nox2apic\n", |
| 160 | apicid); |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | pr_warning("x2apic already enabled. will disable it\n"); |
| 165 | } else |
| 166 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); |
| 167 | |
| 168 | nox2apic = 1; |
| 169 | |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 170 | return 0; |
| 171 | } |
| 172 | early_param("nox2apic", setup_nox2apic); |
| 173 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 175 | unsigned long mp_lapic_addr; |
| 176 | int disable_apic; |
| 177 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 178 | static int disable_apic_timer __initdata; |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 179 | /* Local APIC timer works in C2 */ |
Linus Torvalds | 2e7c283 | 2007-03-23 11:32:31 -0700 | [diff] [blame] | 180 | int local_apic_timer_c2_ok; |
| 181 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); |
| 182 | |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 183 | int first_system_vector = 0xfe; |
| 184 | |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 185 | /* |
| 186 | * Debug level, exported for io_apic.c |
| 187 | */ |
Maciej W. Rozycki | baa1318 | 2008-07-14 18:44:51 +0100 | [diff] [blame] | 188 | unsigned int apic_verbosity; |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 189 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 190 | int pic_mode; |
| 191 | |
Alexey Starikovskiy | bab4b27 | 2008-05-19 19:47:03 +0400 | [diff] [blame] | 192 | /* Have we found an MP table */ |
| 193 | int smp_found_config; |
| 194 | |
Aaron Durbin | 3992872 | 2006-12-07 02:14:01 +0100 | [diff] [blame] | 195 | static struct resource lapic_resource = { |
| 196 | .name = "Local APIC", |
| 197 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, |
| 198 | }; |
| 199 | |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 200 | unsigned int lapic_timer_frequency = 0; |
Thomas Gleixner | d03030e | 2007-10-12 23:04:06 +0200 | [diff] [blame] | 201 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 202 | static void apic_pm_activate(void); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 203 | |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 204 | static unsigned long apic_phys; |
| 205 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 206 | /* |
| 207 | * Get the LAPIC version |
| 208 | */ |
| 209 | static inline int lapic_get_version(void) |
| 210 | { |
| 211 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 212 | } |
| 213 | |
| 214 | /* |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 215 | * Check, if the APIC is integrated or a separate chip |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 216 | */ |
| 217 | static inline int lapic_is_integrated(void) |
| 218 | { |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 219 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 220 | return 1; |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 221 | #else |
| 222 | return APIC_INTEGRATED(lapic_get_version()); |
| 223 | #endif |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | /* |
| 227 | * Check, whether this is a modern or a first generation APIC |
| 228 | */ |
| 229 | static int modern_apic(void) |
| 230 | { |
| 231 | /* AMD systems use old APIC versions, so check the CPU */ |
| 232 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
| 233 | boot_cpu_data.x86 >= 0xf) |
| 234 | return 1; |
| 235 | return lapic_get_version() >= 0x14; |
| 236 | } |
| 237 | |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 238 | /* |
Cyrill Gorcunov | a933c61 | 2009-10-14 00:07:04 +0400 | [diff] [blame] | 239 | * right after this call apic become NOOP driven |
| 240 | * so apic->write/read doesn't do anything |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 241 | */ |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 242 | static void __init apic_disable(void) |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 243 | { |
Cyrill Gorcunov | f88f2b4 | 2009-10-15 19:04:16 +0400 | [diff] [blame] | 244 | pr_info("APIC: switched to apic NOOP\n"); |
Cyrill Gorcunov | a933c61 | 2009-10-14 00:07:04 +0400 | [diff] [blame] | 245 | apic = &apic_noop; |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 246 | } |
| 247 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 248 | void native_apic_wait_icr_idle(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 249 | { |
| 250 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) |
| 251 | cpu_relax(); |
| 252 | } |
| 253 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 254 | u32 native_safe_apic_wait_icr_idle(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 255 | { |
| 256 | u32 send_status; |
| 257 | int timeout; |
| 258 | |
| 259 | timeout = 0; |
| 260 | do { |
| 261 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; |
| 262 | if (!send_status) |
| 263 | break; |
Fernando Luis Vazquez Cao | b49d7d8 | 2011-12-15 11:32:24 +0900 | [diff] [blame] | 264 | inc_irq_stat(icr_read_retry_count); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 265 | udelay(100); |
| 266 | } while (timeout++ < 1000); |
| 267 | |
| 268 | return send_status; |
| 269 | } |
| 270 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 271 | void native_apic_icr_write(u32 low, u32 id) |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 272 | { |
Cyrill Gorcunov | ed4e5ec | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 273 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 274 | apic_write(APIC_ICR, low); |
| 275 | } |
| 276 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 277 | u64 native_apic_icr_read(void) |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 278 | { |
| 279 | u32 icr1, icr2; |
| 280 | |
| 281 | icr2 = apic_read(APIC_ICR2); |
| 282 | icr1 = apic_read(APIC_ICR); |
| 283 | |
Cyrill Gorcunov | cf9768d7 | 2008-08-16 23:21:55 +0400 | [diff] [blame] | 284 | return icr1 | ((u64)icr2 << 32); |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 285 | } |
| 286 | |
Cyrill Gorcunov | 7c37e48 | 2008-08-24 02:01:40 -0700 | [diff] [blame] | 287 | #ifdef CONFIG_X86_32 |
| 288 | /** |
| 289 | * get_physical_broadcast - Get number of physical broadcast IDs |
| 290 | */ |
| 291 | int get_physical_broadcast(void) |
| 292 | { |
| 293 | return modern_apic() ? 0xff : 0xf; |
| 294 | } |
| 295 | #endif |
| 296 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 297 | /** |
| 298 | * lapic_get_maxlvt - get the maximum number of local vector table entries |
| 299 | */ |
| 300 | int lapic_get_maxlvt(void) |
| 301 | { |
Cyrill Gorcunov | 36a028d | 2008-07-24 13:52:28 +0200 | [diff] [blame] | 302 | unsigned int v; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 303 | |
| 304 | v = apic_read(APIC_LVR); |
Cyrill Gorcunov | 36a028d | 2008-07-24 13:52:28 +0200 | [diff] [blame] | 305 | /* |
| 306 | * - we always have APIC integrated on 64bit mode |
| 307 | * - 82489DXs do not report # of LVT entries |
| 308 | */ |
| 309 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | /* |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 313 | * Local APIC timer |
| 314 | */ |
| 315 | |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 316 | /* Clock divisor */ |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 317 | #define APIC_DIVISOR 16 |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 318 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 319 | /* |
| 320 | * This function sets up the local APIC timer, with a timeout of |
| 321 | * 'clocks' APIC bus clock. During calibration we actually call |
| 322 | * this function twice on the boot CPU, once with a bogus timeout |
| 323 | * value, second time for real. The other (noncalibrating) CPUs |
| 324 | * call this function only once, with the real, calibrated value. |
| 325 | * |
| 326 | * We do reads before writes even if unnecessary, to get around the |
| 327 | * P5 APIC double write bug. |
| 328 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 329 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
| 330 | { |
| 331 | unsigned int lvtt_value, tmp_value; |
| 332 | |
| 333 | lvtt_value = LOCAL_TIMER_VECTOR; |
| 334 | if (!oneshot) |
| 335 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 336 | if (!lapic_is_integrated()) |
| 337 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); |
| 338 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 339 | if (!irqen) |
| 340 | lvtt_value |= APIC_LVT_MASKED; |
| 341 | |
| 342 | apic_write(APIC_LVTT, lvtt_value); |
| 343 | |
| 344 | /* |
| 345 | * Divide PICLK by 16 |
| 346 | */ |
| 347 | tmp_value = apic_read(APIC_TDCR); |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 348 | apic_write(APIC_TDCR, |
| 349 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
| 350 | APIC_TDR_DIV_16); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 351 | |
| 352 | if (!oneshot) |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 353 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 354 | } |
| 355 | |
| 356 | /* |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 357 | * Setup extended LVT, AMD specific |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 358 | * |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 359 | * Software should use the LVT offsets the BIOS provides. The offsets |
| 360 | * are determined by the subsystems using it like those for MCE |
| 361 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts |
| 362 | * are supported. Beginning with family 10h at least 4 offsets are |
| 363 | * available. |
Robert Richter | 286f571 | 2008-07-22 21:08:46 +0200 | [diff] [blame] | 364 | * |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 365 | * Since the offsets must be consistent for all cores, we keep track |
| 366 | * of the LVT offsets in software and reserve the offset for the same |
| 367 | * vector also to be used on other cores. An offset is freed by |
| 368 | * setting the entry to APIC_EILVT_MASKED. |
| 369 | * |
| 370 | * If the BIOS is right, there should be no conflicts. Otherwise a |
| 371 | * "[Firmware Bug]: ..." error message is generated. However, if |
| 372 | * software does not properly determines the offsets, it is not |
| 373 | * necessarily a BIOS bug. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 374 | */ |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 375 | |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 376 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 377 | |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 378 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) |
| 379 | { |
| 380 | return (old & APIC_EILVT_MASKED) |
| 381 | || (new == APIC_EILVT_MASKED) |
| 382 | || ((new & ~APIC_EILVT_MASKED) == old); |
| 383 | } |
| 384 | |
| 385 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) |
| 386 | { |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 387 | unsigned int rsvd, vector; |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 388 | |
| 389 | if (offset >= APIC_EILVT_NR_MAX) |
| 390 | return ~0; |
| 391 | |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 392 | rsvd = atomic_read(&eilvt_offsets[offset]); |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 393 | do { |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 394 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
| 395 | if (vector && !eilvt_entry_is_changeable(vector, new)) |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 396 | /* may not change if vectors are different */ |
| 397 | return rsvd; |
| 398 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); |
| 399 | } while (rsvd != new); |
| 400 | |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 401 | rsvd &= ~APIC_EILVT_MASKED; |
| 402 | if (rsvd && rsvd != vector) |
| 403 | pr_info("LVT offset %d assigned for vector 0x%02x\n", |
| 404 | offset, rsvd); |
| 405 | |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 406 | return new; |
| 407 | } |
| 408 | |
| 409 | /* |
| 410 | * If mask=1, the LVT entry does not generate interrupts while mask=0 |
Robert Richter | cbf74ce | 2011-05-30 16:31:11 +0200 | [diff] [blame] | 411 | * enables the vector. See also the BKDGs. Must be called with |
| 412 | * preemption disabled. |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 413 | */ |
| 414 | |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 415 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 416 | { |
| 417 | unsigned long reg = APIC_EILVTn(offset); |
| 418 | unsigned int new, old, reserved; |
| 419 | |
| 420 | new = (mask << 16) | (msg_type << 8) | vector; |
| 421 | old = apic_read(reg); |
| 422 | reserved = reserve_eilvt_offset(offset, new); |
| 423 | |
| 424 | if (reserved != new) { |
Robert Richter | eb48c9c | 2010-10-25 16:03:39 +0200 | [diff] [blame] | 425 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
| 426 | "vector 0x%x, but the register is already in use for " |
| 427 | "vector 0x%x on another cpu\n", |
| 428 | smp_processor_id(), reg, offset, new, reserved); |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 429 | return -EINVAL; |
| 430 | } |
| 431 | |
| 432 | if (!eilvt_entry_is_changeable(old, new)) { |
Robert Richter | eb48c9c | 2010-10-25 16:03:39 +0200 | [diff] [blame] | 433 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
| 434 | "vector 0x%x, but the register is already in use for " |
| 435 | "vector 0x%x on this cpu\n", |
| 436 | smp_processor_id(), reg, offset, new, old); |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 437 | return -EBUSY; |
| 438 | } |
| 439 | |
| 440 | apic_write(reg, new); |
| 441 | |
| 442 | return 0; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 443 | } |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 444 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 445 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 446 | /* |
| 447 | * Program the next event, relative to now |
| 448 | */ |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 449 | static int lapic_next_event(unsigned long delta, |
| 450 | struct clock_event_device *evt) |
| 451 | { |
| 452 | apic_write(APIC_TMICT, delta); |
| 453 | return 0; |
| 454 | } |
| 455 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 456 | /* |
| 457 | * Setup the lapic timer in periodic or oneshot mode |
| 458 | */ |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 459 | static void lapic_timer_setup(enum clock_event_mode mode, |
| 460 | struct clock_event_device *evt) |
| 461 | { |
| 462 | unsigned long flags; |
| 463 | unsigned int v; |
| 464 | |
| 465 | /* Lapic used as dummy for broadcast ? */ |
| 466 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) |
| 467 | return; |
| 468 | |
| 469 | local_irq_save(flags); |
| 470 | |
| 471 | switch (mode) { |
| 472 | case CLOCK_EVT_MODE_PERIODIC: |
| 473 | case CLOCK_EVT_MODE_ONESHOT: |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 474 | __setup_APIC_LVTT(lapic_timer_frequency, |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 475 | mode != CLOCK_EVT_MODE_PERIODIC, 1); |
| 476 | break; |
| 477 | case CLOCK_EVT_MODE_UNUSED: |
| 478 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 479 | v = apic_read(APIC_LVTT); |
| 480 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
| 481 | apic_write(APIC_LVTT, v); |
Andreas Herrmann | 6f9b410 | 2009-10-27 11:01:38 +0100 | [diff] [blame] | 482 | apic_write(APIC_TMICT, 0); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 483 | break; |
| 484 | case CLOCK_EVT_MODE_RESUME: |
| 485 | /* Nothing to do here */ |
| 486 | break; |
| 487 | } |
| 488 | |
| 489 | local_irq_restore(flags); |
| 490 | } |
| 491 | |
| 492 | /* |
| 493 | * Local APIC timer broadcast function |
| 494 | */ |
Mike Travis | 9628937 | 2008-12-31 18:08:46 -0800 | [diff] [blame] | 495 | static void lapic_timer_broadcast(const struct cpumask *mask) |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 496 | { |
| 497 | #ifdef CONFIG_SMP |
Ingo Molnar | dac5f41 | 2009-01-28 15:42:24 +0100 | [diff] [blame] | 498 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 499 | #endif |
| 500 | } |
| 501 | |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 502 | |
| 503 | /* |
| 504 | * The local apic timer can be used for any function which is CPU local. |
| 505 | */ |
| 506 | static struct clock_event_device lapic_clockevent = { |
| 507 | .name = "lapic", |
| 508 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
| 509 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
| 510 | .shift = 32, |
| 511 | .set_mode = lapic_timer_setup, |
| 512 | .set_next_event = lapic_next_event, |
| 513 | .broadcast = lapic_timer_broadcast, |
| 514 | .rating = 100, |
| 515 | .irq = -1, |
| 516 | }; |
| 517 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); |
| 518 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 519 | /* |
Uwe Kleine-König | 421f91d | 2010-06-11 12:17:00 +0200 | [diff] [blame] | 520 | * Setup the local APIC timer for this CPU. Copy the initialized values |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 521 | * of the boot CPU and register the clock event in the framework. |
| 522 | */ |
Cyrill Gorcunov | db4b552 | 2008-08-24 02:01:39 -0700 | [diff] [blame] | 523 | static void __cpuinit setup_APIC_timer(void) |
Fernando Luis VazquezCao | 8339e9f | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 524 | { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 525 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); |
| 526 | |
Christoph Lameter | 349c004 | 2011-03-12 12:50:10 +0100 | [diff] [blame] | 527 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
Venkatesh Pallipadi | db954b5 | 2009-04-06 18:51:29 -0700 | [diff] [blame] | 528 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
| 529 | /* Make LAPIC timer preferrable over percpu HPET */ |
| 530 | lapic_clockevent.rating = 150; |
| 531 | } |
| 532 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 533 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
Rusty Russell | 320ab2b | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 534 | levt->cpumask = cpumask_of(smp_processor_id()); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 535 | |
| 536 | clockevents_register_device(levt); |
Fernando Luis VazquezCao | 8339e9f | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 537 | } |
| 538 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 539 | /* |
| 540 | * In this functions we calibrate APIC bus clocks to the external timer. |
| 541 | * |
| 542 | * We want to do the calibration only once since we want to have local timer |
| 543 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus |
| 544 | * frequency. |
| 545 | * |
| 546 | * This was previously done by reading the PIT/HPET and waiting for a wrap |
| 547 | * around to find out, that a tick has elapsed. I have a box, where the PIT |
| 548 | * readout is broken, so it never gets out of the wait loop again. This was |
| 549 | * also reported by others. |
| 550 | * |
| 551 | * Monitoring the jiffies value is inaccurate and the clockevents |
| 552 | * infrastructure allows us to do a simple substitution of the interrupt |
| 553 | * handler. |
| 554 | * |
| 555 | * The calibration routine also uses the pm_timer when possible, as the PIT |
| 556 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes |
| 557 | * back to normal later in the boot process). |
| 558 | */ |
| 559 | |
| 560 | #define LAPIC_CAL_LOOPS (HZ/10) |
| 561 | |
| 562 | static __initdata int lapic_cal_loops = -1; |
| 563 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
| 564 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; |
| 565 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; |
| 566 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; |
| 567 | |
| 568 | /* |
| 569 | * Temporary interrupt handler. |
| 570 | */ |
| 571 | static void __init lapic_cal_handler(struct clock_event_device *dev) |
| 572 | { |
| 573 | unsigned long long tsc = 0; |
| 574 | long tapic = apic_read(APIC_TMCCT); |
| 575 | unsigned long pm = acpi_pm_read_early(); |
| 576 | |
| 577 | if (cpu_has_tsc) |
| 578 | rdtscll(tsc); |
| 579 | |
| 580 | switch (lapic_cal_loops++) { |
| 581 | case 0: |
| 582 | lapic_cal_t1 = tapic; |
| 583 | lapic_cal_tsc1 = tsc; |
| 584 | lapic_cal_pm1 = pm; |
| 585 | lapic_cal_j1 = jiffies; |
| 586 | break; |
| 587 | |
| 588 | case LAPIC_CAL_LOOPS: |
| 589 | lapic_cal_t2 = tapic; |
| 590 | lapic_cal_tsc2 = tsc; |
| 591 | if (pm < lapic_cal_pm1) |
| 592 | pm += ACPI_PM_OVRRUN; |
| 593 | lapic_cal_pm2 = pm; |
| 594 | lapic_cal_j2 = jiffies; |
| 595 | break; |
| 596 | } |
| 597 | } |
| 598 | |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 599 | static int __init |
| 600 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 601 | { |
| 602 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; |
| 603 | const long pm_thresh = pm_100ms / 100; |
| 604 | unsigned long mult; |
| 605 | u64 res; |
| 606 | |
| 607 | #ifndef CONFIG_X86_PM_TIMER |
| 608 | return -1; |
| 609 | #endif |
| 610 | |
Yasuaki Ishimatsu | 39ba5d4 | 2009-01-28 12:52:24 +0900 | [diff] [blame] | 611 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 612 | |
| 613 | /* Check, if the PM timer is available */ |
| 614 | if (!deltapm) |
| 615 | return -1; |
| 616 | |
| 617 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); |
| 618 | |
| 619 | if (deltapm > (pm_100ms - pm_thresh) && |
| 620 | deltapm < (pm_100ms + pm_thresh)) { |
Yasuaki Ishimatsu | 39ba5d4 | 2009-01-28 12:52:24 +0900 | [diff] [blame] | 621 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 622 | return 0; |
| 623 | } |
| 624 | |
| 625 | res = (((u64)deltapm) * mult) >> 22; |
| 626 | do_div(res, 1000000); |
| 627 | pr_warning("APIC calibration not consistent " |
Yasuaki Ishimatsu | 39ba5d4 | 2009-01-28 12:52:24 +0900 | [diff] [blame] | 628 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 629 | |
| 630 | /* Correct the lapic counter value */ |
| 631 | res = (((u64)(*delta)) * pm_100ms); |
| 632 | do_div(res, deltapm); |
| 633 | pr_info("APIC delta adjusted to PM-Timer: " |
| 634 | "%lu (%ld)\n", (unsigned long)res, *delta); |
| 635 | *delta = (long)res; |
| 636 | |
| 637 | /* Correct the tsc counter value */ |
| 638 | if (cpu_has_tsc) { |
| 639 | res = (((u64)(*deltatsc)) * pm_100ms); |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 640 | do_div(res, deltapm); |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 641 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
Frans Pop | 3235dc3 | 2010-02-06 18:47:17 +0100 | [diff] [blame] | 642 | "PM-Timer: %lu (%ld)\n", |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 643 | (unsigned long)res, *deltatsc); |
| 644 | *deltatsc = (long)res; |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 645 | } |
| 646 | |
| 647 | return 0; |
| 648 | } |
| 649 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 650 | static int __init calibrate_APIC_clock(void) |
| 651 | { |
| 652 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 653 | void (*real_handler)(struct clock_event_device *dev); |
| 654 | unsigned long deltaj; |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 655 | long delta, deltatsc; |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 656 | int pm_referenced = 0; |
| 657 | |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 658 | /** |
| 659 | * check if lapic timer has already been calibrated by platform |
| 660 | * specific routine, such as tsc calibration code. if so, we just fill |
| 661 | * in the clockevent structure and return. |
| 662 | */ |
| 663 | |
| 664 | if (lapic_timer_frequency) { |
| 665 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
| 666 | lapic_timer_frequency); |
| 667 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, |
| 668 | TICK_NSEC, lapic_clockevent.shift); |
| 669 | lapic_clockevent.max_delta_ns = |
| 670 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); |
| 671 | lapic_clockevent.min_delta_ns = |
| 672 | clockevent_delta2ns(0xF, &lapic_clockevent); |
| 673 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
| 674 | return 0; |
| 675 | } |
| 676 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 677 | local_irq_disable(); |
| 678 | |
| 679 | /* Replace the global interrupt handler */ |
| 680 | real_handler = global_clock_event->event_handler; |
| 681 | global_clock_event->event_handler = lapic_cal_handler; |
| 682 | |
| 683 | /* |
Cyrill Gorcunov | 81608f3 | 2008-10-10 19:00:17 +0400 | [diff] [blame] | 684 | * Setup the APIC counter to maximum. There is no way the lapic |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 685 | * can underflow in the 100ms detection time frame |
| 686 | */ |
Cyrill Gorcunov | 81608f3 | 2008-10-10 19:00:17 +0400 | [diff] [blame] | 687 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 688 | |
| 689 | /* Let the interrupts run */ |
| 690 | local_irq_enable(); |
| 691 | |
| 692 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
| 693 | cpu_relax(); |
| 694 | |
| 695 | local_irq_disable(); |
| 696 | |
| 697 | /* Restore the real event handler */ |
| 698 | global_clock_event->event_handler = real_handler; |
| 699 | |
| 700 | /* Build delta t1-t2 as apic timer counts down */ |
| 701 | delta = lapic_cal_t1 - lapic_cal_t2; |
| 702 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); |
| 703 | |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 704 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
| 705 | |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 706 | /* we trust the PM based calibration if possible */ |
| 707 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 708 | &delta, &deltatsc); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 709 | |
| 710 | /* Calculate the scaled math multiplication factor */ |
| 711 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
| 712 | lapic_clockevent.shift); |
| 713 | lapic_clockevent.max_delta_ns = |
Pierre Tardy | 4aed89d | 2011-01-06 16:23:29 +0100 | [diff] [blame] | 714 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 715 | lapic_clockevent.min_delta_ns = |
| 716 | clockevent_delta2ns(0xF, &lapic_clockevent); |
| 717 | |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 718 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 719 | |
| 720 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); |
Thomas Gleixner | 411462f | 2009-11-16 11:52:39 +0100 | [diff] [blame] | 721 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 722 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 723 | lapic_timer_frequency); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 724 | |
| 725 | if (cpu_has_tsc) { |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 726 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
| 727 | "%ld.%04ld MHz.\n", |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 728 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
| 729 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 730 | } |
| 731 | |
| 732 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " |
| 733 | "%u.%04u MHz.\n", |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 734 | lapic_timer_frequency / (1000000 / HZ), |
| 735 | lapic_timer_frequency % (1000000 / HZ)); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 736 | |
| 737 | /* |
| 738 | * Do a sanity check on the APIC calibration result |
| 739 | */ |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 740 | if (lapic_timer_frequency < (1000000 / HZ)) { |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 741 | local_irq_enable(); |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 742 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 743 | return -1; |
| 744 | } |
| 745 | |
| 746 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; |
| 747 | |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 748 | /* |
| 749 | * PM timer calibration failed or not turned on |
| 750 | * so lets try APIC timer based calibration |
| 751 | */ |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 752 | if (!pm_referenced) { |
| 753 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); |
| 754 | |
| 755 | /* |
| 756 | * Setup the apic timer manually |
| 757 | */ |
| 758 | levt->event_handler = lapic_cal_handler; |
| 759 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); |
| 760 | lapic_cal_loops = -1; |
| 761 | |
| 762 | /* Let the interrupts run */ |
| 763 | local_irq_enable(); |
| 764 | |
| 765 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
| 766 | cpu_relax(); |
| 767 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 768 | /* Stop the lapic timer */ |
| 769 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); |
| 770 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 771 | /* Jiffies delta */ |
| 772 | deltaj = lapic_cal_j2 - lapic_cal_j1; |
| 773 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); |
| 774 | |
| 775 | /* Check, if the jiffies result is consistent */ |
| 776 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
| 777 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
| 778 | else |
| 779 | levt->features |= CLOCK_EVT_FEAT_DUMMY; |
| 780 | } else |
| 781 | local_irq_enable(); |
| 782 | |
| 783 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 784 | pr_warning("APIC timer disabled due to verification failure\n"); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 785 | return -1; |
| 786 | } |
| 787 | |
| 788 | return 0; |
| 789 | } |
| 790 | |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 791 | /* |
| 792 | * Setup the boot APIC |
| 793 | * |
| 794 | * Calibrate and verify the result. |
| 795 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 796 | void __init setup_boot_APIC_clock(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 797 | { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 798 | /* |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 799 | * The local apic timer can be disabled via the kernel |
| 800 | * commandline or from the CPU detection code. Register the lapic |
| 801 | * timer as a dummy clock event source on SMP systems, so the |
| 802 | * broadcast mechanism is used. On UP systems simply ignore it. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 803 | */ |
| 804 | if (disable_apic_timer) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 805 | pr_info("Disabling APIC timer\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 806 | /* No broadcast on UP ! */ |
Thomas Gleixner | 9d09951 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 807 | if (num_possible_cpus() > 1) { |
| 808 | lapic_clockevent.mult = 1; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 809 | setup_APIC_timer(); |
Thomas Gleixner | 9d09951 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 810 | } |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 811 | return; |
| 812 | } |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 813 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 814 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
| 815 | "calibrating APIC timer ...\n"); |
| 816 | |
Cyrill Gorcunov | 89b3b1f4 | 2008-07-15 21:02:54 +0400 | [diff] [blame] | 817 | if (calibrate_APIC_clock()) { |
Thomas Gleixner | c2b84b3 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 818 | /* No broadcast on UP ! */ |
| 819 | if (num_possible_cpus() > 1) |
| 820 | setup_APIC_timer(); |
| 821 | return; |
| 822 | } |
| 823 | |
| 824 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 825 | * If nmi_watchdog is set to IO_APIC, we need the |
| 826 | * PIT/HPET going. Otherwise register lapic as a dummy |
| 827 | * device. |
| 828 | */ |
Don Zickus | 072b198 | 2010-11-12 11:22:24 -0500 | [diff] [blame] | 829 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 830 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 831 | /* Setup the lapic or request the broadcast */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 832 | setup_APIC_timer(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 833 | } |
| 834 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 835 | void __cpuinit setup_secondary_APIC_clock(void) |
| 836 | { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 837 | setup_APIC_timer(); |
| 838 | } |
| 839 | |
| 840 | /* |
| 841 | * The guts of the apic timer interrupt |
| 842 | */ |
| 843 | static void local_apic_timer_interrupt(void) |
| 844 | { |
| 845 | int cpu = smp_processor_id(); |
| 846 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); |
| 847 | |
| 848 | /* |
| 849 | * Normally we should not be here till LAPIC has been initialized but |
| 850 | * in some cases like kdump, its possible that there is a pending LAPIC |
| 851 | * timer interrupt from previous kernel's context and is delivered in |
| 852 | * new kernel the moment interrupts are enabled. |
| 853 | * |
| 854 | * Interrupts are enabled early and LAPIC is setup much later, hence |
| 855 | * its possible that when we get here evt->event_handler is NULL. |
| 856 | * Check for event_handler being NULL and discard the interrupt as |
| 857 | * spurious. |
| 858 | */ |
| 859 | if (!evt->event_handler) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 860 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 861 | /* Switch it off */ |
| 862 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); |
| 863 | return; |
| 864 | } |
| 865 | |
| 866 | /* |
| 867 | * the NMI deadlock-detector uses this. |
| 868 | */ |
Hiroshi Shimamoto | 915b0d0 | 2008-12-08 19:19:26 -0800 | [diff] [blame] | 869 | inc_irq_stat(apic_timer_irqs); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 870 | |
| 871 | evt->event_handler(evt); |
| 872 | } |
| 873 | |
| 874 | /* |
| 875 | * Local APIC timer interrupt. This is the most natural way for doing |
| 876 | * local interrupts, but local timer interrupts can be emulated by |
| 877 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] |
| 878 | * |
| 879 | * [ if a single-CPU system runs an SMP kernel then we call the local |
| 880 | * interrupt as well. Thus we cannot inline the local irq ... ] |
| 881 | */ |
Frederic Weisbecker | bcbc4f2 | 2008-12-09 23:54:20 +0100 | [diff] [blame] | 882 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 883 | { |
| 884 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 885 | |
| 886 | /* |
| 887 | * NOTE! We'd better ACK the irq immediately, |
| 888 | * because timer handling can be slow. |
| 889 | */ |
| 890 | ack_APIC_irq(); |
| 891 | /* |
| 892 | * update_process_times() expects us to have done irq_enter(). |
| 893 | * Besides, if we don't timer interrupts ignore the global |
| 894 | * interrupt lock, which is the WrongThing (tm) to do. |
| 895 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 896 | irq_enter(); |
Frederic Weisbecker | 98ad1cc | 2011-10-07 18:22:09 +0200 | [diff] [blame] | 897 | exit_idle(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 898 | local_apic_timer_interrupt(); |
| 899 | irq_exit(); |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 900 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 901 | set_irq_regs(old_regs); |
| 902 | } |
| 903 | |
| 904 | int setup_profiling_timer(unsigned int multiplier) |
| 905 | { |
| 906 | return -EINVAL; |
| 907 | } |
| 908 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 909 | /* |
| 910 | * Local APIC start and shutdown |
| 911 | */ |
| 912 | |
| 913 | /** |
| 914 | * clear_local_APIC - shutdown the local APIC |
| 915 | * |
| 916 | * This is called, when a CPU is disabled and before rebooting, so the state of |
| 917 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS |
| 918 | * leftovers during boot. |
| 919 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 920 | void clear_local_APIC(void) |
| 921 | { |
Chuck Ebbert | 2584a82 | 2008-05-20 18:18:12 -0400 | [diff] [blame] | 922 | int maxlvt; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 923 | u32 v; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 925 | /* APIC hasn't been mapped yet */ |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 926 | if (!x2apic_mode && !apic_phys) |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 927 | return; |
| 928 | |
| 929 | maxlvt = lapic_get_maxlvt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 930 | /* |
Siddha, Suresh B | 704fc59 | 2006-06-26 13:59:53 +0200 | [diff] [blame] | 931 | * Masking an LVT entry can trigger a local APIC error |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 932 | * if the vector is zero. Mask LVTERR first to prevent this. |
| 933 | */ |
| 934 | if (maxlvt >= 3) { |
| 935 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 936 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 937 | } |
| 938 | /* |
| 939 | * Careful: we have to set masks only first to deassert |
| 940 | * any level-triggered sources. |
| 941 | */ |
| 942 | v = apic_read(APIC_LVTT); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 943 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 944 | v = apic_read(APIC_LVT0); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 945 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 946 | v = apic_read(APIC_LVT1); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 947 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 948 | if (maxlvt >= 4) { |
| 949 | v = apic_read(APIC_LVTPC); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 950 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 951 | } |
| 952 | |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 953 | /* lets not touch this if we didn't frob it */ |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 954 | #ifdef CONFIG_X86_THERMAL_VECTOR |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 955 | if (maxlvt >= 5) { |
| 956 | v = apic_read(APIC_LVTTHMR); |
| 957 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
| 958 | } |
| 959 | #endif |
Andi Kleen | 5ca8681 | 2009-02-12 13:49:37 +0100 | [diff] [blame] | 960 | #ifdef CONFIG_X86_MCE_INTEL |
| 961 | if (maxlvt >= 6) { |
| 962 | v = apic_read(APIC_LVTCMCI); |
| 963 | if (!(v & APIC_LVT_MASKED)) |
| 964 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); |
| 965 | } |
| 966 | #endif |
| 967 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 968 | /* |
| 969 | * Clean APIC state for other OSs: |
| 970 | */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 971 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
| 972 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
| 973 | apic_write(APIC_LVT1, APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 974 | if (maxlvt >= 3) |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 975 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 976 | if (maxlvt >= 4) |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 977 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 978 | |
| 979 | /* Integrated APIC (!82489DX) ? */ |
| 980 | if (lapic_is_integrated()) { |
| 981 | if (maxlvt > 3) |
| 982 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
| 983 | apic_write(APIC_ESR, 0); |
| 984 | apic_read(APIC_ESR); |
| 985 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | } |
| 987 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 988 | /** |
| 989 | * disable_local_APIC - clear and disable the local APIC |
| 990 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 991 | void disable_local_APIC(void) |
| 992 | { |
| 993 | unsigned int value; |
| 994 | |
Jan Beulich | 4a13ad0 | 2009-01-14 12:28:51 +0000 | [diff] [blame] | 995 | /* APIC hasn't been mapped yet */ |
Yinghai Lu | fd19dce | 2010-07-15 00:00:59 -0700 | [diff] [blame] | 996 | if (!x2apic_mode && !apic_phys) |
Jan Beulich | 4a13ad0 | 2009-01-14 12:28:51 +0000 | [diff] [blame] | 997 | return; |
| 998 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 999 | clear_local_APIC(); |
| 1000 | |
| 1001 | /* |
| 1002 | * Disable APIC (implies clearing of registers |
| 1003 | * for 82489DX!). |
| 1004 | */ |
| 1005 | value = apic_read(APIC_SPIV); |
| 1006 | value &= ~APIC_SPIV_APIC_ENABLED; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1007 | apic_write(APIC_SPIV, value); |
Cyrill Gorcunov | 990b183 | 2008-08-18 20:45:51 +0400 | [diff] [blame] | 1008 | |
| 1009 | #ifdef CONFIG_X86_32 |
| 1010 | /* |
| 1011 | * When LAPIC was disabled by the BIOS and enabled by the kernel, |
| 1012 | * restore the disabled state. |
| 1013 | */ |
| 1014 | if (enabled_via_apicbase) { |
| 1015 | unsigned int l, h; |
| 1016 | |
| 1017 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1018 | l &= ~MSR_IA32_APICBASE_ENABLE; |
| 1019 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 1020 | } |
| 1021 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1022 | } |
| 1023 | |
Cyrill Gorcunov | fe4024d | 2008-08-18 20:45:52 +0400 | [diff] [blame] | 1024 | /* |
| 1025 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
| 1026 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and |
| 1027 | * not power-off. Additionally clear all LVT entries before disable_local_APIC |
| 1028 | * for the case where Linux didn't enable the LAPIC. |
| 1029 | */ |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 1030 | void lapic_shutdown(void) |
| 1031 | { |
| 1032 | unsigned long flags; |
| 1033 | |
Cyrill Gorcunov | 8312136 | 2009-09-15 11:12:30 +0400 | [diff] [blame] | 1034 | if (!cpu_has_apic && !apic_from_smp_config()) |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 1035 | return; |
| 1036 | |
| 1037 | local_irq_save(flags); |
| 1038 | |
Cyrill Gorcunov | fe4024d | 2008-08-18 20:45:52 +0400 | [diff] [blame] | 1039 | #ifdef CONFIG_X86_32 |
| 1040 | if (!enabled_via_apicbase) |
| 1041 | clear_local_APIC(); |
| 1042 | else |
| 1043 | #endif |
| 1044 | disable_local_APIC(); |
| 1045 | |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 1046 | |
| 1047 | local_irq_restore(flags); |
| 1048 | } |
| 1049 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1050 | /* |
| 1051 | * This is to verify that we're looking at a real local APIC. |
| 1052 | * Check these against your board if the CPUs aren't getting |
| 1053 | * started for no apparent reason. |
| 1054 | */ |
| 1055 | int __init verify_local_APIC(void) |
| 1056 | { |
| 1057 | unsigned int reg0, reg1; |
| 1058 | |
| 1059 | /* |
| 1060 | * The version register is read-only in a real APIC. |
| 1061 | */ |
| 1062 | reg0 = apic_read(APIC_LVR); |
| 1063 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); |
| 1064 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); |
| 1065 | reg1 = apic_read(APIC_LVR); |
| 1066 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); |
| 1067 | |
| 1068 | /* |
| 1069 | * The two version reads above should print the same |
| 1070 | * numbers. If the second one is different, then we |
| 1071 | * poke at a non-APIC. |
| 1072 | */ |
| 1073 | if (reg1 != reg0) |
| 1074 | return 0; |
| 1075 | |
| 1076 | /* |
| 1077 | * Check if the version looks reasonably. |
| 1078 | */ |
| 1079 | reg1 = GET_APIC_VERSION(reg0); |
| 1080 | if (reg1 == 0x00 || reg1 == 0xff) |
| 1081 | return 0; |
Thomas Gleixner | 37e650c | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 1082 | reg1 = lapic_get_maxlvt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1083 | if (reg1 < 0x02 || reg1 == 0xff) |
| 1084 | return 0; |
| 1085 | |
| 1086 | /* |
| 1087 | * The ID register is read/write in a real APIC. |
| 1088 | */ |
Suresh Siddha | 2d7a66d | 2008-07-11 14:24:19 -0700 | [diff] [blame] | 1089 | reg0 = apic_read(APIC_ID); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1090 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
Ingo Molnar | 5b81272 | 2009-01-28 14:59:17 +0100 | [diff] [blame] | 1091 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
Suresh Siddha | 2d7a66d | 2008-07-11 14:24:19 -0700 | [diff] [blame] | 1092 | reg1 = apic_read(APIC_ID); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1093 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
| 1094 | apic_write(APIC_ID, reg0); |
Ingo Molnar | 5b81272 | 2009-01-28 14:59:17 +0100 | [diff] [blame] | 1095 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1096 | return 0; |
| 1097 | |
| 1098 | /* |
| 1099 | * The next two are just to see if we have sane values. |
| 1100 | * They're only really relevant if we're in Virtual Wire |
| 1101 | * compatibility mode, but most boxes are anymore. |
| 1102 | */ |
| 1103 | reg0 = apic_read(APIC_LVT0); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1104 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1105 | reg1 = apic_read(APIC_LVT1); |
| 1106 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); |
| 1107 | |
| 1108 | return 1; |
| 1109 | } |
| 1110 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1111 | /** |
| 1112 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs |
| 1113 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1114 | void __init sync_Arb_IDs(void) |
| 1115 | { |
Cyrill Gorcunov | 296cb95 | 2008-08-15 13:51:23 +0200 | [diff] [blame] | 1116 | /* |
| 1117 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not |
| 1118 | * needed on AMD. |
| 1119 | */ |
| 1120 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1121 | return; |
| 1122 | |
| 1123 | /* |
| 1124 | * Wait for idle. |
| 1125 | */ |
| 1126 | apic_wait_icr_idle(); |
| 1127 | |
| 1128 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
Cyrill Gorcunov | 6f6da97 | 2008-08-15 23:05:19 +0400 | [diff] [blame] | 1129 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
| 1130 | APIC_INT_LEVELTRIG | APIC_DM_INIT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1131 | } |
| 1132 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1133 | /* |
| 1134 | * An initial setup of the virtual wire mode. |
| 1135 | */ |
| 1136 | void __init init_bsp_APIC(void) |
| 1137 | { |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1138 | unsigned int value; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1139 | |
| 1140 | /* |
| 1141 | * Don't do the setup now if we have a SMP BIOS as the |
| 1142 | * through-I/O-APIC virtual wire mode might be active. |
| 1143 | */ |
| 1144 | if (smp_found_config || !cpu_has_apic) |
| 1145 | return; |
| 1146 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1147 | /* |
| 1148 | * Do not trust the local APIC being empty at bootup. |
| 1149 | */ |
| 1150 | clear_local_APIC(); |
| 1151 | |
| 1152 | /* |
| 1153 | * Enable APIC. |
| 1154 | */ |
| 1155 | value = apic_read(APIC_SPIV); |
| 1156 | value &= ~APIC_VECTOR_MASK; |
| 1157 | value |= APIC_SPIV_APIC_ENABLED; |
Cyrill Gorcunov | 638c041 | 2008-08-15 23:05:18 +0400 | [diff] [blame] | 1158 | |
| 1159 | #ifdef CONFIG_X86_32 |
| 1160 | /* This bit is reserved on P4/Xeon and should be cleared */ |
| 1161 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && |
| 1162 | (boot_cpu_data.x86 == 15)) |
| 1163 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 1164 | else |
| 1165 | #endif |
| 1166 | value |= APIC_SPIV_FOCUS_DISABLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1167 | value |= SPURIOUS_APIC_VECTOR; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1168 | apic_write(APIC_SPIV, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1169 | |
| 1170 | /* |
| 1171 | * Set up the virtual wire mode. |
| 1172 | */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1173 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1174 | value = APIC_DM_NMI; |
Cyrill Gorcunov | 638c041 | 2008-08-15 23:05:18 +0400 | [diff] [blame] | 1175 | if (!lapic_is_integrated()) /* 82489DX */ |
| 1176 | value |= APIC_LVT_LEVEL_TRIGGER; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1177 | apic_write(APIC_LVT1, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1178 | } |
| 1179 | |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1180 | static void __cpuinit lapic_setup_esr(void) |
| 1181 | { |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1182 | unsigned int oldvalue, value, maxlvt; |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1183 | |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1184 | if (!lapic_is_integrated()) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1185 | pr_info("No ESR for 82489DX.\n"); |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1186 | return; |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1187 | } |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1188 | |
Ingo Molnar | 08125d3 | 2009-01-28 05:08:44 +0100 | [diff] [blame] | 1189 | if (apic->disable_esr) { |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1190 | /* |
| 1191 | * Something untraceable is creating bad interrupts on |
| 1192 | * secondary quads ... for the moment, just leave the |
| 1193 | * ESR disabled - we can't do anything useful with the |
| 1194 | * errors anyway - mbligh |
| 1195 | */ |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1196 | pr_info("Leaving ESR disabled.\n"); |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1197 | return; |
| 1198 | } |
| 1199 | |
| 1200 | maxlvt = lapic_get_maxlvt(); |
| 1201 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 1202 | apic_write(APIC_ESR, 0); |
| 1203 | oldvalue = apic_read(APIC_ESR); |
| 1204 | |
| 1205 | /* enables sending errors */ |
| 1206 | value = ERROR_APIC_VECTOR; |
| 1207 | apic_write(APIC_LVTERR, value); |
| 1208 | |
| 1209 | /* |
| 1210 | * spec says clear errors after enabling vector. |
| 1211 | */ |
| 1212 | if (maxlvt > 3) |
| 1213 | apic_write(APIC_ESR, 0); |
| 1214 | value = apic_read(APIC_ESR); |
| 1215 | if (value != oldvalue) |
| 1216 | apic_printk(APIC_VERBOSE, "ESR value before enabling " |
| 1217 | "vector: 0x%08x after: 0x%08x\n", |
| 1218 | oldvalue, value); |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1219 | } |
| 1220 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1221 | /** |
| 1222 | * setup_local_APIC - setup the local APIC |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1223 | * |
| 1224 | * Used to setup local APIC while initializing BSP or bringin up APs. |
| 1225 | * Always called with preemption disabled. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1226 | */ |
| 1227 | void __cpuinit setup_local_APIC(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1228 | { |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1229 | int cpu = smp_processor_id(); |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1230 | unsigned int value, queued; |
| 1231 | int i, j, acked = 0; |
| 1232 | unsigned long long tsc = 0, ntsc; |
| 1233 | long long max_loops = cpu_khz; |
| 1234 | |
| 1235 | if (cpu_has_tsc) |
| 1236 | rdtscll(tsc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1237 | |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1238 | if (disable_apic) { |
Henrik Kretzschmar | 7167d08 | 2011-02-22 15:38:05 +0100 | [diff] [blame] | 1239 | disable_ioapic_support(); |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1240 | return; |
| 1241 | } |
| 1242 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1243 | #ifdef CONFIG_X86_32 |
| 1244 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
Ingo Molnar | 08125d3 | 2009-01-28 05:08:44 +0100 | [diff] [blame] | 1245 | if (lapic_is_integrated() && apic->disable_esr) { |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1246 | apic_write(APIC_ESR, 0); |
| 1247 | apic_write(APIC_ESR, 0); |
| 1248 | apic_write(APIC_ESR, 0); |
| 1249 | apic_write(APIC_ESR, 0); |
| 1250 | } |
| 1251 | #endif |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1252 | perf_events_lapic_init(); |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1253 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1254 | /* |
| 1255 | * Double-check whether this APIC is really registered. |
| 1256 | * This is meaningless in clustered apic mode, so we skip it. |
| 1257 | */ |
Daniel Walker | c2777f9 | 2009-09-12 10:40:20 -0700 | [diff] [blame] | 1258 | BUG_ON(!apic->apic_id_registered()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1259 | |
| 1260 | /* |
| 1261 | * Intel recommends to set DFR, LDR and TPR before enabling |
| 1262 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel |
| 1263 | * document number 292116). So here it goes... |
| 1264 | */ |
Ingo Molnar | a5c4329 | 2009-01-28 06:50:47 +0100 | [diff] [blame] | 1265 | apic->init_apic_ldr(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1266 | |
Tejun Heo | 6f802c4 | 2011-01-23 14:37:31 +0100 | [diff] [blame] | 1267 | #ifdef CONFIG_X86_32 |
| 1268 | /* |
Tejun Heo | acb8bc0 | 2011-01-23 14:37:33 +0100 | [diff] [blame] | 1269 | * APIC LDR is initialized. If logical_apicid mapping was |
| 1270 | * initialized during get_smp_config(), make sure it matches the |
| 1271 | * actual value. |
Tejun Heo | 6f802c4 | 2011-01-23 14:37:31 +0100 | [diff] [blame] | 1272 | */ |
Tejun Heo | acb8bc0 | 2011-01-23 14:37:33 +0100 | [diff] [blame] | 1273 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
| 1274 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); |
| 1275 | /* always use the value from LDR */ |
Tejun Heo | 6f802c4 | 2011-01-23 14:37:31 +0100 | [diff] [blame] | 1276 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
| 1277 | logical_smp_processor_id(); |
Tejun Heo | c4b90c1 | 2011-05-02 14:18:52 +0200 | [diff] [blame] | 1278 | |
| 1279 | /* |
| 1280 | * Some NUMA implementations (NUMAQ) don't initialize apicid to |
| 1281 | * node mapping during NUMA init. Now that logical apicid is |
| 1282 | * guaranteed to be known, give it another chance. This is already |
| 1283 | * a bit too late - percpu allocation has already happened without |
| 1284 | * proper NUMA affinity. |
| 1285 | */ |
Tejun Heo | 84914ed0 | 2011-05-02 14:18:52 +0200 | [diff] [blame] | 1286 | if (apic->x86_32_numa_cpu_node) |
| 1287 | set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu), |
| 1288 | apic->x86_32_numa_cpu_node(cpu)); |
Tejun Heo | 6f802c4 | 2011-01-23 14:37:31 +0100 | [diff] [blame] | 1289 | #endif |
| 1290 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1291 | /* |
| 1292 | * Set Task Priority to 'accept all'. We never change this |
| 1293 | * later on. |
| 1294 | */ |
| 1295 | value = apic_read(APIC_TASKPRI); |
| 1296 | value &= ~APIC_TPRI_MASK; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1297 | apic_write(APIC_TASKPRI, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1298 | |
| 1299 | /* |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1300 | * After a crash, we no longer service the interrupts and a pending |
| 1301 | * interrupt from previous kernel might still have ISR bit set. |
| 1302 | * |
| 1303 | * Most probably by now CPU has serviced that pending interrupt and |
| 1304 | * it might not have done the ack_APIC_irq() because it thought, |
| 1305 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it |
| 1306 | * does not clear the ISR bit and cpu thinks it has already serivced |
| 1307 | * the interrupt. Hence a vector might get locked. It was noticed |
| 1308 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. |
| 1309 | */ |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1310 | do { |
| 1311 | queued = 0; |
| 1312 | for (i = APIC_ISR_NR - 1; i >= 0; i--) |
| 1313 | queued |= apic_read(APIC_IRR + i*0x10); |
| 1314 | |
| 1315 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { |
| 1316 | value = apic_read(APIC_ISR + i*0x10); |
| 1317 | for (j = 31; j >= 0; j--) { |
| 1318 | if (value & (1<<j)) { |
| 1319 | ack_APIC_irq(); |
| 1320 | acked++; |
| 1321 | } |
| 1322 | } |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1323 | } |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1324 | if (acked > 256) { |
| 1325 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", |
| 1326 | acked); |
| 1327 | break; |
| 1328 | } |
Shai Fultheim | 42fa425 | 2012-04-20 01:12:32 +0300 | [diff] [blame] | 1329 | if (queued) { |
| 1330 | if (cpu_has_tsc) { |
| 1331 | rdtscll(ntsc); |
| 1332 | max_loops = (cpu_khz << 10) - (ntsc - tsc); |
| 1333 | } else |
| 1334 | max_loops--; |
| 1335 | } |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1336 | } while (queued && max_loops > 0); |
| 1337 | WARN_ON(max_loops <= 0); |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1338 | |
| 1339 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1340 | * Now that we are all set up, enable the APIC |
| 1341 | */ |
| 1342 | value = apic_read(APIC_SPIV); |
| 1343 | value &= ~APIC_VECTOR_MASK; |
| 1344 | /* |
| 1345 | * Enable APIC |
| 1346 | */ |
| 1347 | value |= APIC_SPIV_APIC_ENABLED; |
| 1348 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1349 | #ifdef CONFIG_X86_32 |
| 1350 | /* |
| 1351 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with |
| 1352 | * certain networking cards. If high frequency interrupts are |
| 1353 | * happening on a particular IOAPIC pin, plus the IOAPIC routing |
| 1354 | * entry is masked/unmasked at a high rate as well then sooner or |
| 1355 | * later IOAPIC line gets 'stuck', no more interrupts are received |
| 1356 | * from the device. If focus CPU is disabled then the hang goes |
| 1357 | * away, oh well :-( |
| 1358 | * |
| 1359 | * [ This bug can be reproduced easily with a level-triggered |
| 1360 | * PCI Ne2000 networking cards and PII/PIII processors, dual |
| 1361 | * BX chipset. ] |
| 1362 | */ |
| 1363 | /* |
| 1364 | * Actually disabling the focus CPU check just makes the hang less |
| 1365 | * frequent as it makes the interrupt distributon model be more |
| 1366 | * like LRU than MRU (the short-term load is more even across CPUs). |
| 1367 | * See also the comment in end_level_ioapic_irq(). --macro |
| 1368 | */ |
| 1369 | |
| 1370 | /* |
| 1371 | * - enable focus processor (bit==0) |
| 1372 | * - 64bit mode always use processor focus |
| 1373 | * so no need to set it |
| 1374 | */ |
| 1375 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 1376 | #endif |
Andi Kleen | 3f14c74 | 2006-09-26 10:52:29 +0200 | [diff] [blame] | 1377 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1378 | /* |
| 1379 | * Set spurious IRQ vector |
| 1380 | */ |
| 1381 | value |= SPURIOUS_APIC_VECTOR; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1382 | apic_write(APIC_SPIV, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1383 | |
| 1384 | /* |
| 1385 | * Set up LVT0, LVT1: |
| 1386 | * |
| 1387 | * set up through-local-APIC on the BP's LINT0. This is not |
| 1388 | * strictly necessary in pure symmetric-IO mode, but sometimes |
| 1389 | * we delegate interrupts to the 8259A. |
| 1390 | */ |
| 1391 | /* |
| 1392 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro |
| 1393 | */ |
| 1394 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1395 | if (!cpu && (pic_mode || !value)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1396 | value = APIC_DM_EXTINT; |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1397 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1398 | } else { |
| 1399 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1400 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1401 | } |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1402 | apic_write(APIC_LVT0, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1403 | |
| 1404 | /* |
| 1405 | * only the BP should see the LINT1 NMI signal, obviously. |
| 1406 | */ |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1407 | if (!cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1408 | value = APIC_DM_NMI; |
| 1409 | else |
| 1410 | value = APIC_DM_NMI | APIC_LVT_MASKED; |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1411 | if (!lapic_is_integrated()) /* 82489DX */ |
| 1412 | value |= APIC_LVT_LEVEL_TRIGGER; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1413 | apic_write(APIC_LVT1, value); |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1414 | |
Andi Kleen | be71b85 | 2009-02-12 13:49:38 +0100 | [diff] [blame] | 1415 | #ifdef CONFIG_X86_MCE_INTEL |
| 1416 | /* Recheck CMCI information after local APIC is up on CPU #0 */ |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1417 | if (!cpu) |
Andi Kleen | be71b85 | 2009-02-12 13:49:38 +0100 | [diff] [blame] | 1418 | cmci_recheck(); |
| 1419 | #endif |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1420 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1421 | |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1422 | void __cpuinit end_local_APIC_setup(void) |
| 1423 | { |
| 1424 | lapic_setup_esr(); |
Cyrill Gorcunov | fa6b95f | 2008-08-18 20:45:58 +0400 | [diff] [blame] | 1425 | |
| 1426 | #ifdef CONFIG_X86_32 |
Cyrill Gorcunov | 1b4ee4e | 2008-08-18 23:12:33 +0400 | [diff] [blame] | 1427 | { |
| 1428 | unsigned int value; |
| 1429 | /* Disable the local apic timer */ |
| 1430 | value = apic_read(APIC_LVTT); |
| 1431 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
| 1432 | apic_write(APIC_LVTT, value); |
| 1433 | } |
Cyrill Gorcunov | fa6b95f | 2008-08-18 20:45:58 +0400 | [diff] [blame] | 1434 | #endif |
| 1435 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1436 | apic_pm_activate(); |
Jan Beulich | 2fb270f | 2011-02-09 08:21:02 +0000 | [diff] [blame] | 1437 | } |
| 1438 | |
| 1439 | void __init bsp_end_local_APIC_setup(void) |
| 1440 | { |
| 1441 | end_local_APIC_setup(); |
Kenji Kaneshige | 7f7fbf4 | 2010-11-30 22:22:28 -0800 | [diff] [blame] | 1442 | |
| 1443 | /* |
| 1444 | * Now that local APIC setup is completed for BP, configure the fault |
| 1445 | * handling for interrupt remapping. |
| 1446 | */ |
Suresh Siddha | 95a02e9 | 2012-03-30 11:47:07 -0700 | [diff] [blame] | 1447 | if (irq_remapping_enabled) |
| 1448 | irq_remap_enable_fault_handling(); |
Kenji Kaneshige | 7f7fbf4 | 2010-11-30 22:22:28 -0800 | [diff] [blame] | 1449 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1450 | } |
| 1451 | |
Yinghai Lu | 06cd9a7 | 2009-02-16 17:29:58 -0800 | [diff] [blame] | 1452 | #ifdef CONFIG_X86_X2APIC |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1453 | /* |
| 1454 | * Need to disable xapic and x2apic at the same time and then enable xapic mode |
| 1455 | */ |
| 1456 | static inline void __disable_x2apic(u64 msr) |
| 1457 | { |
| 1458 | wrmsrl(MSR_IA32_APICBASE, |
| 1459 | msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); |
| 1460 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); |
| 1461 | } |
| 1462 | |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 1463 | static __init void disable_x2apic(void) |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1464 | { |
| 1465 | u64 msr; |
| 1466 | |
| 1467 | if (!cpu_has_x2apic) |
| 1468 | return; |
| 1469 | |
| 1470 | rdmsrl(MSR_IA32_APICBASE, msr); |
| 1471 | if (msr & X2APIC_ENABLE) { |
| 1472 | u32 x2apic_id = read_apic_id(); |
| 1473 | |
| 1474 | if (x2apic_id >= 255) |
| 1475 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); |
| 1476 | |
| 1477 | pr_info("Disabling x2apic\n"); |
| 1478 | __disable_x2apic(msr); |
| 1479 | |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 1480 | if (nox2apic) { |
| 1481 | clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC); |
| 1482 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); |
| 1483 | } |
| 1484 | |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1485 | x2apic_disabled = 1; |
| 1486 | x2apic_mode = 0; |
| 1487 | |
| 1488 | register_lapic_address(mp_lapic_addr); |
| 1489 | } |
| 1490 | } |
| 1491 | |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1492 | void check_x2apic(void) |
| 1493 | { |
Suresh Siddha | ef1f87a | 2009-02-21 14:23:21 -0800 | [diff] [blame] | 1494 | if (x2apic_enabled()) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1495 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 1496 | x2apic_preenabled = x2apic_mode = 1; |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1497 | } |
| 1498 | } |
| 1499 | |
| 1500 | void enable_x2apic(void) |
| 1501 | { |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1502 | u64 msr; |
| 1503 | |
| 1504 | rdmsrl(MSR_IA32_APICBASE, msr); |
| 1505 | if (x2apic_disabled) { |
| 1506 | __disable_x2apic(msr); |
| 1507 | return; |
| 1508 | } |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1509 | |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 1510 | if (!x2apic_mode) |
Yinghai Lu | 06cd9a7 | 2009-02-16 17:29:58 -0800 | [diff] [blame] | 1511 | return; |
| 1512 | |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1513 | if (!(msr & X2APIC_ENABLE)) { |
Mike Travis | 450b1e8 | 2009-12-11 08:08:50 -0800 | [diff] [blame] | 1514 | printk_once(KERN_INFO "Enabling x2apic\n"); |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1515 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1516 | } |
| 1517 | } |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 1518 | #endif /* CONFIG_X86_X2APIC */ |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1519 | |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1520 | int __init enable_IR(void) |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1521 | { |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 1522 | #ifdef CONFIG_IRQ_REMAP |
Suresh Siddha | 95a02e9 | 2012-03-30 11:47:07 -0700 | [diff] [blame] | 1523 | if (!irq_remapping_supported()) { |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 1524 | pr_debug("intr-remapping not supported\n"); |
Suresh Siddha | 41750d3 | 2011-08-23 17:05:18 -0700 | [diff] [blame] | 1525 | return -1; |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 1526 | } |
| 1527 | |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 1528 | if (!x2apic_preenabled && skip_ioapic_setup) { |
| 1529 | pr_info("Skipped enabling intr-remap because of skipping " |
| 1530 | "io-apic setup\n"); |
Suresh Siddha | 41750d3 | 2011-08-23 17:05:18 -0700 | [diff] [blame] | 1531 | return -1; |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1532 | } |
| 1533 | |
Suresh Siddha | 95a02e9 | 2012-03-30 11:47:07 -0700 | [diff] [blame] | 1534 | return irq_remapping_enable(); |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1535 | #endif |
Suresh Siddha | 41750d3 | 2011-08-23 17:05:18 -0700 | [diff] [blame] | 1536 | return -1; |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1537 | } |
| 1538 | |
| 1539 | void __init enable_IR_x2apic(void) |
| 1540 | { |
| 1541 | unsigned long flags; |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1542 | int ret, x2apic_enabled = 0; |
Joerg Roedel | 736baef | 2012-03-30 11:47:00 -0700 | [diff] [blame] | 1543 | int hardware_init_ret; |
Yinghai Lu | b7f42ab | 2009-08-17 11:19:40 -0700 | [diff] [blame] | 1544 | |
Joerg Roedel | 736baef | 2012-03-30 11:47:00 -0700 | [diff] [blame] | 1545 | /* Make sure irq_remap_ops are initialized */ |
Suresh Siddha | 95a02e9 | 2012-03-30 11:47:07 -0700 | [diff] [blame] | 1546 | setup_irq_remapping_ops(); |
Joerg Roedel | 736baef | 2012-03-30 11:47:00 -0700 | [diff] [blame] | 1547 | |
Suresh Siddha | 95a02e9 | 2012-03-30 11:47:07 -0700 | [diff] [blame] | 1548 | hardware_init_ret = irq_remapping_prepare(); |
Joerg Roedel | 736baef | 2012-03-30 11:47:00 -0700 | [diff] [blame] | 1549 | if (hardware_init_ret && !x2apic_supported()) |
Yinghai Lu | e670761 | 2009-11-21 00:23:37 -0800 | [diff] [blame] | 1550 | return; |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1551 | |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 1552 | ret = save_ioapic_entries(); |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1553 | if (ret) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1554 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1555 | return; |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1556 | } |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1557 | |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 1558 | local_irq_save(flags); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1559 | legacy_pic->mask_all(); |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 1560 | mask_ioapic_entries(); |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 1561 | |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 1562 | if (x2apic_preenabled && nox2apic) |
| 1563 | disable_x2apic(); |
| 1564 | |
Joerg Roedel | 736baef | 2012-03-30 11:47:00 -0700 | [diff] [blame] | 1565 | if (hardware_init_ret) |
Suresh Siddha | 41750d3 | 2011-08-23 17:05:18 -0700 | [diff] [blame] | 1566 | ret = -1; |
Yinghai Lu | b7f42ab | 2009-08-17 11:19:40 -0700 | [diff] [blame] | 1567 | else |
| 1568 | ret = enable_IR(); |
| 1569 | |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1570 | if (!x2apic_supported()) |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 1571 | goto skip_x2apic; |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1572 | |
Suresh Siddha | 41750d3 | 2011-08-23 17:05:18 -0700 | [diff] [blame] | 1573 | if (ret < 0) { |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1574 | /* IR is required if there is APIC ID > 255 even when running |
| 1575 | * under KVM |
| 1576 | */ |
Sheng Yang | 2904ed8 | 2010-12-21 14:18:48 +0800 | [diff] [blame] | 1577 | if (max_physical_apicid > 255 || |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1578 | !hypervisor_x2apic_available()) { |
| 1579 | if (x2apic_preenabled) |
| 1580 | disable_x2apic(); |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 1581 | goto skip_x2apic; |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1582 | } |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1583 | /* |
| 1584 | * without IR all CPUs can be addressed by IOAPIC/MSI |
| 1585 | * only in physical mode |
| 1586 | */ |
| 1587 | x2apic_force_phys(); |
| 1588 | } |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1589 | |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1590 | if (ret == IRQ_REMAP_XAPIC_MODE) { |
| 1591 | pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n"); |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 1592 | goto skip_x2apic; |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1593 | } |
Suresh Siddha | 41750d3 | 2011-08-23 17:05:18 -0700 | [diff] [blame] | 1594 | |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1595 | x2apic_enabled = 1; |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 1596 | |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 1597 | if (x2apic_supported() && !x2apic_mode) { |
| 1598 | x2apic_mode = 1; |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1599 | enable_x2apic(); |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 1600 | pr_info("Enabled x2apic\n"); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1601 | } |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1602 | |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 1603 | skip_x2apic: |
Suresh Siddha | 41750d3 | 2011-08-23 17:05:18 -0700 | [diff] [blame] | 1604 | if (ret < 0) /* IR enabling failed */ |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 1605 | restore_ioapic_entries(); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1606 | legacy_pic->restore_mask(); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1607 | local_irq_restore(flags); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1608 | } |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 1609 | |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1610 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1611 | /* |
| 1612 | * Detect and enable local APICs on non-SMP boards. |
| 1613 | * Original code written by Keir Fraser. |
| 1614 | * On AMD64 we trust the BIOS - if it says no APIC it is likely |
| 1615 | * not correctly set up (usually the APIC timer won't work etc.) |
| 1616 | */ |
| 1617 | static int __init detect_init_APIC(void) |
| 1618 | { |
| 1619 | if (!cpu_has_apic) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1620 | pr_info("No local APIC present\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1621 | return -1; |
| 1622 | } |
| 1623 | |
| 1624 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1625 | return 0; |
| 1626 | } |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1627 | #else |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1628 | |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 1629 | static int __init apic_verify(void) |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1630 | { |
| 1631 | u32 features, h, l; |
| 1632 | |
| 1633 | /* |
| 1634 | * The APIC feature bit should now be enabled |
| 1635 | * in `cpuid' |
| 1636 | */ |
| 1637 | features = cpuid_edx(1); |
| 1638 | if (!(features & (1 << X86_FEATURE_APIC))) { |
| 1639 | pr_warning("Could not enable APIC!\n"); |
| 1640 | return -1; |
| 1641 | } |
| 1642 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
| 1643 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
| 1644 | |
| 1645 | /* The BIOS may have set up the APIC at some other address */ |
Bryan O'Donoghue | cbf2829 | 2012-04-18 17:37:39 +0100 | [diff] [blame] | 1646 | if (boot_cpu_data.x86 >= 6) { |
| 1647 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1648 | if (l & MSR_IA32_APICBASE_ENABLE) |
| 1649 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; |
| 1650 | } |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1651 | |
| 1652 | pr_info("Found and enabled local APIC!\n"); |
| 1653 | return 0; |
| 1654 | } |
| 1655 | |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 1656 | int __init apic_force_enable(unsigned long addr) |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1657 | { |
| 1658 | u32 h, l; |
| 1659 | |
| 1660 | if (disable_apic) |
| 1661 | return -1; |
| 1662 | |
| 1663 | /* |
| 1664 | * Some BIOSes disable the local APIC in the APIC_BASE |
| 1665 | * MSR. This can only be done in software for Intel P6 or later |
| 1666 | * and AMD K7 (Model > 1) or later. |
| 1667 | */ |
Bryan O'Donoghue | cbf2829 | 2012-04-18 17:37:39 +0100 | [diff] [blame] | 1668 | if (boot_cpu_data.x86 >= 6) { |
| 1669 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1670 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { |
| 1671 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
| 1672 | l &= ~MSR_IA32_APICBASE_BASE; |
| 1673 | l |= MSR_IA32_APICBASE_ENABLE | addr; |
| 1674 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 1675 | enabled_via_apicbase = 1; |
| 1676 | } |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1677 | } |
| 1678 | return apic_verify(); |
| 1679 | } |
| 1680 | |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1681 | /* |
| 1682 | * Detect and initialize APIC |
| 1683 | */ |
| 1684 | static int __init detect_init_APIC(void) |
| 1685 | { |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1686 | /* Disabled by kernel option? */ |
| 1687 | if (disable_apic) |
| 1688 | return -1; |
| 1689 | |
| 1690 | switch (boot_cpu_data.x86_vendor) { |
| 1691 | case X86_VENDOR_AMD: |
| 1692 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || |
Borislav Petkov | 8587706 | 2009-02-03 16:24:22 +0100 | [diff] [blame] | 1693 | (boot_cpu_data.x86 >= 15)) |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1694 | break; |
| 1695 | goto no_apic; |
| 1696 | case X86_VENDOR_INTEL: |
| 1697 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || |
| 1698 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) |
| 1699 | break; |
| 1700 | goto no_apic; |
| 1701 | default: |
| 1702 | goto no_apic; |
| 1703 | } |
| 1704 | |
| 1705 | if (!cpu_has_apic) { |
| 1706 | /* |
| 1707 | * Over-ride BIOS and try to enable the local APIC only if |
| 1708 | * "lapic" specified. |
| 1709 | */ |
| 1710 | if (!force_enable_local_apic) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1711 | pr_info("Local APIC disabled by BIOS -- " |
| 1712 | "you can enable it with \"lapic\"\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1713 | return -1; |
| 1714 | } |
Thomas Gleixner | a906fda | 2011-02-25 16:09:31 +0100 | [diff] [blame] | 1715 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1716 | return -1; |
| 1717 | } else { |
| 1718 | if (apic_verify()) |
| 1719 | return -1; |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1720 | } |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1721 | |
| 1722 | apic_pm_activate(); |
| 1723 | |
| 1724 | return 0; |
| 1725 | |
| 1726 | no_apic: |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1727 | pr_info("No local APIC present or hardware disabled\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1728 | return -1; |
| 1729 | } |
| 1730 | #endif |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1731 | |
| 1732 | /** |
| 1733 | * init_apic_mappings - initialize APIC mappings |
| 1734 | */ |
| 1735 | void __init init_apic_mappings(void) |
| 1736 | { |
Yinghai Lu | 4401da6 | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1737 | unsigned int new_apicid; |
| 1738 | |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 1739 | if (x2apic_mode) { |
Yinghai Lu | 4c9961d | 2008-07-11 18:44:16 -0700 | [diff] [blame] | 1740 | boot_cpu_physical_apicid = read_apic_id(); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1741 | return; |
| 1742 | } |
| 1743 | |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1744 | /* If no local APIC can be found return early */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1745 | if (!smp_found_config && detect_init_APIC()) { |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1746 | /* lets NOP'ify apic operations */ |
Cyrill Gorcunov | cec6be6 | 2009-05-11 17:41:40 +0400 | [diff] [blame] | 1747 | pr_info("APIC: disable apic facility\n"); |
| 1748 | apic_disable(); |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1749 | } else { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1750 | apic_phys = mp_lapic_addr; |
| 1751 | |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1752 | /* |
| 1753 | * acpi lapic path already maps that address in |
| 1754 | * acpi_register_lapic_address() |
| 1755 | */ |
Eric W. Biederman | 5989cd6 | 2010-08-04 13:30:27 -0700 | [diff] [blame] | 1756 | if (!acpi_lapic && !smp_found_config) |
Yinghai Lu | 326a2e6 | 2010-12-07 00:55:38 -0800 | [diff] [blame] | 1757 | register_lapic_address(apic_phys); |
Cyrill Gorcunov | cec6be6 | 2009-05-11 17:41:40 +0400 | [diff] [blame] | 1758 | } |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1759 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1760 | /* |
| 1761 | * Fetch the APIC ID of the BSP in case we have a |
| 1762 | * default configuration (or the MP table is broken). |
| 1763 | */ |
Yinghai Lu | 4401da6 | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1764 | new_apicid = read_apic_id(); |
| 1765 | if (boot_cpu_physical_apicid != new_apicid) { |
| 1766 | boot_cpu_physical_apicid = new_apicid; |
Cyrill Gorcunov | 103428e | 2009-06-07 16:48:40 +0400 | [diff] [blame] | 1767 | /* |
| 1768 | * yeah -- we lie about apic_version |
| 1769 | * in case if apic was disabled via boot option |
| 1770 | * but it's not a problem for SMP compiled kernel |
| 1771 | * since smp_sanity_check is prepared for such a case |
| 1772 | * and disable smp mode |
| 1773 | */ |
Yinghai Lu | 4401da6 | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1774 | apic_version[new_apicid] = |
| 1775 | GET_APIC_VERSION(apic_read(APIC_LVR)); |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 1776 | } |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1777 | } |
| 1778 | |
Yinghai Lu | c0104d3 | 2010-12-07 00:55:17 -0800 | [diff] [blame] | 1779 | void __init register_lapic_address(unsigned long address) |
| 1780 | { |
| 1781 | mp_lapic_addr = address; |
| 1782 | |
Yinghai Lu | 0450193 | 2010-12-07 00:55:56 -0800 | [diff] [blame] | 1783 | if (!x2apic_mode) { |
| 1784 | set_fixmap_nocache(FIX_APIC_BASE, address); |
| 1785 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
| 1786 | APIC_BASE, mp_lapic_addr); |
| 1787 | } |
Yinghai Lu | c0104d3 | 2010-12-07 00:55:17 -0800 | [diff] [blame] | 1788 | if (boot_cpu_physical_apicid == -1U) { |
| 1789 | boot_cpu_physical_apicid = read_apic_id(); |
| 1790 | apic_version[boot_cpu_physical_apicid] = |
| 1791 | GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 1792 | } |
| 1793 | } |
| 1794 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1795 | /* |
| 1796 | * This initializes the IO-APIC and APIC hardware if this is |
| 1797 | * a UP kernel. |
| 1798 | */ |
Yinghai Lu | 56d91f1 | 2010-12-16 19:09:24 -0800 | [diff] [blame] | 1799 | int apic_version[MAX_LOCAL_APIC]; |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 1800 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1801 | int __init APIC_init_uniprocessor(void) |
| 1802 | { |
| 1803 | if (disable_apic) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1804 | pr_info("Apic disabled\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1805 | return -1; |
| 1806 | } |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1807 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1808 | if (!cpu_has_apic) { |
| 1809 | disable_apic = 1; |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1810 | pr_info("Apic disabled by BIOS\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1811 | return -1; |
| 1812 | } |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1813 | #else |
| 1814 | if (!smp_found_config && !cpu_has_apic) |
| 1815 | return -1; |
| 1816 | |
| 1817 | /* |
| 1818 | * Complain if the BIOS pretends there is one. |
| 1819 | */ |
| 1820 | if (!cpu_has_apic && |
| 1821 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1822 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
| 1823 | boot_cpu_physical_apicid); |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1824 | return -1; |
| 1825 | } |
| 1826 | #endif |
| 1827 | |
Ingo Molnar | 72ce016 | 2009-01-28 06:50:47 +0100 | [diff] [blame] | 1828 | default_setup_apic_routing(); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1829 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1830 | verify_local_APIC(); |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1831 | connect_bsp_APIC(); |
| 1832 | |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1833 | #ifdef CONFIG_X86_64 |
Glauber de Oliveira Costa | c70dcb7 | 2008-03-19 14:25:58 -0300 | [diff] [blame] | 1834 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1835 | #else |
| 1836 | /* |
| 1837 | * Hack: In case of kdump, after a crash, kernel might be booting |
| 1838 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid |
| 1839 | * might be zero if read from MP tables. Get it from LAPIC. |
| 1840 | */ |
| 1841 | # ifdef CONFIG_CRASH_DUMP |
| 1842 | boot_cpu_physical_apicid = read_apic_id(); |
| 1843 | # endif |
| 1844 | #endif |
| 1845 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1846 | setup_local_APIC(); |
| 1847 | |
Yinghai Lu | 88d0f55 | 2009-02-14 23:57:28 -0800 | [diff] [blame] | 1848 | #ifdef CONFIG_X86_IO_APIC |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1849 | /* |
| 1850 | * Now enable IO-APICs, actually call clear_IO_APIC |
Yinghai Lu | 98c061b | 2009-02-16 00:00:50 -0800 | [diff] [blame] | 1851 | * We need clear_IO_APIC before enabling error vector |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1852 | */ |
| 1853 | if (!skip_ioapic_setup && nr_ioapics) |
| 1854 | enable_IO_APIC(); |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1855 | #endif |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1856 | |
Jan Beulich | 2fb270f | 2011-02-09 08:21:02 +0000 | [diff] [blame] | 1857 | bsp_end_local_APIC_setup(); |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1858 | |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1859 | #ifdef CONFIG_X86_IO_APIC |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1860 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
| 1861 | setup_IO_APIC(); |
Yinghai Lu | 98c061b | 2009-02-16 00:00:50 -0800 | [diff] [blame] | 1862 | else { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1863 | nr_ioapics = 0; |
Yinghai Lu | 98c061b | 2009-02-16 00:00:50 -0800 | [diff] [blame] | 1864 | } |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1865 | #endif |
| 1866 | |
Thomas Gleixner | 736deca | 2009-08-19 12:35:53 +0200 | [diff] [blame] | 1867 | x86_init.timers.setup_percpu_clockev(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1868 | return 0; |
| 1869 | } |
| 1870 | |
| 1871 | /* |
| 1872 | * Local APIC interrupts |
| 1873 | */ |
| 1874 | |
| 1875 | /* |
| 1876 | * This interrupt should _never_ happen with our APIC/SMP architecture |
| 1877 | */ |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1878 | void smp_spurious_interrupt(struct pt_regs *regs) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1879 | { |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1880 | u32 v; |
| 1881 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1882 | irq_enter(); |
Frederic Weisbecker | 98ad1cc | 2011-10-07 18:22:09 +0200 | [diff] [blame] | 1883 | exit_idle(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1884 | /* |
| 1885 | * Check if this really is a spurious interrupt and ACK it |
| 1886 | * if it is a vectored one. Just in case... |
| 1887 | * Spurious interrupts should not be ACKed. |
| 1888 | */ |
| 1889 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
| 1890 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) |
| 1891 | ack_APIC_irq(); |
| 1892 | |
Hiroshi Shimamoto | 915b0d0 | 2008-12-08 19:19:26 -0800 | [diff] [blame] | 1893 | inc_irq_stat(irq_spurious_count); |
| 1894 | |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1895 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1896 | pr_info("spurious APIC interrupt on CPU#%d, " |
| 1897 | "should never happen.\n", smp_processor_id()); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1898 | irq_exit(); |
| 1899 | } |
| 1900 | |
| 1901 | /* |
| 1902 | * This interrupt should never happen with our APIC/SMP architecture |
| 1903 | */ |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1904 | void smp_error_interrupt(struct pt_regs *regs) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1905 | { |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1906 | u32 v0, v1; |
| 1907 | u32 i = 0; |
| 1908 | static const char * const error_interrupt_reason[] = { |
| 1909 | "Send CS error", /* APIC Error Bit 0 */ |
| 1910 | "Receive CS error", /* APIC Error Bit 1 */ |
| 1911 | "Send accept error", /* APIC Error Bit 2 */ |
| 1912 | "Receive accept error", /* APIC Error Bit 3 */ |
| 1913 | "Redirectable IPI", /* APIC Error Bit 4 */ |
| 1914 | "Send illegal vector", /* APIC Error Bit 5 */ |
| 1915 | "Received illegal vector", /* APIC Error Bit 6 */ |
| 1916 | "Illegal register address", /* APIC Error Bit 7 */ |
| 1917 | }; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1918 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1919 | irq_enter(); |
Frederic Weisbecker | 98ad1cc | 2011-10-07 18:22:09 +0200 | [diff] [blame] | 1920 | exit_idle(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1921 | /* First tickle the hardware, only then report what went on. -- REW */ |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1922 | v0 = apic_read(APIC_ESR); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1923 | apic_write(APIC_ESR, 0); |
| 1924 | v1 = apic_read(APIC_ESR); |
| 1925 | ack_APIC_irq(); |
| 1926 | atomic_inc(&irq_err_count); |
| 1927 | |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1928 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)", |
| 1929 | smp_processor_id(), v0 , v1); |
| 1930 | |
| 1931 | v1 = v1 & 0xff; |
| 1932 | while (v1) { |
| 1933 | if (v1 & 0x1) |
| 1934 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); |
| 1935 | i++; |
| 1936 | v1 >>= 1; |
Peter Senna Tschudin | 4b8073e | 2012-09-18 18:36:14 +0200 | [diff] [blame] | 1937 | } |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1938 | |
| 1939 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); |
| 1940 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1941 | irq_exit(); |
| 1942 | } |
| 1943 | |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1944 | /** |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1945 | * connect_bsp_APIC - attach the APIC to the interrupt system |
| 1946 | */ |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1947 | void __init connect_bsp_APIC(void) |
| 1948 | { |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1949 | #ifdef CONFIG_X86_32 |
| 1950 | if (pic_mode) { |
| 1951 | /* |
| 1952 | * Do not trust the local APIC being empty at bootup. |
| 1953 | */ |
| 1954 | clear_local_APIC(); |
| 1955 | /* |
| 1956 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's |
| 1957 | * local APIC to INT and NMI lines. |
| 1958 | */ |
| 1959 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " |
| 1960 | "enabling APIC mode.\n"); |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 1961 | imcr_pic_to_apic(); |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1962 | } |
| 1963 | #endif |
Ingo Molnar | 4904033 | 2009-01-28 12:43:18 +0100 | [diff] [blame] | 1964 | if (apic->enable_apic_mode) |
| 1965 | apic->enable_apic_mode(); |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1966 | } |
| 1967 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 1968 | /** |
| 1969 | * disconnect_bsp_APIC - detach the APIC from the interrupt system |
| 1970 | * @virt_wire_setup: indicates, whether virtual wire mode is selected |
| 1971 | * |
| 1972 | * Virtual wire mode is necessary to deliver legacy interrupts even when the |
| 1973 | * APIC is disabled. |
| 1974 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1975 | void disconnect_bsp_APIC(int virt_wire_setup) |
| 1976 | { |
Cyrill Gorcunov | 1b4ee4e | 2008-08-18 23:12:33 +0400 | [diff] [blame] | 1977 | unsigned int value; |
| 1978 | |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 1979 | #ifdef CONFIG_X86_32 |
| 1980 | if (pic_mode) { |
| 1981 | /* |
| 1982 | * Put the board back into PIC mode (has an effect only on |
| 1983 | * certain older boards). Note that APIC interrupts, including |
| 1984 | * IPIs, won't work beyond this point! The only exception are |
| 1985 | * INIT IPIs. |
| 1986 | */ |
| 1987 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " |
| 1988 | "entering PIC mode.\n"); |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 1989 | imcr_apic_to_pic(); |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 1990 | return; |
| 1991 | } |
| 1992 | #endif |
| 1993 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1994 | /* Go back to Virtual Wire compatibility mode */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1995 | |
| 1996 | /* For the spurious interrupt use vector F, and enable it */ |
| 1997 | value = apic_read(APIC_SPIV); |
| 1998 | value &= ~APIC_VECTOR_MASK; |
| 1999 | value |= APIC_SPIV_APIC_ENABLED; |
| 2000 | value |= 0xf; |
| 2001 | apic_write(APIC_SPIV, value); |
| 2002 | |
| 2003 | if (!virt_wire_setup) { |
| 2004 | /* |
| 2005 | * For LVT0 make it edge triggered, active high, |
| 2006 | * external and enabled |
| 2007 | */ |
| 2008 | value = apic_read(APIC_LVT0); |
| 2009 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | |
| 2010 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 2011 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
| 2012 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 2013 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
| 2014 | apic_write(APIC_LVT0, value); |
| 2015 | } else { |
| 2016 | /* Disable LVT0 */ |
| 2017 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
| 2018 | } |
| 2019 | |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 2020 | /* |
| 2021 | * For LVT1 make it edge triggered, active high, |
| 2022 | * nmi and enabled |
| 2023 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2024 | value = apic_read(APIC_LVT1); |
| 2025 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | |
| 2026 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 2027 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
| 2028 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 2029 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); |
| 2030 | apic_write(APIC_LVT1, value); |
| 2031 | } |
| 2032 | |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2033 | void __cpuinit generic_processor_info(int apicid, int version) |
| 2034 | { |
Vivek Goyal | 14cb6dc | 2011-07-08 13:19:26 -0400 | [diff] [blame] | 2035 | int cpu, max = nr_cpu_ids; |
| 2036 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, |
| 2037 | phys_cpu_present_map); |
| 2038 | |
| 2039 | /* |
| 2040 | * If boot cpu has not been detected yet, then only allow upto |
| 2041 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu |
| 2042 | */ |
| 2043 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && |
| 2044 | apicid != boot_cpu_physical_apicid) { |
| 2045 | int thiscpu = max + disabled_cpus - 1; |
| 2046 | |
| 2047 | pr_warning( |
| 2048 | "ACPI: NR_CPUS/possible_cpus limit of %i almost" |
| 2049 | " reached. Keeping one slot for boot cpu." |
| 2050 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); |
| 2051 | |
| 2052 | disabled_cpus++; |
| 2053 | return; |
| 2054 | } |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2055 | |
Mike Travis | 3b11ce7 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 2056 | if (num_processors >= nr_cpu_ids) { |
Mike Travis | 3b11ce7 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 2057 | int thiscpu = max + disabled_cpus; |
| 2058 | |
| 2059 | pr_warning( |
| 2060 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." |
| 2061 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); |
| 2062 | |
| 2063 | disabled_cpus++; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2064 | return; |
| 2065 | } |
| 2066 | |
| 2067 | num_processors++; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2068 | if (apicid == boot_cpu_physical_apicid) { |
| 2069 | /* |
| 2070 | * x86_bios_cpu_apicid is required to have processors listed |
| 2071 | * in same order as logical cpu numbers. Hence the first |
| 2072 | * entry is BSP, and so on. |
Yinghai Lu | e5fea86 | 2011-02-08 23:22:17 -0800 | [diff] [blame] | 2073 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
| 2074 | * for BSP. |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2075 | */ |
| 2076 | cpu = 0; |
Yinghai Lu | e5fea86 | 2011-02-08 23:22:17 -0800 | [diff] [blame] | 2077 | } else |
| 2078 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
| 2079 | |
| 2080 | /* |
| 2081 | * Validate version |
| 2082 | */ |
| 2083 | if (version == 0x0) { |
| 2084 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", |
| 2085 | cpu, apicid); |
| 2086 | version = 0x10; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2087 | } |
Yinghai Lu | e5fea86 | 2011-02-08 23:22:17 -0800 | [diff] [blame] | 2088 | apic_version[apicid] = version; |
| 2089 | |
| 2090 | if (version != apic_version[boot_cpu_physical_apicid]) { |
| 2091 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", |
| 2092 | apic_version[boot_cpu_physical_apicid], cpu, version); |
| 2093 | } |
| 2094 | |
| 2095 | physid_set(apicid, phys_cpu_present_map); |
Yinghai Lu | e0da336 | 2008-06-08 18:29:22 -0700 | [diff] [blame] | 2096 | if (apicid > max_physical_apicid) |
| 2097 | max_physical_apicid = apicid; |
| 2098 | |
Ingo Molnar | 3e5095d | 2009-01-27 17:07:08 +0100 | [diff] [blame] | 2099 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
Tejun Heo | f10fcd4 | 2009-01-13 20:41:34 +0900 | [diff] [blame] | 2100 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
| 2101 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 2102 | #endif |
Tejun Heo | acb8bc0 | 2011-01-23 14:37:33 +0100 | [diff] [blame] | 2103 | #ifdef CONFIG_X86_32 |
| 2104 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
| 2105 | apic->x86_32_early_logical_apicid(cpu); |
| 2106 | #endif |
Mike Travis | 1de88cd | 2008-12-16 17:34:02 -0800 | [diff] [blame] | 2107 | set_cpu_possible(cpu, true); |
| 2108 | set_cpu_present(cpu, true); |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2109 | } |
| 2110 | |
Suresh Siddha | 0c81c74 | 2008-07-10 11:16:48 -0700 | [diff] [blame] | 2111 | int hard_smp_processor_id(void) |
| 2112 | { |
| 2113 | return read_apic_id(); |
| 2114 | } |
Ingo Molnar | 1dcdd3d | 2009-01-28 17:55:37 +0100 | [diff] [blame] | 2115 | |
| 2116 | void default_init_apic_ldr(void) |
| 2117 | { |
| 2118 | unsigned long val; |
| 2119 | |
| 2120 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
| 2121 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
| 2122 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); |
| 2123 | apic_write(APIC_LDR, val); |
| 2124 | } |
| 2125 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 2126 | int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
| 2127 | const struct cpumask *andmask, |
| 2128 | unsigned int *apicid) |
Alexander Gordeev | 6398268 | 2012-06-05 13:23:44 +0200 | [diff] [blame] | 2129 | { |
Alexander Gordeev | ea3807e | 2012-06-14 09:49:55 +0200 | [diff] [blame] | 2130 | unsigned int cpu; |
Alexander Gordeev | 6398268 | 2012-06-05 13:23:44 +0200 | [diff] [blame] | 2131 | |
| 2132 | for_each_cpu_and(cpu, cpumask, andmask) { |
| 2133 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
| 2134 | break; |
| 2135 | } |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 2136 | |
Alexander Gordeev | ea3807e | 2012-06-14 09:49:55 +0200 | [diff] [blame] | 2137 | if (likely(cpu < nr_cpu_ids)) { |
Alexander Gordeev | a5a3915 | 2012-06-14 09:49:35 +0200 | [diff] [blame] | 2138 | *apicid = per_cpu(x86_cpu_to_apicid, cpu); |
| 2139 | return 0; |
Alexander Gordeev | a5a3915 | 2012-06-14 09:49:35 +0200 | [diff] [blame] | 2140 | } |
Alexander Gordeev | ea3807e | 2012-06-14 09:49:55 +0200 | [diff] [blame] | 2141 | |
| 2142 | return -EINVAL; |
Alexander Gordeev | 6398268 | 2012-06-05 13:23:44 +0200 | [diff] [blame] | 2143 | } |
| 2144 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2145 | /* |
Michael S. Tsirkin | 1551df6 | 2012-07-15 15:56:46 +0300 | [diff] [blame] | 2146 | * Override the generic EOI implementation with an optimized version. |
| 2147 | * Only called during early boot when only one CPU is active and with |
| 2148 | * interrupts disabled, so we know this does not race with actual APIC driver |
| 2149 | * use. |
| 2150 | */ |
| 2151 | void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) |
| 2152 | { |
| 2153 | struct apic **drv; |
| 2154 | |
| 2155 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { |
| 2156 | /* Should happen once for each apic */ |
| 2157 | WARN_ON((*drv)->eoi_write == eoi_write); |
| 2158 | (*drv)->eoi_write = eoi_write; |
| 2159 | } |
| 2160 | } |
| 2161 | |
| 2162 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2163 | * Power management |
| 2164 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2165 | #ifdef CONFIG_PM |
| 2166 | |
| 2167 | static struct { |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 2168 | /* |
| 2169 | * 'active' is true if the local APIC was enabled by us and |
| 2170 | * not the BIOS; this signifies that we are also responsible |
| 2171 | * for disabling it before entering apm/acpi suspend |
| 2172 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2173 | int active; |
| 2174 | /* r/w apic fields */ |
| 2175 | unsigned int apic_id; |
| 2176 | unsigned int apic_taskpri; |
| 2177 | unsigned int apic_ldr; |
| 2178 | unsigned int apic_dfr; |
| 2179 | unsigned int apic_spiv; |
| 2180 | unsigned int apic_lvtt; |
| 2181 | unsigned int apic_lvtpc; |
| 2182 | unsigned int apic_lvt0; |
| 2183 | unsigned int apic_lvt1; |
| 2184 | unsigned int apic_lvterr; |
| 2185 | unsigned int apic_tmict; |
| 2186 | unsigned int apic_tdcr; |
| 2187 | unsigned int apic_thmr; |
| 2188 | } apic_pm_state; |
| 2189 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2190 | static int lapic_suspend(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2191 | { |
| 2192 | unsigned long flags; |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2193 | int maxlvt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2194 | |
| 2195 | if (!apic_pm_state.active) |
| 2196 | return 0; |
| 2197 | |
Thomas Gleixner | 37e650c | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 2198 | maxlvt = lapic_get_maxlvt(); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2199 | |
Suresh Siddha | 2d7a66d | 2008-07-11 14:24:19 -0700 | [diff] [blame] | 2200 | apic_pm_state.apic_id = apic_read(APIC_ID); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2201 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
| 2202 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); |
| 2203 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); |
| 2204 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); |
| 2205 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2206 | if (maxlvt >= 4) |
| 2207 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2208 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); |
| 2209 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); |
| 2210 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); |
| 2211 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); |
| 2212 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 2213 | #ifdef CONFIG_X86_THERMAL_VECTOR |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2214 | if (maxlvt >= 5) |
| 2215 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); |
| 2216 | #endif |
Cyrill Gorcunov | 24968cf | 2008-08-16 23:21:52 +0400 | [diff] [blame] | 2217 | |
Fernando Luis Vázquez Cao | 2b94ab2 | 2006-09-26 10:52:33 +0200 | [diff] [blame] | 2218 | local_irq_save(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2219 | disable_local_APIC(); |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 2220 | |
Suresh Siddha | 95a02e9 | 2012-03-30 11:47:07 -0700 | [diff] [blame] | 2221 | if (irq_remapping_enabled) |
| 2222 | irq_remapping_disable(); |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 2223 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2224 | local_irq_restore(flags); |
| 2225 | return 0; |
| 2226 | } |
| 2227 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2228 | static void lapic_resume(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2229 | { |
| 2230 | unsigned int l, h; |
| 2231 | unsigned long flags; |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 2232 | int maxlvt; |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2233 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2234 | if (!apic_pm_state.active) |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2235 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2236 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2237 | local_irq_save(flags); |
Suresh Siddha | 95a02e9 | 2012-03-30 11:47:07 -0700 | [diff] [blame] | 2238 | if (irq_remapping_enabled) { |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 2239 | /* |
| 2240 | * IO-APIC and PIC have their own resume routines. |
| 2241 | * We just mask them here to make sure the interrupt |
| 2242 | * subsystem is completely quiet while we enable x2apic |
| 2243 | * and interrupt-remapping. |
| 2244 | */ |
| 2245 | mask_ioapic_entries(); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 2246 | legacy_pic->mask_all(); |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2247 | } |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2248 | |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 2249 | if (x2apic_mode) |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2250 | enable_x2apic(); |
Suresh Siddha | cf6567f | 2009-03-16 17:05:00 -0700 | [diff] [blame] | 2251 | else { |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2252 | /* |
| 2253 | * Make sure the APICBASE points to the right address |
| 2254 | * |
| 2255 | * FIXME! This will be wrong if we ever support suspend on |
| 2256 | * SMP! We'll need to do this as part of the CPU restore! |
| 2257 | */ |
Bryan O'Donoghue | cbf2829 | 2012-04-18 17:37:39 +0100 | [diff] [blame] | 2258 | if (boot_cpu_data.x86 >= 6) { |
| 2259 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 2260 | l &= ~MSR_IA32_APICBASE_BASE; |
| 2261 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; |
| 2262 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 2263 | } |
Yinghai Lu | d5e629a | 2008-08-17 21:12:27 -0700 | [diff] [blame] | 2264 | } |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 2265 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2266 | maxlvt = lapic_get_maxlvt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2267 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
| 2268 | apic_write(APIC_ID, apic_pm_state.apic_id); |
| 2269 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); |
| 2270 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); |
| 2271 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); |
| 2272 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); |
| 2273 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); |
| 2274 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2275 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2276 | if (maxlvt >= 5) |
| 2277 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); |
| 2278 | #endif |
| 2279 | if (maxlvt >= 4) |
| 2280 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2281 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); |
| 2282 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); |
| 2283 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); |
| 2284 | apic_write(APIC_ESR, 0); |
| 2285 | apic_read(APIC_ESR); |
| 2286 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); |
| 2287 | apic_write(APIC_ESR, 0); |
| 2288 | apic_read(APIC_ESR); |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2289 | |
Suresh Siddha | 95a02e9 | 2012-03-30 11:47:07 -0700 | [diff] [blame] | 2290 | if (irq_remapping_enabled) |
| 2291 | irq_remapping_reenable(x2apic_mode); |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 2292 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2293 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2294 | } |
| 2295 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 2296 | /* |
| 2297 | * This device has no shutdown method - fully functioning local APICs |
| 2298 | * are needed on every CPU up until machine_halt/restart/poweroff. |
| 2299 | */ |
| 2300 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2301 | static struct syscore_ops lapic_syscore_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2302 | .resume = lapic_resume, |
| 2303 | .suspend = lapic_suspend, |
| 2304 | }; |
| 2305 | |
Ashok Raj | e6982c6 | 2005-06-25 14:54:58 -0700 | [diff] [blame] | 2306 | static void __cpuinit apic_pm_activate(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2307 | { |
| 2308 | apic_pm_state.active = 1; |
| 2309 | } |
| 2310 | |
| 2311 | static int __init init_lapic_sysfs(void) |
| 2312 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2313 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2314 | if (cpu_has_apic) |
| 2315 | register_syscore_ops(&lapic_syscore_ops); |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 2316 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2317 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2318 | } |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2319 | |
| 2320 | /* local apic needs to resume before other devices access its registers. */ |
| 2321 | core_initcall(init_lapic_sysfs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2322 | |
| 2323 | #else /* CONFIG_PM */ |
| 2324 | |
| 2325 | static void apic_pm_activate(void) { } |
| 2326 | |
| 2327 | #endif /* CONFIG_PM */ |
| 2328 | |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 2329 | #ifdef CONFIG_X86_64 |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2330 | |
| 2331 | static int __cpuinit apic_cluster_num(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2332 | { |
| 2333 | int i, clusters, zeros; |
| 2334 | unsigned id; |
Yinghai Lu | 322850a | 2008-02-23 21:48:42 -0800 | [diff] [blame] | 2335 | u16 *bios_cpu_apicid; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2336 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
| 2337 | |
Mike Travis | 23ca4bb | 2008-05-12 21:21:12 +0200 | [diff] [blame] | 2338 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
Suresh Siddha | 376ec33f | 2005-05-16 21:53:32 -0700 | [diff] [blame] | 2339 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2340 | |
Mike Travis | 168ef54 | 2008-12-16 17:34:01 -0800 | [diff] [blame] | 2341 | for (i = 0; i < nr_cpu_ids; i++) { |
travis@sgi.com | e8c10ef | 2008-01-30 13:33:12 +0100 | [diff] [blame] | 2342 | /* are we being called early in kernel startup? */ |
Mike Travis | 693e3c5 | 2008-01-30 13:33:14 +0100 | [diff] [blame] | 2343 | if (bios_cpu_apicid) { |
| 2344 | id = bios_cpu_apicid[i]; |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 2345 | } else if (i < nr_cpu_ids) { |
travis@sgi.com | e8c10ef | 2008-01-30 13:33:12 +0100 | [diff] [blame] | 2346 | if (cpu_present(i)) |
| 2347 | id = per_cpu(x86_bios_cpu_apicid, i); |
| 2348 | else |
| 2349 | continue; |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 2350 | } else |
travis@sgi.com | e8c10ef | 2008-01-30 13:33:12 +0100 | [diff] [blame] | 2351 | break; |
| 2352 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2353 | if (id != BAD_APICID) |
| 2354 | __set_bit(APIC_CLUSTERID(id), clustermap); |
| 2355 | } |
| 2356 | |
| 2357 | /* Problem: Partially populated chassis may not have CPUs in some of |
| 2358 | * the APIC clusters they have been allocated. Only present CPUs have |
travis@sgi.com | 602a54a | 2008-01-30 13:33:21 +0100 | [diff] [blame] | 2359 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
| 2360 | * Since clusters are allocated sequentially, count zeros only if |
| 2361 | * they are bounded by ones. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2362 | */ |
| 2363 | clusters = 0; |
| 2364 | zeros = 0; |
| 2365 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { |
| 2366 | if (test_bit(i, clustermap)) { |
| 2367 | clusters += 1 + zeros; |
| 2368 | zeros = 0; |
| 2369 | } else |
| 2370 | ++zeros; |
| 2371 | } |
| 2372 | |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2373 | return clusters; |
| 2374 | } |
| 2375 | |
| 2376 | static int __cpuinitdata multi_checked; |
| 2377 | static int __cpuinitdata multi; |
| 2378 | |
| 2379 | static int __cpuinit set_multi(const struct dmi_system_id *d) |
| 2380 | { |
| 2381 | if (multi) |
| 2382 | return 0; |
Cyrill Gorcunov | 6f0aced | 2009-05-01 23:54:25 +0400 | [diff] [blame] | 2383 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2384 | multi = 1; |
| 2385 | return 0; |
| 2386 | } |
| 2387 | |
| 2388 | static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { |
| 2389 | { |
| 2390 | .callback = set_multi, |
| 2391 | .ident = "IBM System Summit2", |
| 2392 | .matches = { |
| 2393 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), |
| 2394 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), |
| 2395 | }, |
| 2396 | }, |
| 2397 | {} |
| 2398 | }; |
| 2399 | |
| 2400 | static void __cpuinit dmi_check_multi(void) |
| 2401 | { |
| 2402 | if (multi_checked) |
| 2403 | return; |
| 2404 | |
| 2405 | dmi_check_system(multi_dmi_table); |
| 2406 | multi_checked = 1; |
| 2407 | } |
| 2408 | |
| 2409 | /* |
| 2410 | * apic_is_clustered_box() -- Check if we can expect good TSC |
| 2411 | * |
| 2412 | * Thus far, the major user of this is IBM's Summit2 series: |
| 2413 | * Clustered boxes may have unsynced TSC problems if they are |
| 2414 | * multi-chassis. |
| 2415 | * Use DMI to check them |
| 2416 | */ |
| 2417 | __cpuinit int apic_is_clustered_box(void) |
| 2418 | { |
| 2419 | dmi_check_multi(); |
| 2420 | if (multi) |
Ravikiran G Thirumalai | 1cb6848 | 2008-03-20 00:45:08 -0700 | [diff] [blame] | 2421 | return 1; |
| 2422 | |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2423 | if (!is_vsmp_box()) |
| 2424 | return 0; |
| 2425 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2426 | /* |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2427 | * ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
| 2428 | * not guaranteed to be synced between boards |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2429 | */ |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2430 | if (apic_cluster_num() > 1) |
| 2431 | return 1; |
| 2432 | |
| 2433 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2434 | } |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 2435 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2436 | |
| 2437 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2438 | * APIC command line parameters |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2439 | */ |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2440 | static int __init setup_disableapic(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2441 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2442 | disable_apic = 1; |
Yinghai Lu | 9175fc0 | 2008-07-21 01:38:14 -0700 | [diff] [blame] | 2443 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2444 | return 0; |
| 2445 | } |
| 2446 | early_param("disableapic", setup_disableapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2447 | |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2448 | /* same as disableapic, for compatibility */ |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2449 | static int __init setup_nolapic(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2450 | { |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2451 | return setup_disableapic(arg); |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2452 | } |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2453 | early_param("nolapic", setup_nolapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2454 | |
Linus Torvalds | 2e7c283 | 2007-03-23 11:32:31 -0700 | [diff] [blame] | 2455 | static int __init parse_lapic_timer_c2_ok(char *arg) |
| 2456 | { |
| 2457 | local_apic_timer_c2_ok = 1; |
| 2458 | return 0; |
| 2459 | } |
| 2460 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); |
| 2461 | |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2462 | static int __init parse_disable_apic_timer(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2463 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2464 | disable_apic_timer = 1; |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2465 | return 0; |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2466 | } |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2467 | early_param("noapictimer", parse_disable_apic_timer); |
| 2468 | |
| 2469 | static int __init parse_nolapic_timer(char *arg) |
| 2470 | { |
| 2471 | disable_apic_timer = 1; |
| 2472 | return 0; |
| 2473 | } |
| 2474 | early_param("nolapic_timer", parse_nolapic_timer); |
Andi Kleen | 73dea47 | 2006-02-03 21:50:50 +0100 | [diff] [blame] | 2475 | |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2476 | static int __init apic_set_verbosity(char *arg) |
| 2477 | { |
| 2478 | if (!arg) { |
| 2479 | #ifdef CONFIG_X86_64 |
| 2480 | skip_ioapic_setup = 0; |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2481 | return 0; |
| 2482 | #endif |
| 2483 | return -EINVAL; |
| 2484 | } |
| 2485 | |
| 2486 | if (strcmp("debug", arg) == 0) |
| 2487 | apic_verbosity = APIC_DEBUG; |
| 2488 | else if (strcmp("verbose", arg) == 0) |
| 2489 | apic_verbosity = APIC_VERBOSE; |
| 2490 | else { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 2491 | pr_warning("APIC Verbosity level %s not recognised" |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2492 | " use apic=verbose or apic=debug\n", arg); |
| 2493 | return -EINVAL; |
| 2494 | } |
| 2495 | |
| 2496 | return 0; |
| 2497 | } |
| 2498 | early_param("apic", apic_set_verbosity); |
| 2499 | |
Yinghai Lu | 1e934dd | 2008-02-22 13:37:26 -0800 | [diff] [blame] | 2500 | static int __init lapic_insert_resource(void) |
| 2501 | { |
| 2502 | if (!apic_phys) |
| 2503 | return -1; |
| 2504 | |
| 2505 | /* Put local APIC into the resource map. */ |
| 2506 | lapic_resource.start = apic_phys; |
| 2507 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; |
| 2508 | insert_resource(&iomem_resource, &lapic_resource); |
| 2509 | |
| 2510 | return 0; |
| 2511 | } |
| 2512 | |
| 2513 | /* |
| 2514 | * need call insert after e820_reserve_resources() |
| 2515 | * that is using request_resource |
| 2516 | */ |
| 2517 | late_initcall(lapic_insert_resource); |