blob: b17416e72fbdc461e7f5d3207ed6b6d459e7c145 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Local APIC handling, local APIC timers
3 *
Ingo Molnar8f47e162009-01-31 02:03:42 +01004 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
Ingo Molnarcdd6c482009-09-21 12:02:48 +020017#include <linux/perf_event.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/kernel_stat.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010019#include <linux/mc146818rtc.h>
Thomas Gleixner70a20022008-01-30 13:30:18 +010020#include <linux/acpi_pmtmr.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010021#include <linux/clockchips.h>
22#include <linux/interrupt.h>
23#include <linux/bootmem.h>
Frederic Weisbeckerbcbc4f22008-12-09 23:54:20 +010024#include <linux/ftrace.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010025#include <linux/ioport.h>
26#include <linux/module.h>
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +010027#include <linux/syscore_ops.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010028#include <linux/delay.h>
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +053029#include <linux/timex.h>
Ralf Baechle334955e2011-06-01 19:04:57 +010030#include <linux/i8253.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010031#include <linux/dmar.h>
32#include <linux/init.h>
33#include <linux/cpu.h>
34#include <linux/dmi.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010035#include <linux/smp.h>
36#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Suresh Siddha8a8f4222012-03-30 11:47:08 -070038#include <asm/irq_remapping.h>
Ingo Molnarcdd6c482009-09-21 12:02:48 +020039#include <asm/perf_event.h>
Thomas Gleixner736deca2009-08-19 12:35:53 +020040#include <asm/x86_init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#include <asm/pgalloc.h>
Arun Sharma600634972011-07-26 16:09:06 -070042#include <linux/atomic.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010043#include <asm/mpspec.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010044#include <asm/i8259.h>
Andi Kleen73dea472006-02-03 21:50:50 +010045#include <asm/proto.h>
Andi Kleen2c8c0e62006-09-26 10:52:32 +020046#include <asm/apic.h>
Henrik Kretzschmar7167d082011-02-22 15:38:05 +010047#include <asm/io_apic.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010048#include <asm/desc.h>
49#include <asm/hpet.h>
50#include <asm/idle.h>
51#include <asm/mtrr.h>
Ralf Baechle16f871b2011-06-01 19:05:06 +010052#include <asm/time.h>
Jaswinder Singh Rajput2bc13792009-01-11 20:34:47 +053053#include <asm/smp.h>
Andi Kleenbe71b852009-02-12 13:49:38 +010054#include <asm/mce.h>
Kerstin Jonsson8c3ba8d2010-05-24 12:13:15 -070055#include <asm/tsc.h>
Sheng Yang2904ed82010-12-21 14:18:48 +080056#include <asm/hypervisor.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070057
Brian Gerstec70de82009-01-27 12:56:47 +090058unsigned int num_processors;
Ingo Molnarfdbecd92009-01-31 03:57:12 +010059
Brian Gerstec70de82009-01-27 12:56:47 +090060unsigned disabled_cpus __cpuinitdata;
Ingo Molnarfdbecd92009-01-31 03:57:12 +010061
Brian Gerstec70de82009-01-27 12:56:47 +090062/* Processor that is doing the boot up */
63unsigned int boot_cpu_physical_apicid = -1U;
Glauber Costa5af55732008-03-25 13:28:56 -030064
Cyrill Gorcunov80e56092008-08-24 02:01:42 -070065/*
Ingo Molnarfdbecd92009-01-31 03:57:12 +010066 * The highest APIC ID seen during enumeration.
Cyrill Gorcunov80e56092008-08-24 02:01:42 -070067 */
Brian Gerstec70de82009-01-27 12:56:47 +090068unsigned int max_physical_apicid;
69
Ingo Molnarfdbecd92009-01-31 03:57:12 +010070/*
71 * Bitmask of physically existing CPUs:
72 */
Brian Gerstec70de82009-01-27 12:56:47 +090073physid_mask_t phys_cpu_present_map;
74
75/*
76 * Map cpu index to physical APIC ID
77 */
Vlad Zolotarov0816b0f2012-06-11 12:56:52 +030078DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
79DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
Brian Gerstec70de82009-01-27 12:56:47 +090080EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
81EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
Cyrill Gorcunov80e56092008-08-24 02:01:42 -070082
Yinghai Lub3c51172008-08-24 02:01:46 -070083#ifdef CONFIG_X86_32
Tejun Heo4c321ff2011-01-23 14:37:30 +010084
Tejun Heo4c321ff2011-01-23 14:37:30 +010085/*
86 * On x86_32, the mapping between cpu and logical apicid may vary
87 * depending on apic in use. The following early percpu variable is
88 * used for the mapping. This is where the behaviors of x86_64 and 32
89 * actually diverge. Let's keep it ugly for now.
90 */
Vlad Zolotarov0816b0f2012-06-11 12:56:52 +030091DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
Tejun Heo4c321ff2011-01-23 14:37:30 +010092
Yinghai Lub3c51172008-08-24 02:01:46 -070093/*
94 * Knob to control our willingness to enable the local APIC.
95 *
96 * +1=force-enable
97 */
Henrik Kretzschmar25874a22011-03-11 08:02:36 +010098static int force_enable_local_apic __initdata;
Yinghai Lub3c51172008-08-24 02:01:46 -070099/*
100 * APIC command line parameters
101 */
102static int __init parse_lapic(char *arg)
103{
104 force_enable_local_apic = 1;
105 return 0;
106}
107early_param("lapic", parse_lapic);
Yinghai Luf28c0ae2008-08-24 02:01:49 -0700108/* Local APIC was disabled by the BIOS and enabled by the kernel */
109static int enabled_via_apicbase;
110
Cyrill Gorcunovc0eaa452009-04-12 20:47:40 +0400111/*
112 * Handle interrupt mode configuration register (IMCR).
113 * This register controls whether the interrupt signals
114 * that reach the BSP come from the master PIC or from the
115 * local APIC. Before entering Symmetric I/O Mode, either
116 * the BIOS or the operating system must switch out of
117 * PIC Mode by changing the IMCR.
118 */
Alexander van Heukelum5cda3952009-04-13 17:39:24 +0200119static inline void imcr_pic_to_apic(void)
Cyrill Gorcunovc0eaa452009-04-12 20:47:40 +0400120{
121 /* select IMCR register */
122 outb(0x70, 0x22);
123 /* NMI and 8259 INTR go through APIC */
124 outb(0x01, 0x23);
125}
126
Alexander van Heukelum5cda3952009-04-13 17:39:24 +0200127static inline void imcr_apic_to_pic(void)
Cyrill Gorcunovc0eaa452009-04-12 20:47:40 +0400128{
129 /* select IMCR register */
130 outb(0x70, 0x22);
131 /* NMI and 8259 INTR go directly to BSP */
132 outb(0x00, 0x23);
133}
Yinghai Lub3c51172008-08-24 02:01:46 -0700134#endif
135
136#ifdef CONFIG_X86_64
Chris Wrightbc1d99c2007-10-12 23:04:23 +0200137static int apic_calibrate_pmtmr __initdata;
Yinghai Lub3c51172008-08-24 02:01:46 -0700138static __init int setup_apicpmtimer(char *s)
139{
140 apic_calibrate_pmtmr = 1;
141 notsc_setup(NULL);
142 return 0;
143}
144__setup("apicpmtimer", setup_apicpmtimer);
145#endif
146
Suresh Siddhafc1edaf2009-04-20 13:02:27 -0700147int x2apic_mode;
Yinghai Lu06cd9a72009-02-16 17:29:58 -0800148#ifdef CONFIG_X86_X2APIC
Suresh Siddha6e1cb382008-07-10 11:16:58 -0700149/* x2apic enabled before OS handover */
Yinghai Lufb209bd2011-12-21 17:45:17 -0800150int x2apic_preenabled;
151static int x2apic_disabled;
Yinghai Lua31bc322011-12-23 11:01:43 -0800152static int nox2apic;
Yinghai Lu49899ea2008-08-24 02:01:47 -0700153static __init int setup_nox2apic(char *str)
154{
Suresh Siddha39d83a52009-04-20 13:02:29 -0700155 if (x2apic_enabled()) {
Yinghai Lua31bc322011-12-23 11:01:43 -0800156 int apicid = native_apic_msr_read(APIC_ID);
Suresh Siddha39d83a52009-04-20 13:02:29 -0700157
Yinghai Lua31bc322011-12-23 11:01:43 -0800158 if (apicid >= 255) {
159 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
160 apicid);
161 return 0;
162 }
163
164 pr_warning("x2apic already enabled. will disable it\n");
165 } else
166 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
167
168 nox2apic = 1;
169
Yinghai Lu49899ea2008-08-24 02:01:47 -0700170 return 0;
171}
172early_param("nox2apic", setup_nox2apic);
173#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174
Yinghai Lub3c51172008-08-24 02:01:46 -0700175unsigned long mp_lapic_addr;
176int disable_apic;
177/* Disable local APIC timer from the kernel commandline or via dmi quirk */
Henrik Kretzschmar25874a22011-03-11 08:02:36 +0100178static int disable_apic_timer __initdata;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100179/* Local APIC timer works in C2 */
Linus Torvalds2e7c2832007-03-23 11:32:31 -0700180int local_apic_timer_c2_ok;
181EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
182
Yinghai Luefa25592008-08-19 20:50:36 -0700183int first_system_vector = 0xfe;
184
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100185/*
186 * Debug level, exported for io_apic.c
187 */
Maciej W. Rozyckibaa13182008-07-14 18:44:51 +0100188unsigned int apic_verbosity;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100189
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -0700190int pic_mode;
191
Alexey Starikovskiybab4b272008-05-19 19:47:03 +0400192/* Have we found an MP table */
193int smp_found_config;
194
Aaron Durbin39928722006-12-07 02:14:01 +0100195static struct resource lapic_resource = {
196 .name = "Local APIC",
197 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
198};
199
Jacob Pan1ade93e2011-11-10 13:42:40 +0000200unsigned int lapic_timer_frequency = 0;
Thomas Gleixnerd03030e2007-10-12 23:04:06 +0200201
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100202static void apic_pm_activate(void);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200203
Andi Kleend3432892008-01-30 13:33:17 +0100204static unsigned long apic_phys;
205
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100206/*
207 * Get the LAPIC version
208 */
209static inline int lapic_get_version(void)
210{
211 return GET_APIC_VERSION(apic_read(APIC_LVR));
212}
213
214/*
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400215 * Check, if the APIC is integrated or a separate chip
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100216 */
217static inline int lapic_is_integrated(void)
218{
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400219#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100220 return 1;
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400221#else
222 return APIC_INTEGRATED(lapic_get_version());
223#endif
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100224}
225
226/*
227 * Check, whether this is a modern or a first generation APIC
228 */
229static int modern_apic(void)
230{
231 /* AMD systems use old APIC versions, so check the CPU */
232 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
233 boot_cpu_data.x86 >= 0xf)
234 return 1;
235 return lapic_get_version() >= 0x14;
236}
237
Cyrill Gorcunov08306ce2009-04-12 20:47:41 +0400238/*
Cyrill Gorcunova933c612009-10-14 00:07:04 +0400239 * right after this call apic become NOOP driven
240 * so apic->write/read doesn't do anything
Cyrill Gorcunov08306ce2009-04-12 20:47:41 +0400241 */
Henrik Kretzschmar25874a22011-03-11 08:02:36 +0100242static void __init apic_disable(void)
Cyrill Gorcunov08306ce2009-04-12 20:47:41 +0400243{
Cyrill Gorcunovf88f2b42009-10-15 19:04:16 +0400244 pr_info("APIC: switched to apic NOOP\n");
Cyrill Gorcunova933c612009-10-14 00:07:04 +0400245 apic = &apic_noop;
Cyrill Gorcunov08306ce2009-04-12 20:47:41 +0400246}
247
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800248void native_apic_wait_icr_idle(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100249{
250 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
251 cpu_relax();
252}
253
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800254u32 native_safe_apic_wait_icr_idle(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100255{
256 u32 send_status;
257 int timeout;
258
259 timeout = 0;
260 do {
261 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
262 if (!send_status)
263 break;
Fernando Luis Vazquez Caob49d7d82011-12-15 11:32:24 +0900264 inc_irq_stat(icr_read_retry_count);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100265 udelay(100);
266 } while (timeout++ < 1000);
267
268 return send_status;
269}
270
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800271void native_apic_icr_write(u32 low, u32 id)
Suresh Siddha1b374e42008-07-10 11:16:49 -0700272{
Cyrill Gorcunoved4e5ec2008-08-15 13:51:20 +0200273 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
Suresh Siddha1b374e42008-07-10 11:16:49 -0700274 apic_write(APIC_ICR, low);
275}
276
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800277u64 native_apic_icr_read(void)
Suresh Siddha1b374e42008-07-10 11:16:49 -0700278{
279 u32 icr1, icr2;
280
281 icr2 = apic_read(APIC_ICR2);
282 icr1 = apic_read(APIC_ICR);
283
Cyrill Gorcunovcf9768d72008-08-16 23:21:55 +0400284 return icr1 | ((u64)icr2 << 32);
Suresh Siddha1b374e42008-07-10 11:16:49 -0700285}
286
Cyrill Gorcunov7c37e482008-08-24 02:01:40 -0700287#ifdef CONFIG_X86_32
288/**
289 * get_physical_broadcast - Get number of physical broadcast IDs
290 */
291int get_physical_broadcast(void)
292{
293 return modern_apic() ? 0xff : 0xf;
294}
295#endif
296
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100297/**
298 * lapic_get_maxlvt - get the maximum number of local vector table entries
299 */
300int lapic_get_maxlvt(void)
301{
Cyrill Gorcunov36a028d2008-07-24 13:52:28 +0200302 unsigned int v;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100303
304 v = apic_read(APIC_LVR);
Cyrill Gorcunov36a028d2008-07-24 13:52:28 +0200305 /*
306 * - we always have APIC integrated on 64bit mode
307 * - 82489DXs do not report # of LVT entries
308 */
309 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100310}
311
312/*
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400313 * Local APIC timer
314 */
315
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400316/* Clock divisor */
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400317#define APIC_DIVISOR 16
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200318
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100319/*
320 * This function sets up the local APIC timer, with a timeout of
321 * 'clocks' APIC bus clock. During calibration we actually call
322 * this function twice on the boot CPU, once with a bogus timeout
323 * value, second time for real. The other (noncalibrating) CPUs
324 * call this function only once, with the real, calibrated value.
325 *
326 * We do reads before writes even if unnecessary, to get around the
327 * P5 APIC double write bug.
328 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100329static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
330{
331 unsigned int lvtt_value, tmp_value;
332
333 lvtt_value = LOCAL_TIMER_VECTOR;
334 if (!oneshot)
335 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200336 if (!lapic_is_integrated())
337 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
338
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100339 if (!irqen)
340 lvtt_value |= APIC_LVT_MASKED;
341
342 apic_write(APIC_LVTT, lvtt_value);
343
344 /*
345 * Divide PICLK by 16
346 */
347 tmp_value = apic_read(APIC_TDCR);
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400348 apic_write(APIC_TDCR,
349 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
350 APIC_TDR_DIV_16);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100351
352 if (!oneshot)
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200353 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100354}
355
356/*
Robert Richtera68c4392010-10-06 12:27:53 +0200357 * Setup extended LVT, AMD specific
Robert Richter7b83dae2008-01-30 13:30:40 +0100358 *
Robert Richtera68c4392010-10-06 12:27:53 +0200359 * Software should use the LVT offsets the BIOS provides. The offsets
360 * are determined by the subsystems using it like those for MCE
361 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
362 * are supported. Beginning with family 10h at least 4 offsets are
363 * available.
Robert Richter286f5712008-07-22 21:08:46 +0200364 *
Robert Richtera68c4392010-10-06 12:27:53 +0200365 * Since the offsets must be consistent for all cores, we keep track
366 * of the LVT offsets in software and reserve the offset for the same
367 * vector also to be used on other cores. An offset is freed by
368 * setting the entry to APIC_EILVT_MASKED.
369 *
370 * If the BIOS is right, there should be no conflicts. Otherwise a
371 * "[Firmware Bug]: ..." error message is generated. However, if
372 * software does not properly determines the offsets, it is not
373 * necessarily a BIOS bug.
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100374 */
Robert Richter7b83dae2008-01-30 13:30:40 +0100375
Robert Richtera68c4392010-10-06 12:27:53 +0200376static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100377
Robert Richtera68c4392010-10-06 12:27:53 +0200378static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
379{
380 return (old & APIC_EILVT_MASKED)
381 || (new == APIC_EILVT_MASKED)
382 || ((new & ~APIC_EILVT_MASKED) == old);
383}
384
385static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
386{
Robert Richter8abc3122012-03-27 20:04:02 +0200387 unsigned int rsvd, vector;
Robert Richtera68c4392010-10-06 12:27:53 +0200388
389 if (offset >= APIC_EILVT_NR_MAX)
390 return ~0;
391
Robert Richter8abc3122012-03-27 20:04:02 +0200392 rsvd = atomic_read(&eilvt_offsets[offset]);
Robert Richtera68c4392010-10-06 12:27:53 +0200393 do {
Robert Richter8abc3122012-03-27 20:04:02 +0200394 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
395 if (vector && !eilvt_entry_is_changeable(vector, new))
Robert Richtera68c4392010-10-06 12:27:53 +0200396 /* may not change if vectors are different */
397 return rsvd;
398 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
399 } while (rsvd != new);
400
Robert Richter8abc3122012-03-27 20:04:02 +0200401 rsvd &= ~APIC_EILVT_MASKED;
402 if (rsvd && rsvd != vector)
403 pr_info("LVT offset %d assigned for vector 0x%02x\n",
404 offset, rsvd);
405
Robert Richtera68c4392010-10-06 12:27:53 +0200406 return new;
407}
408
409/*
410 * If mask=1, the LVT entry does not generate interrupts while mask=0
Robert Richtercbf74ce2011-05-30 16:31:11 +0200411 * enables the vector. See also the BKDGs. Must be called with
412 * preemption disabled.
Robert Richtera68c4392010-10-06 12:27:53 +0200413 */
414
Robert Richter27afdf22010-10-06 12:27:54 +0200415int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
Robert Richtera68c4392010-10-06 12:27:53 +0200416{
417 unsigned long reg = APIC_EILVTn(offset);
418 unsigned int new, old, reserved;
419
420 new = (mask << 16) | (msg_type << 8) | vector;
421 old = apic_read(reg);
422 reserved = reserve_eilvt_offset(offset, new);
423
424 if (reserved != new) {
Robert Richtereb48c9c2010-10-25 16:03:39 +0200425 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
426 "vector 0x%x, but the register is already in use for "
427 "vector 0x%x on another cpu\n",
428 smp_processor_id(), reg, offset, new, reserved);
Robert Richtera68c4392010-10-06 12:27:53 +0200429 return -EINVAL;
430 }
431
432 if (!eilvt_entry_is_changeable(old, new)) {
Robert Richtereb48c9c2010-10-25 16:03:39 +0200433 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
434 "vector 0x%x, but the register is already in use for "
435 "vector 0x%x on this cpu\n",
436 smp_processor_id(), reg, offset, new, old);
Robert Richtera68c4392010-10-06 12:27:53 +0200437 return -EBUSY;
438 }
439
440 apic_write(reg, new);
441
442 return 0;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100443}
Robert Richter27afdf22010-10-06 12:27:54 +0200444EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
Robert Richter7b83dae2008-01-30 13:30:40 +0100445
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100446/*
447 * Program the next event, relative to now
448 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200449static int lapic_next_event(unsigned long delta,
450 struct clock_event_device *evt)
451{
452 apic_write(APIC_TMICT, delta);
453 return 0;
454}
455
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100456/*
457 * Setup the lapic timer in periodic or oneshot mode
458 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200459static void lapic_timer_setup(enum clock_event_mode mode,
460 struct clock_event_device *evt)
461{
462 unsigned long flags;
463 unsigned int v;
464
465 /* Lapic used as dummy for broadcast ? */
466 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
467 return;
468
469 local_irq_save(flags);
470
471 switch (mode) {
472 case CLOCK_EVT_MODE_PERIODIC:
473 case CLOCK_EVT_MODE_ONESHOT:
Jacob Pan1ade93e2011-11-10 13:42:40 +0000474 __setup_APIC_LVTT(lapic_timer_frequency,
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200475 mode != CLOCK_EVT_MODE_PERIODIC, 1);
476 break;
477 case CLOCK_EVT_MODE_UNUSED:
478 case CLOCK_EVT_MODE_SHUTDOWN:
479 v = apic_read(APIC_LVTT);
480 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
481 apic_write(APIC_LVTT, v);
Andreas Herrmann6f9b4102009-10-27 11:01:38 +0100482 apic_write(APIC_TMICT, 0);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200483 break;
484 case CLOCK_EVT_MODE_RESUME:
485 /* Nothing to do here */
486 break;
487 }
488
489 local_irq_restore(flags);
490}
491
492/*
493 * Local APIC timer broadcast function
494 */
Mike Travis96289372008-12-31 18:08:46 -0800495static void lapic_timer_broadcast(const struct cpumask *mask)
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200496{
497#ifdef CONFIG_SMP
Ingo Molnardac5f412009-01-28 15:42:24 +0100498 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200499#endif
500}
501
Henrik Kretzschmar25874a22011-03-11 08:02:36 +0100502
503/*
504 * The local apic timer can be used for any function which is CPU local.
505 */
506static struct clock_event_device lapic_clockevent = {
507 .name = "lapic",
508 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
509 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
510 .shift = 32,
511 .set_mode = lapic_timer_setup,
512 .set_next_event = lapic_next_event,
513 .broadcast = lapic_timer_broadcast,
514 .rating = 100,
515 .irq = -1,
516};
517static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
518
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100519/*
Uwe Kleine-König421f91d2010-06-11 12:17:00 +0200520 * Setup the local APIC timer for this CPU. Copy the initialized values
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100521 * of the boot CPU and register the clock event in the framework.
522 */
Cyrill Gorcunovdb4b5522008-08-24 02:01:39 -0700523static void __cpuinit setup_APIC_timer(void)
Fernando Luis VazquezCao8339e9f2007-05-02 19:27:17 +0200524{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100525 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
526
Christoph Lameter349c0042011-03-12 12:50:10 +0100527 if (this_cpu_has(X86_FEATURE_ARAT)) {
Venkatesh Pallipadidb954b52009-04-06 18:51:29 -0700528 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
529 /* Make LAPIC timer preferrable over percpu HPET */
530 lapic_clockevent.rating = 150;
531 }
532
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100533 memcpy(levt, &lapic_clockevent, sizeof(*levt));
Rusty Russell320ab2b2008-12-13 21:20:26 +1030534 levt->cpumask = cpumask_of(smp_processor_id());
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100535
536 clockevents_register_device(levt);
Fernando Luis VazquezCao8339e9f2007-05-02 19:27:17 +0200537}
538
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700539/*
540 * In this functions we calibrate APIC bus clocks to the external timer.
541 *
542 * We want to do the calibration only once since we want to have local timer
543 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
544 * frequency.
545 *
546 * This was previously done by reading the PIT/HPET and waiting for a wrap
547 * around to find out, that a tick has elapsed. I have a box, where the PIT
548 * readout is broken, so it never gets out of the wait loop again. This was
549 * also reported by others.
550 *
551 * Monitoring the jiffies value is inaccurate and the clockevents
552 * infrastructure allows us to do a simple substitution of the interrupt
553 * handler.
554 *
555 * The calibration routine also uses the pm_timer when possible, as the PIT
556 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
557 * back to normal later in the boot process).
558 */
559
560#define LAPIC_CAL_LOOPS (HZ/10)
561
562static __initdata int lapic_cal_loops = -1;
563static __initdata long lapic_cal_t1, lapic_cal_t2;
564static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
565static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
566static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
567
568/*
569 * Temporary interrupt handler.
570 */
571static void __init lapic_cal_handler(struct clock_event_device *dev)
572{
573 unsigned long long tsc = 0;
574 long tapic = apic_read(APIC_TMCCT);
575 unsigned long pm = acpi_pm_read_early();
576
577 if (cpu_has_tsc)
578 rdtscll(tsc);
579
580 switch (lapic_cal_loops++) {
581 case 0:
582 lapic_cal_t1 = tapic;
583 lapic_cal_tsc1 = tsc;
584 lapic_cal_pm1 = pm;
585 lapic_cal_j1 = jiffies;
586 break;
587
588 case LAPIC_CAL_LOOPS:
589 lapic_cal_t2 = tapic;
590 lapic_cal_tsc2 = tsc;
591 if (pm < lapic_cal_pm1)
592 pm += ACPI_PM_OVRRUN;
593 lapic_cal_pm2 = pm;
594 lapic_cal_j2 = jiffies;
595 break;
596 }
597}
598
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900599static int __init
600calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400601{
602 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
603 const long pm_thresh = pm_100ms / 100;
604 unsigned long mult;
605 u64 res;
606
607#ifndef CONFIG_X86_PM_TIMER
608 return -1;
609#endif
610
Yasuaki Ishimatsu39ba5d42009-01-28 12:52:24 +0900611 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400612
613 /* Check, if the PM timer is available */
614 if (!deltapm)
615 return -1;
616
617 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
618
619 if (deltapm > (pm_100ms - pm_thresh) &&
620 deltapm < (pm_100ms + pm_thresh)) {
Yasuaki Ishimatsu39ba5d42009-01-28 12:52:24 +0900621 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900622 return 0;
623 }
624
625 res = (((u64)deltapm) * mult) >> 22;
626 do_div(res, 1000000);
627 pr_warning("APIC calibration not consistent "
Yasuaki Ishimatsu39ba5d42009-01-28 12:52:24 +0900628 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900629
630 /* Correct the lapic counter value */
631 res = (((u64)(*delta)) * pm_100ms);
632 do_div(res, deltapm);
633 pr_info("APIC delta adjusted to PM-Timer: "
634 "%lu (%ld)\n", (unsigned long)res, *delta);
635 *delta = (long)res;
636
637 /* Correct the tsc counter value */
638 if (cpu_has_tsc) {
639 res = (((u64)(*deltatsc)) * pm_100ms);
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400640 do_div(res, deltapm);
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900641 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
Frans Pop3235dc32010-02-06 18:47:17 +0100642 "PM-Timer: %lu (%ld)\n",
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900643 (unsigned long)res, *deltatsc);
644 *deltatsc = (long)res;
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400645 }
646
647 return 0;
648}
649
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700650static int __init calibrate_APIC_clock(void)
651{
652 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700653 void (*real_handler)(struct clock_event_device *dev);
654 unsigned long deltaj;
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900655 long delta, deltatsc;
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700656 int pm_referenced = 0;
657
Jacob Pan1ade93e2011-11-10 13:42:40 +0000658 /**
659 * check if lapic timer has already been calibrated by platform
660 * specific routine, such as tsc calibration code. if so, we just fill
661 * in the clockevent structure and return.
662 */
663
664 if (lapic_timer_frequency) {
665 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
666 lapic_timer_frequency);
667 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
668 TICK_NSEC, lapic_clockevent.shift);
669 lapic_clockevent.max_delta_ns =
670 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
671 lapic_clockevent.min_delta_ns =
672 clockevent_delta2ns(0xF, &lapic_clockevent);
673 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
674 return 0;
675 }
676
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700677 local_irq_disable();
678
679 /* Replace the global interrupt handler */
680 real_handler = global_clock_event->event_handler;
681 global_clock_event->event_handler = lapic_cal_handler;
682
683 /*
Cyrill Gorcunov81608f32008-10-10 19:00:17 +0400684 * Setup the APIC counter to maximum. There is no way the lapic
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700685 * can underflow in the 100ms detection time frame
686 */
Cyrill Gorcunov81608f32008-10-10 19:00:17 +0400687 __setup_APIC_LVTT(0xffffffff, 0, 0);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700688
689 /* Let the interrupts run */
690 local_irq_enable();
691
692 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
693 cpu_relax();
694
695 local_irq_disable();
696
697 /* Restore the real event handler */
698 global_clock_event->event_handler = real_handler;
699
700 /* Build delta t1-t2 as apic timer counts down */
701 delta = lapic_cal_t1 - lapic_cal_t2;
702 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
703
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900704 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
705
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400706 /* we trust the PM based calibration if possible */
707 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900708 &delta, &deltatsc);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700709
710 /* Calculate the scaled math multiplication factor */
711 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
712 lapic_clockevent.shift);
713 lapic_clockevent.max_delta_ns =
Pierre Tardy4aed89d2011-01-06 16:23:29 +0100714 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700715 lapic_clockevent.min_delta_ns =
716 clockevent_delta2ns(0xF, &lapic_clockevent);
717
Jacob Pan1ade93e2011-11-10 13:42:40 +0000718 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700719
720 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
Thomas Gleixner411462f2009-11-16 11:52:39 +0100721 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700722 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
Jacob Pan1ade93e2011-11-10 13:42:40 +0000723 lapic_timer_frequency);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700724
725 if (cpu_has_tsc) {
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700726 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
727 "%ld.%04ld MHz.\n",
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900728 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
729 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700730 }
731
732 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
733 "%u.%04u MHz.\n",
Jacob Pan1ade93e2011-11-10 13:42:40 +0000734 lapic_timer_frequency / (1000000 / HZ),
735 lapic_timer_frequency % (1000000 / HZ));
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700736
737 /*
738 * Do a sanity check on the APIC calibration result
739 */
Jacob Pan1ade93e2011-11-10 13:42:40 +0000740 if (lapic_timer_frequency < (1000000 / HZ)) {
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700741 local_irq_enable();
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100742 pr_warning("APIC frequency too slow, disabling apic timer\n");
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700743 return -1;
744 }
745
746 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
747
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400748 /*
749 * PM timer calibration failed or not turned on
750 * so lets try APIC timer based calibration
751 */
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700752 if (!pm_referenced) {
753 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
754
755 /*
756 * Setup the apic timer manually
757 */
758 levt->event_handler = lapic_cal_handler;
759 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
760 lapic_cal_loops = -1;
761
762 /* Let the interrupts run */
763 local_irq_enable();
764
765 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
766 cpu_relax();
767
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700768 /* Stop the lapic timer */
769 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
770
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700771 /* Jiffies delta */
772 deltaj = lapic_cal_j2 - lapic_cal_j1;
773 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
774
775 /* Check, if the jiffies result is consistent */
776 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
777 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
778 else
779 levt->features |= CLOCK_EVT_FEAT_DUMMY;
780 } else
781 local_irq_enable();
782
783 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +0530784 pr_warning("APIC timer disabled due to verification failure\n");
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700785 return -1;
786 }
787
788 return 0;
789}
790
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100791/*
792 * Setup the boot APIC
793 *
794 * Calibrate and verify the result.
795 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100796void __init setup_boot_APIC_clock(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100798 /*
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400799 * The local apic timer can be disabled via the kernel
800 * commandline or from the CPU detection code. Register the lapic
801 * timer as a dummy clock event source on SMP systems, so the
802 * broadcast mechanism is used. On UP systems simply ignore it.
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100803 */
804 if (disable_apic_timer) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100805 pr_info("Disabling APIC timer\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100806 /* No broadcast on UP ! */
Thomas Gleixner9d099512008-01-30 13:33:04 +0100807 if (num_possible_cpus() > 1) {
808 lapic_clockevent.mult = 1;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100809 setup_APIC_timer();
Thomas Gleixner9d099512008-01-30 13:33:04 +0100810 }
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100811 return;
812 }
Thomas Gleixner6935d1f2007-07-21 17:10:17 +0200813
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400814 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
815 "calibrating APIC timer ...\n");
816
Cyrill Gorcunov89b3b1f42008-07-15 21:02:54 +0400817 if (calibrate_APIC_clock()) {
Thomas Gleixnerc2b84b32008-01-30 13:33:04 +0100818 /* No broadcast on UP ! */
819 if (num_possible_cpus() > 1)
820 setup_APIC_timer();
821 return;
822 }
823
824 /*
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100825 * If nmi_watchdog is set to IO_APIC, we need the
826 * PIT/HPET going. Otherwise register lapic as a dummy
827 * device.
828 */
Don Zickus072b1982010-11-12 11:22:24 -0500829 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100830
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400831 /* Setup the lapic or request the broadcast */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100832 setup_APIC_timer();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833}
834
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100835void __cpuinit setup_secondary_APIC_clock(void)
836{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100837 setup_APIC_timer();
838}
839
840/*
841 * The guts of the apic timer interrupt
842 */
843static void local_apic_timer_interrupt(void)
844{
845 int cpu = smp_processor_id();
846 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
847
848 /*
849 * Normally we should not be here till LAPIC has been initialized but
850 * in some cases like kdump, its possible that there is a pending LAPIC
851 * timer interrupt from previous kernel's context and is delivered in
852 * new kernel the moment interrupts are enabled.
853 *
854 * Interrupts are enabled early and LAPIC is setup much later, hence
855 * its possible that when we get here evt->event_handler is NULL.
856 * Check for event_handler being NULL and discard the interrupt as
857 * spurious.
858 */
859 if (!evt->event_handler) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100860 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100861 /* Switch it off */
862 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
863 return;
864 }
865
866 /*
867 * the NMI deadlock-detector uses this.
868 */
Hiroshi Shimamoto915b0d02008-12-08 19:19:26 -0800869 inc_irq_stat(apic_timer_irqs);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100870
871 evt->event_handler(evt);
872}
873
874/*
875 * Local APIC timer interrupt. This is the most natural way for doing
876 * local interrupts, but local timer interrupts can be emulated by
877 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
878 *
879 * [ if a single-CPU system runs an SMP kernel then we call the local
880 * interrupt as well. Thus we cannot inline the local irq ... ]
881 */
Frederic Weisbeckerbcbc4f22008-12-09 23:54:20 +0100882void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100883{
884 struct pt_regs *old_regs = set_irq_regs(regs);
885
886 /*
887 * NOTE! We'd better ACK the irq immediately,
888 * because timer handling can be slow.
889 */
890 ack_APIC_irq();
891 /*
892 * update_process_times() expects us to have done irq_enter().
893 * Besides, if we don't timer interrupts ignore the global
894 * interrupt lock, which is the WrongThing (tm) to do.
895 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100896 irq_enter();
Frederic Weisbecker98ad1cc2011-10-07 18:22:09 +0200897 exit_idle();
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100898 local_apic_timer_interrupt();
899 irq_exit();
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400900
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100901 set_irq_regs(old_regs);
902}
903
904int setup_profiling_timer(unsigned int multiplier)
905{
906 return -EINVAL;
907}
908
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100909/*
910 * Local APIC start and shutdown
911 */
912
913/**
914 * clear_local_APIC - shutdown the local APIC
915 *
916 * This is called, when a CPU is disabled and before rebooting, so the state of
917 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
918 * leftovers during boot.
919 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920void clear_local_APIC(void)
921{
Chuck Ebbert2584a822008-05-20 18:18:12 -0400922 int maxlvt;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100923 u32 v;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924
Andi Kleend3432892008-01-30 13:33:17 +0100925 /* APIC hasn't been mapped yet */
Suresh Siddhafc1edaf2009-04-20 13:02:27 -0700926 if (!x2apic_mode && !apic_phys)
Andi Kleend3432892008-01-30 13:33:17 +0100927 return;
928
929 maxlvt = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930 /*
Siddha, Suresh B704fc592006-06-26 13:59:53 +0200931 * Masking an LVT entry can trigger a local APIC error
Linus Torvalds1da177e2005-04-16 15:20:36 -0700932 * if the vector is zero. Mask LVTERR first to prevent this.
933 */
934 if (maxlvt >= 3) {
935 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
Andi Kleen11a8e772006-01-11 22:46:51 +0100936 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700937 }
938 /*
939 * Careful: we have to set masks only first to deassert
940 * any level-triggered sources.
941 */
942 v = apic_read(APIC_LVTT);
Andi Kleen11a8e772006-01-11 22:46:51 +0100943 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944 v = apic_read(APIC_LVT0);
Andi Kleen11a8e772006-01-11 22:46:51 +0100945 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946 v = apic_read(APIC_LVT1);
Andi Kleen11a8e772006-01-11 22:46:51 +0100947 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948 if (maxlvt >= 4) {
949 v = apic_read(APIC_LVTPC);
Andi Kleen11a8e772006-01-11 22:46:51 +0100950 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700951 }
952
Cyrill Gorcunov67640142008-08-16 23:21:50 +0400953 /* lets not touch this if we didn't frob it */
Andi Kleen4efc0672009-04-28 19:07:31 +0200954#ifdef CONFIG_X86_THERMAL_VECTOR
Cyrill Gorcunov67640142008-08-16 23:21:50 +0400955 if (maxlvt >= 5) {
956 v = apic_read(APIC_LVTTHMR);
957 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
958 }
959#endif
Andi Kleen5ca86812009-02-12 13:49:37 +0100960#ifdef CONFIG_X86_MCE_INTEL
961 if (maxlvt >= 6) {
962 v = apic_read(APIC_LVTCMCI);
963 if (!(v & APIC_LVT_MASKED))
964 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
965 }
966#endif
967
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968 /*
969 * Clean APIC state for other OSs:
970 */
Andi Kleen11a8e772006-01-11 22:46:51 +0100971 apic_write(APIC_LVTT, APIC_LVT_MASKED);
972 apic_write(APIC_LVT0, APIC_LVT_MASKED);
973 apic_write(APIC_LVT1, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974 if (maxlvt >= 3)
Andi Kleen11a8e772006-01-11 22:46:51 +0100975 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976 if (maxlvt >= 4)
Andi Kleen11a8e772006-01-11 22:46:51 +0100977 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
Cyrill Gorcunov67640142008-08-16 23:21:50 +0400978
979 /* Integrated APIC (!82489DX) ? */
980 if (lapic_is_integrated()) {
981 if (maxlvt > 3)
982 /* Clear ESR due to Pentium errata 3AP and 11AP */
983 apic_write(APIC_ESR, 0);
984 apic_read(APIC_ESR);
985 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986}
987
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100988/**
989 * disable_local_APIC - clear and disable the local APIC
990 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991void disable_local_APIC(void)
992{
993 unsigned int value;
994
Jan Beulich4a13ad02009-01-14 12:28:51 +0000995 /* APIC hasn't been mapped yet */
Yinghai Lufd19dce2010-07-15 00:00:59 -0700996 if (!x2apic_mode && !apic_phys)
Jan Beulich4a13ad02009-01-14 12:28:51 +0000997 return;
998
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 clear_local_APIC();
1000
1001 /*
1002 * Disable APIC (implies clearing of registers
1003 * for 82489DX!).
1004 */
1005 value = apic_read(APIC_SPIV);
1006 value &= ~APIC_SPIV_APIC_ENABLED;
Andi Kleen11a8e772006-01-11 22:46:51 +01001007 apic_write(APIC_SPIV, value);
Cyrill Gorcunov990b1832008-08-18 20:45:51 +04001008
1009#ifdef CONFIG_X86_32
1010 /*
1011 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1012 * restore the disabled state.
1013 */
1014 if (enabled_via_apicbase) {
1015 unsigned int l, h;
1016
1017 rdmsr(MSR_IA32_APICBASE, l, h);
1018 l &= ~MSR_IA32_APICBASE_ENABLE;
1019 wrmsr(MSR_IA32_APICBASE, l, h);
1020 }
1021#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022}
1023
Cyrill Gorcunovfe4024d2008-08-18 20:45:52 +04001024/*
1025 * If Linux enabled the LAPIC against the BIOS default disable it down before
1026 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1027 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1028 * for the case where Linux didn't enable the LAPIC.
1029 */
Hiroshi Shimamoto9b7711f2007-10-19 18:21:11 -07001030void lapic_shutdown(void)
1031{
1032 unsigned long flags;
1033
Cyrill Gorcunov83121362009-09-15 11:12:30 +04001034 if (!cpu_has_apic && !apic_from_smp_config())
Hiroshi Shimamoto9b7711f2007-10-19 18:21:11 -07001035 return;
1036
1037 local_irq_save(flags);
1038
Cyrill Gorcunovfe4024d2008-08-18 20:45:52 +04001039#ifdef CONFIG_X86_32
1040 if (!enabled_via_apicbase)
1041 clear_local_APIC();
1042 else
1043#endif
1044 disable_local_APIC();
1045
Hiroshi Shimamoto9b7711f2007-10-19 18:21:11 -07001046
1047 local_irq_restore(flags);
1048}
1049
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050/*
1051 * This is to verify that we're looking at a real local APIC.
1052 * Check these against your board if the CPUs aren't getting
1053 * started for no apparent reason.
1054 */
1055int __init verify_local_APIC(void)
1056{
1057 unsigned int reg0, reg1;
1058
1059 /*
1060 * The version register is read-only in a real APIC.
1061 */
1062 reg0 = apic_read(APIC_LVR);
1063 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1064 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1065 reg1 = apic_read(APIC_LVR);
1066 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1067
1068 /*
1069 * The two version reads above should print the same
1070 * numbers. If the second one is different, then we
1071 * poke at a non-APIC.
1072 */
1073 if (reg1 != reg0)
1074 return 0;
1075
1076 /*
1077 * Check if the version looks reasonably.
1078 */
1079 reg1 = GET_APIC_VERSION(reg0);
1080 if (reg1 == 0x00 || reg1 == 0xff)
1081 return 0;
Thomas Gleixner37e650c2008-01-30 13:30:14 +01001082 reg1 = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 if (reg1 < 0x02 || reg1 == 0xff)
1084 return 0;
1085
1086 /*
1087 * The ID register is read/write in a real APIC.
1088 */
Suresh Siddha2d7a66d2008-07-11 14:24:19 -07001089 reg0 = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
Ingo Molnar5b812722009-01-28 14:59:17 +01001091 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
Suresh Siddha2d7a66d2008-07-11 14:24:19 -07001092 reg1 = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1094 apic_write(APIC_ID, reg0);
Ingo Molnar5b812722009-01-28 14:59:17 +01001095 if (reg1 != (reg0 ^ apic->apic_id_mask))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096 return 0;
1097
1098 /*
1099 * The next two are just to see if we have sane values.
1100 * They're only really relevant if we're in Virtual Wire
1101 * compatibility mode, but most boxes are anymore.
1102 */
1103 reg0 = apic_read(APIC_LVT0);
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001104 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105 reg1 = apic_read(APIC_LVT1);
1106 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1107
1108 return 1;
1109}
1110
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001111/**
1112 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1113 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114void __init sync_Arb_IDs(void)
1115{
Cyrill Gorcunov296cb952008-08-15 13:51:23 +02001116 /*
1117 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1118 * needed on AMD.
1119 */
1120 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121 return;
1122
1123 /*
1124 * Wait for idle.
1125 */
1126 apic_wait_icr_idle();
1127
1128 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
Cyrill Gorcunov6f6da972008-08-15 23:05:19 +04001129 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1130 APIC_INT_LEVELTRIG | APIC_DM_INIT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001131}
1132
Linus Torvalds1da177e2005-04-16 15:20:36 -07001133/*
1134 * An initial setup of the virtual wire mode.
1135 */
1136void __init init_bsp_APIC(void)
1137{
Andi Kleen11a8e772006-01-11 22:46:51 +01001138 unsigned int value;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139
1140 /*
1141 * Don't do the setup now if we have a SMP BIOS as the
1142 * through-I/O-APIC virtual wire mode might be active.
1143 */
1144 if (smp_found_config || !cpu_has_apic)
1145 return;
1146
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147 /*
1148 * Do not trust the local APIC being empty at bootup.
1149 */
1150 clear_local_APIC();
1151
1152 /*
1153 * Enable APIC.
1154 */
1155 value = apic_read(APIC_SPIV);
1156 value &= ~APIC_VECTOR_MASK;
1157 value |= APIC_SPIV_APIC_ENABLED;
Cyrill Gorcunov638c0412008-08-15 23:05:18 +04001158
1159#ifdef CONFIG_X86_32
1160 /* This bit is reserved on P4/Xeon and should be cleared */
1161 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1162 (boot_cpu_data.x86 == 15))
1163 value &= ~APIC_SPIV_FOCUS_DISABLED;
1164 else
1165#endif
1166 value |= APIC_SPIV_FOCUS_DISABLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167 value |= SPURIOUS_APIC_VECTOR;
Andi Kleen11a8e772006-01-11 22:46:51 +01001168 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001169
1170 /*
1171 * Set up the virtual wire mode.
1172 */
Andi Kleen11a8e772006-01-11 22:46:51 +01001173 apic_write(APIC_LVT0, APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001174 value = APIC_DM_NMI;
Cyrill Gorcunov638c0412008-08-15 23:05:18 +04001175 if (!lapic_is_integrated()) /* 82489DX */
1176 value |= APIC_LVT_LEVEL_TRIGGER;
Andi Kleen11a8e772006-01-11 22:46:51 +01001177 apic_write(APIC_LVT1, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178}
1179
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001180static void __cpuinit lapic_setup_esr(void)
1181{
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001182 unsigned int oldvalue, value, maxlvt;
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001183
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001184 if (!lapic_is_integrated()) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001185 pr_info("No ESR for 82489DX.\n");
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001186 return;
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001187 }
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001188
Ingo Molnar08125d32009-01-28 05:08:44 +01001189 if (apic->disable_esr) {
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001190 /*
1191 * Something untraceable is creating bad interrupts on
1192 * secondary quads ... for the moment, just leave the
1193 * ESR disabled - we can't do anything useful with the
1194 * errors anyway - mbligh
1195 */
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001196 pr_info("Leaving ESR disabled.\n");
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001197 return;
1198 }
1199
1200 maxlvt = lapic_get_maxlvt();
1201 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1202 apic_write(APIC_ESR, 0);
1203 oldvalue = apic_read(APIC_ESR);
1204
1205 /* enables sending errors */
1206 value = ERROR_APIC_VECTOR;
1207 apic_write(APIC_LVTERR, value);
1208
1209 /*
1210 * spec says clear errors after enabling vector.
1211 */
1212 if (maxlvt > 3)
1213 apic_write(APIC_ESR, 0);
1214 value = apic_read(APIC_ESR);
1215 if (value != oldvalue)
1216 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1217 "vector: 0x%08x after: 0x%08x\n",
1218 oldvalue, value);
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001219}
1220
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001221/**
1222 * setup_local_APIC - setup the local APIC
Tejun Heo0aa002f2010-12-09 11:47:21 +01001223 *
1224 * Used to setup local APIC while initializing BSP or bringin up APs.
1225 * Always called with preemption disabled.
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001226 */
1227void __cpuinit setup_local_APIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228{
Tejun Heo0aa002f2010-12-09 11:47:21 +01001229 int cpu = smp_processor_id();
Kerstin Jonsson8c3ba8d2010-05-24 12:13:15 -07001230 unsigned int value, queued;
1231 int i, j, acked = 0;
1232 unsigned long long tsc = 0, ntsc;
1233 long long max_loops = cpu_khz;
1234
1235 if (cpu_has_tsc)
1236 rdtscll(tsc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237
Jan Beulichf1182632009-01-14 12:27:35 +00001238 if (disable_apic) {
Henrik Kretzschmar7167d082011-02-22 15:38:05 +01001239 disable_ioapic_support();
Jan Beulichf1182632009-01-14 12:27:35 +00001240 return;
1241 }
1242
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001243#ifdef CONFIG_X86_32
1244 /* Pound the ESR really hard over the head with a big hammer - mbligh */
Ingo Molnar08125d32009-01-28 05:08:44 +01001245 if (lapic_is_integrated() && apic->disable_esr) {
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001246 apic_write(APIC_ESR, 0);
1247 apic_write(APIC_ESR, 0);
1248 apic_write(APIC_ESR, 0);
1249 apic_write(APIC_ESR, 0);
1250 }
1251#endif
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001252 perf_events_lapic_init();
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001253
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254 /*
1255 * Double-check whether this APIC is really registered.
1256 * This is meaningless in clustered apic mode, so we skip it.
1257 */
Daniel Walkerc2777f92009-09-12 10:40:20 -07001258 BUG_ON(!apic->apic_id_registered());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001259
1260 /*
1261 * Intel recommends to set DFR, LDR and TPR before enabling
1262 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1263 * document number 292116). So here it goes...
1264 */
Ingo Molnara5c43292009-01-28 06:50:47 +01001265 apic->init_apic_ldr();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001266
Tejun Heo6f802c42011-01-23 14:37:31 +01001267#ifdef CONFIG_X86_32
1268 /*
Tejun Heoacb8bc02011-01-23 14:37:33 +01001269 * APIC LDR is initialized. If logical_apicid mapping was
1270 * initialized during get_smp_config(), make sure it matches the
1271 * actual value.
Tejun Heo6f802c42011-01-23 14:37:31 +01001272 */
Tejun Heoacb8bc02011-01-23 14:37:33 +01001273 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1274 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1275 /* always use the value from LDR */
Tejun Heo6f802c42011-01-23 14:37:31 +01001276 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1277 logical_smp_processor_id();
Tejun Heoc4b90c12011-05-02 14:18:52 +02001278
1279 /*
1280 * Some NUMA implementations (NUMAQ) don't initialize apicid to
1281 * node mapping during NUMA init. Now that logical apicid is
1282 * guaranteed to be known, give it another chance. This is already
1283 * a bit too late - percpu allocation has already happened without
1284 * proper NUMA affinity.
1285 */
Tejun Heo84914ed02011-05-02 14:18:52 +02001286 if (apic->x86_32_numa_cpu_node)
1287 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
1288 apic->x86_32_numa_cpu_node(cpu));
Tejun Heo6f802c42011-01-23 14:37:31 +01001289#endif
1290
Linus Torvalds1da177e2005-04-16 15:20:36 -07001291 /*
1292 * Set Task Priority to 'accept all'. We never change this
1293 * later on.
1294 */
1295 value = apic_read(APIC_TASKPRI);
1296 value &= ~APIC_TPRI_MASK;
Andi Kleen11a8e772006-01-11 22:46:51 +01001297 apic_write(APIC_TASKPRI, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298
1299 /*
Vivek Goyalda7ed9f2006-03-25 16:31:16 +01001300 * After a crash, we no longer service the interrupts and a pending
1301 * interrupt from previous kernel might still have ISR bit set.
1302 *
1303 * Most probably by now CPU has serviced that pending interrupt and
1304 * it might not have done the ack_APIC_irq() because it thought,
1305 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1306 * does not clear the ISR bit and cpu thinks it has already serivced
1307 * the interrupt. Hence a vector might get locked. It was noticed
1308 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1309 */
Kerstin Jonsson8c3ba8d2010-05-24 12:13:15 -07001310 do {
1311 queued = 0;
1312 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1313 queued |= apic_read(APIC_IRR + i*0x10);
1314
1315 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1316 value = apic_read(APIC_ISR + i*0x10);
1317 for (j = 31; j >= 0; j--) {
1318 if (value & (1<<j)) {
1319 ack_APIC_irq();
1320 acked++;
1321 }
1322 }
Vivek Goyalda7ed9f2006-03-25 16:31:16 +01001323 }
Kerstin Jonsson8c3ba8d2010-05-24 12:13:15 -07001324 if (acked > 256) {
1325 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1326 acked);
1327 break;
1328 }
Shai Fultheim42fa4252012-04-20 01:12:32 +03001329 if (queued) {
1330 if (cpu_has_tsc) {
1331 rdtscll(ntsc);
1332 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1333 } else
1334 max_loops--;
1335 }
Kerstin Jonsson8c3ba8d2010-05-24 12:13:15 -07001336 } while (queued && max_loops > 0);
1337 WARN_ON(max_loops <= 0);
Vivek Goyalda7ed9f2006-03-25 16:31:16 +01001338
1339 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001340 * Now that we are all set up, enable the APIC
1341 */
1342 value = apic_read(APIC_SPIV);
1343 value &= ~APIC_VECTOR_MASK;
1344 /*
1345 * Enable APIC
1346 */
1347 value |= APIC_SPIV_APIC_ENABLED;
1348
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001349#ifdef CONFIG_X86_32
1350 /*
1351 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1352 * certain networking cards. If high frequency interrupts are
1353 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1354 * entry is masked/unmasked at a high rate as well then sooner or
1355 * later IOAPIC line gets 'stuck', no more interrupts are received
1356 * from the device. If focus CPU is disabled then the hang goes
1357 * away, oh well :-(
1358 *
1359 * [ This bug can be reproduced easily with a level-triggered
1360 * PCI Ne2000 networking cards and PII/PIII processors, dual
1361 * BX chipset. ]
1362 */
1363 /*
1364 * Actually disabling the focus CPU check just makes the hang less
1365 * frequent as it makes the interrupt distributon model be more
1366 * like LRU than MRU (the short-term load is more even across CPUs).
1367 * See also the comment in end_level_ioapic_irq(). --macro
1368 */
1369
1370 /*
1371 * - enable focus processor (bit==0)
1372 * - 64bit mode always use processor focus
1373 * so no need to set it
1374 */
1375 value &= ~APIC_SPIV_FOCUS_DISABLED;
1376#endif
Andi Kleen3f14c742006-09-26 10:52:29 +02001377
Linus Torvalds1da177e2005-04-16 15:20:36 -07001378 /*
1379 * Set spurious IRQ vector
1380 */
1381 value |= SPURIOUS_APIC_VECTOR;
Andi Kleen11a8e772006-01-11 22:46:51 +01001382 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001383
1384 /*
1385 * Set up LVT0, LVT1:
1386 *
1387 * set up through-local-APIC on the BP's LINT0. This is not
1388 * strictly necessary in pure symmetric-IO mode, but sometimes
1389 * we delegate interrupts to the 8259A.
1390 */
1391 /*
1392 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1393 */
1394 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
Tejun Heo0aa002f2010-12-09 11:47:21 +01001395 if (!cpu && (pic_mode || !value)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001396 value = APIC_DM_EXTINT;
Tejun Heo0aa002f2010-12-09 11:47:21 +01001397 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001398 } else {
1399 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
Tejun Heo0aa002f2010-12-09 11:47:21 +01001400 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001401 }
Andi Kleen11a8e772006-01-11 22:46:51 +01001402 apic_write(APIC_LVT0, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001403
1404 /*
1405 * only the BP should see the LINT1 NMI signal, obviously.
1406 */
Tejun Heo0aa002f2010-12-09 11:47:21 +01001407 if (!cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001408 value = APIC_DM_NMI;
1409 else
1410 value = APIC_DM_NMI | APIC_LVT_MASKED;
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001411 if (!lapic_is_integrated()) /* 82489DX */
1412 value |= APIC_LVT_LEVEL_TRIGGER;
Andi Kleen11a8e772006-01-11 22:46:51 +01001413 apic_write(APIC_LVT1, value);
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001414
Andi Kleenbe71b852009-02-12 13:49:38 +01001415#ifdef CONFIG_X86_MCE_INTEL
1416 /* Recheck CMCI information after local APIC is up on CPU #0 */
Tejun Heo0aa002f2010-12-09 11:47:21 +01001417 if (!cpu)
Andi Kleenbe71b852009-02-12 13:49:38 +01001418 cmci_recheck();
1419#endif
Andi Kleen739f33b2008-01-30 13:30:40 +01001420}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001421
Andi Kleen739f33b2008-01-30 13:30:40 +01001422void __cpuinit end_local_APIC_setup(void)
1423{
1424 lapic_setup_esr();
Cyrill Gorcunovfa6b95f2008-08-18 20:45:58 +04001425
1426#ifdef CONFIG_X86_32
Cyrill Gorcunov1b4ee4e2008-08-18 23:12:33 +04001427 {
1428 unsigned int value;
1429 /* Disable the local apic timer */
1430 value = apic_read(APIC_LVTT);
1431 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1432 apic_write(APIC_LVTT, value);
1433 }
Cyrill Gorcunovfa6b95f2008-08-18 20:45:58 +04001434#endif
1435
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436 apic_pm_activate();
Jan Beulich2fb270f2011-02-09 08:21:02 +00001437}
1438
1439void __init bsp_end_local_APIC_setup(void)
1440{
1441 end_local_APIC_setup();
Kenji Kaneshige7f7fbf42010-11-30 22:22:28 -08001442
1443 /*
1444 * Now that local APIC setup is completed for BP, configure the fault
1445 * handling for interrupt remapping.
1446 */
Suresh Siddha95a02e92012-03-30 11:47:07 -07001447 if (irq_remapping_enabled)
1448 irq_remap_enable_fault_handling();
Kenji Kaneshige7f7fbf42010-11-30 22:22:28 -08001449
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450}
1451
Yinghai Lu06cd9a72009-02-16 17:29:58 -08001452#ifdef CONFIG_X86_X2APIC
Yinghai Lufb209bd2011-12-21 17:45:17 -08001453/*
1454 * Need to disable xapic and x2apic at the same time and then enable xapic mode
1455 */
1456static inline void __disable_x2apic(u64 msr)
1457{
1458 wrmsrl(MSR_IA32_APICBASE,
1459 msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1460 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1461}
1462
Yinghai Lua31bc322011-12-23 11:01:43 -08001463static __init void disable_x2apic(void)
Yinghai Lufb209bd2011-12-21 17:45:17 -08001464{
1465 u64 msr;
1466
1467 if (!cpu_has_x2apic)
1468 return;
1469
1470 rdmsrl(MSR_IA32_APICBASE, msr);
1471 if (msr & X2APIC_ENABLE) {
1472 u32 x2apic_id = read_apic_id();
1473
1474 if (x2apic_id >= 255)
1475 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1476
1477 pr_info("Disabling x2apic\n");
1478 __disable_x2apic(msr);
1479
Yinghai Lua31bc322011-12-23 11:01:43 -08001480 if (nox2apic) {
1481 clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC);
1482 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1483 }
1484
Yinghai Lufb209bd2011-12-21 17:45:17 -08001485 x2apic_disabled = 1;
1486 x2apic_mode = 0;
1487
1488 register_lapic_address(mp_lapic_addr);
1489 }
1490}
1491
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001492void check_x2apic(void)
1493{
Suresh Siddhaef1f87a2009-02-21 14:23:21 -08001494 if (x2apic_enabled()) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001495 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
Suresh Siddhafc1edaf2009-04-20 13:02:27 -07001496 x2apic_preenabled = x2apic_mode = 1;
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001497 }
1498}
1499
1500void enable_x2apic(void)
1501{
Yinghai Lufb209bd2011-12-21 17:45:17 -08001502 u64 msr;
1503
1504 rdmsrl(MSR_IA32_APICBASE, msr);
1505 if (x2apic_disabled) {
1506 __disable_x2apic(msr);
1507 return;
1508 }
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001509
Suresh Siddhafc1edaf2009-04-20 13:02:27 -07001510 if (!x2apic_mode)
Yinghai Lu06cd9a72009-02-16 17:29:58 -08001511 return;
1512
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001513 if (!(msr & X2APIC_ENABLE)) {
Mike Travis450b1e82009-12-11 08:08:50 -08001514 printk_once(KERN_INFO "Enabling x2apic\n");
Yinghai Lufb209bd2011-12-21 17:45:17 -08001515 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001516 }
1517}
Weidong Han93758232009-04-17 16:42:14 +08001518#endif /* CONFIG_X86_X2APIC */
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001519
Gleb Natapovce69a782009-07-20 15:24:17 +03001520int __init enable_IR(void)
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001521{
Suresh Siddhad3f13812011-08-23 17:05:25 -07001522#ifdef CONFIG_IRQ_REMAP
Suresh Siddha95a02e92012-03-30 11:47:07 -07001523 if (!irq_remapping_supported()) {
Weidong Han93758232009-04-17 16:42:14 +08001524 pr_debug("intr-remapping not supported\n");
Suresh Siddha41750d32011-08-23 17:05:18 -07001525 return -1;
Weidong Han93758232009-04-17 16:42:14 +08001526 }
1527
Weidong Han93758232009-04-17 16:42:14 +08001528 if (!x2apic_preenabled && skip_ioapic_setup) {
1529 pr_info("Skipped enabling intr-remap because of skipping "
1530 "io-apic setup\n");
Suresh Siddha41750d32011-08-23 17:05:18 -07001531 return -1;
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001532 }
1533
Suresh Siddha95a02e92012-03-30 11:47:07 -07001534 return irq_remapping_enable();
Gleb Natapovce69a782009-07-20 15:24:17 +03001535#endif
Suresh Siddha41750d32011-08-23 17:05:18 -07001536 return -1;
Gleb Natapovce69a782009-07-20 15:24:17 +03001537}
1538
1539void __init enable_IR_x2apic(void)
1540{
1541 unsigned long flags;
Gleb Natapovce69a782009-07-20 15:24:17 +03001542 int ret, x2apic_enabled = 0;
Joerg Roedel736baef2012-03-30 11:47:00 -07001543 int hardware_init_ret;
Yinghai Lub7f42ab2009-08-17 11:19:40 -07001544
Joerg Roedel736baef2012-03-30 11:47:00 -07001545 /* Make sure irq_remap_ops are initialized */
Suresh Siddha95a02e92012-03-30 11:47:07 -07001546 setup_irq_remapping_ops();
Joerg Roedel736baef2012-03-30 11:47:00 -07001547
Suresh Siddha95a02e92012-03-30 11:47:07 -07001548 hardware_init_ret = irq_remapping_prepare();
Joerg Roedel736baef2012-03-30 11:47:00 -07001549 if (hardware_init_ret && !x2apic_supported())
Yinghai Lue6707612009-11-21 00:23:37 -08001550 return;
Gleb Natapovce69a782009-07-20 15:24:17 +03001551
Suresh Siddha31dce142011-05-18 16:31:33 -07001552 ret = save_ioapic_entries();
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001553 if (ret) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001554 pr_info("Saving IO-APIC state failed: %d\n", ret);
Yinghai Lufb209bd2011-12-21 17:45:17 -08001555 return;
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001556 }
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001557
Suresh Siddha05c3dc22009-03-16 17:05:03 -07001558 local_irq_save(flags);
Jacob Panb81bb372009-11-09 11:27:04 -08001559 legacy_pic->mask_all();
Suresh Siddha31dce142011-05-18 16:31:33 -07001560 mask_ioapic_entries();
Suresh Siddha05c3dc22009-03-16 17:05:03 -07001561
Yinghai Lua31bc322011-12-23 11:01:43 -08001562 if (x2apic_preenabled && nox2apic)
1563 disable_x2apic();
1564
Joerg Roedel736baef2012-03-30 11:47:00 -07001565 if (hardware_init_ret)
Suresh Siddha41750d32011-08-23 17:05:18 -07001566 ret = -1;
Yinghai Lub7f42ab2009-08-17 11:19:40 -07001567 else
1568 ret = enable_IR();
1569
Yinghai Lufb209bd2011-12-21 17:45:17 -08001570 if (!x2apic_supported())
Yinghai Lua31bc322011-12-23 11:01:43 -08001571 goto skip_x2apic;
Yinghai Lufb209bd2011-12-21 17:45:17 -08001572
Suresh Siddha41750d32011-08-23 17:05:18 -07001573 if (ret < 0) {
Gleb Natapovce69a782009-07-20 15:24:17 +03001574 /* IR is required if there is APIC ID > 255 even when running
1575 * under KVM
1576 */
Sheng Yang2904ed82010-12-21 14:18:48 +08001577 if (max_physical_apicid > 255 ||
Yinghai Lufb209bd2011-12-21 17:45:17 -08001578 !hypervisor_x2apic_available()) {
1579 if (x2apic_preenabled)
1580 disable_x2apic();
Yinghai Lua31bc322011-12-23 11:01:43 -08001581 goto skip_x2apic;
Yinghai Lufb209bd2011-12-21 17:45:17 -08001582 }
Gleb Natapovce69a782009-07-20 15:24:17 +03001583 /*
1584 * without IR all CPUs can be addressed by IOAPIC/MSI
1585 * only in physical mode
1586 */
1587 x2apic_force_phys();
1588 }
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001589
Yinghai Lufb209bd2011-12-21 17:45:17 -08001590 if (ret == IRQ_REMAP_XAPIC_MODE) {
1591 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
Yinghai Lua31bc322011-12-23 11:01:43 -08001592 goto skip_x2apic;
Yinghai Lufb209bd2011-12-21 17:45:17 -08001593 }
Suresh Siddha41750d32011-08-23 17:05:18 -07001594
Gleb Natapovce69a782009-07-20 15:24:17 +03001595 x2apic_enabled = 1;
Weidong Han93758232009-04-17 16:42:14 +08001596
Suresh Siddhafc1edaf2009-04-20 13:02:27 -07001597 if (x2apic_supported() && !x2apic_mode) {
1598 x2apic_mode = 1;
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001599 enable_x2apic();
Weidong Han93758232009-04-17 16:42:14 +08001600 pr_info("Enabled x2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001601 }
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001602
Yinghai Lua31bc322011-12-23 11:01:43 -08001603skip_x2apic:
Suresh Siddha41750d32011-08-23 17:05:18 -07001604 if (ret < 0) /* IR enabling failed */
Suresh Siddha31dce142011-05-18 16:31:33 -07001605 restore_ioapic_entries();
Jacob Panb81bb372009-11-09 11:27:04 -08001606 legacy_pic->restore_mask();
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001607 local_irq_restore(flags);
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001608}
Weidong Han93758232009-04-17 16:42:14 +08001609
Yinghai Lube7a6562008-08-24 02:01:51 -07001610#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001611/*
1612 * Detect and enable local APICs on non-SMP boards.
1613 * Original code written by Keir Fraser.
1614 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1615 * not correctly set up (usually the APIC timer won't work etc.)
1616 */
1617static int __init detect_init_APIC(void)
1618{
1619 if (!cpu_has_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001620 pr_info("No local APIC present\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001621 return -1;
1622 }
1623
1624 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001625 return 0;
1626}
Yinghai Lube7a6562008-08-24 02:01:51 -07001627#else
Thomas Gleixner5a7ae782010-10-19 10:46:28 -07001628
Henrik Kretzschmar25874a22011-03-11 08:02:36 +01001629static int __init apic_verify(void)
Thomas Gleixner5a7ae782010-10-19 10:46:28 -07001630{
1631 u32 features, h, l;
1632
1633 /*
1634 * The APIC feature bit should now be enabled
1635 * in `cpuid'
1636 */
1637 features = cpuid_edx(1);
1638 if (!(features & (1 << X86_FEATURE_APIC))) {
1639 pr_warning("Could not enable APIC!\n");
1640 return -1;
1641 }
1642 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1643 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1644
1645 /* The BIOS may have set up the APIC at some other address */
Bryan O'Donoghuecbf28292012-04-18 17:37:39 +01001646 if (boot_cpu_data.x86 >= 6) {
1647 rdmsr(MSR_IA32_APICBASE, l, h);
1648 if (l & MSR_IA32_APICBASE_ENABLE)
1649 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1650 }
Thomas Gleixner5a7ae782010-10-19 10:46:28 -07001651
1652 pr_info("Found and enabled local APIC!\n");
1653 return 0;
1654}
1655
Henrik Kretzschmar25874a22011-03-11 08:02:36 +01001656int __init apic_force_enable(unsigned long addr)
Thomas Gleixner5a7ae782010-10-19 10:46:28 -07001657{
1658 u32 h, l;
1659
1660 if (disable_apic)
1661 return -1;
1662
1663 /*
1664 * Some BIOSes disable the local APIC in the APIC_BASE
1665 * MSR. This can only be done in software for Intel P6 or later
1666 * and AMD K7 (Model > 1) or later.
1667 */
Bryan O'Donoghuecbf28292012-04-18 17:37:39 +01001668 if (boot_cpu_data.x86 >= 6) {
1669 rdmsr(MSR_IA32_APICBASE, l, h);
1670 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1671 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1672 l &= ~MSR_IA32_APICBASE_BASE;
1673 l |= MSR_IA32_APICBASE_ENABLE | addr;
1674 wrmsr(MSR_IA32_APICBASE, l, h);
1675 enabled_via_apicbase = 1;
1676 }
Thomas Gleixner5a7ae782010-10-19 10:46:28 -07001677 }
1678 return apic_verify();
1679}
1680
Yinghai Lube7a6562008-08-24 02:01:51 -07001681/*
1682 * Detect and initialize APIC
1683 */
1684static int __init detect_init_APIC(void)
1685{
Yinghai Lube7a6562008-08-24 02:01:51 -07001686 /* Disabled by kernel option? */
1687 if (disable_apic)
1688 return -1;
1689
1690 switch (boot_cpu_data.x86_vendor) {
1691 case X86_VENDOR_AMD:
1692 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
Borislav Petkov85877062009-02-03 16:24:22 +01001693 (boot_cpu_data.x86 >= 15))
Yinghai Lube7a6562008-08-24 02:01:51 -07001694 break;
1695 goto no_apic;
1696 case X86_VENDOR_INTEL:
1697 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1698 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1699 break;
1700 goto no_apic;
1701 default:
1702 goto no_apic;
1703 }
1704
1705 if (!cpu_has_apic) {
1706 /*
1707 * Over-ride BIOS and try to enable the local APIC only if
1708 * "lapic" specified.
1709 */
1710 if (!force_enable_local_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001711 pr_info("Local APIC disabled by BIOS -- "
1712 "you can enable it with \"lapic\"\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001713 return -1;
1714 }
Thomas Gleixnera906fda2011-02-25 16:09:31 +01001715 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
Thomas Gleixner5a7ae782010-10-19 10:46:28 -07001716 return -1;
1717 } else {
1718 if (apic_verify())
1719 return -1;
Yinghai Lube7a6562008-08-24 02:01:51 -07001720 }
Yinghai Lube7a6562008-08-24 02:01:51 -07001721
1722 apic_pm_activate();
1723
1724 return 0;
1725
1726no_apic:
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001727 pr_info("No local APIC present or hardware disabled\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001728 return -1;
1729}
1730#endif
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001731
1732/**
1733 * init_apic_mappings - initialize APIC mappings
1734 */
1735void __init init_apic_mappings(void)
1736{
Yinghai Lu4401da62009-05-02 10:40:57 -07001737 unsigned int new_apicid;
1738
Suresh Siddhafc1edaf2009-04-20 13:02:27 -07001739 if (x2apic_mode) {
Yinghai Lu4c9961d2008-07-11 18:44:16 -07001740 boot_cpu_physical_apicid = read_apic_id();
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001741 return;
1742 }
1743
Yinghai Lu4797f6b2009-05-02 10:40:57 -07001744 /* If no local APIC can be found return early */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001745 if (!smp_found_config && detect_init_APIC()) {
Yinghai Lu4797f6b2009-05-02 10:40:57 -07001746 /* lets NOP'ify apic operations */
Cyrill Gorcunovcec6be62009-05-11 17:41:40 +04001747 pr_info("APIC: disable apic facility\n");
1748 apic_disable();
Yinghai Lu4797f6b2009-05-02 10:40:57 -07001749 } else {
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001750 apic_phys = mp_lapic_addr;
1751
Yinghai Lu4797f6b2009-05-02 10:40:57 -07001752 /*
1753 * acpi lapic path already maps that address in
1754 * acpi_register_lapic_address()
1755 */
Eric W. Biederman5989cd62010-08-04 13:30:27 -07001756 if (!acpi_lapic && !smp_found_config)
Yinghai Lu326a2e62010-12-07 00:55:38 -08001757 register_lapic_address(apic_phys);
Cyrill Gorcunovcec6be62009-05-11 17:41:40 +04001758 }
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001759
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001760 /*
1761 * Fetch the APIC ID of the BSP in case we have a
1762 * default configuration (or the MP table is broken).
1763 */
Yinghai Lu4401da62009-05-02 10:40:57 -07001764 new_apicid = read_apic_id();
1765 if (boot_cpu_physical_apicid != new_apicid) {
1766 boot_cpu_physical_apicid = new_apicid;
Cyrill Gorcunov103428e2009-06-07 16:48:40 +04001767 /*
1768 * yeah -- we lie about apic_version
1769 * in case if apic was disabled via boot option
1770 * but it's not a problem for SMP compiled kernel
1771 * since smp_sanity_check is prepared for such a case
1772 * and disable smp mode
1773 */
Yinghai Lu4401da62009-05-02 10:40:57 -07001774 apic_version[new_apicid] =
1775 GET_APIC_VERSION(apic_read(APIC_LVR));
Cyrill Gorcunov08306ce2009-04-12 20:47:41 +04001776 }
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001777}
1778
Yinghai Luc0104d32010-12-07 00:55:17 -08001779void __init register_lapic_address(unsigned long address)
1780{
1781 mp_lapic_addr = address;
1782
Yinghai Lu04501932010-12-07 00:55:56 -08001783 if (!x2apic_mode) {
1784 set_fixmap_nocache(FIX_APIC_BASE, address);
1785 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1786 APIC_BASE, mp_lapic_addr);
1787 }
Yinghai Luc0104d32010-12-07 00:55:17 -08001788 if (boot_cpu_physical_apicid == -1U) {
1789 boot_cpu_physical_apicid = read_apic_id();
1790 apic_version[boot_cpu_physical_apicid] =
1791 GET_APIC_VERSION(apic_read(APIC_LVR));
1792 }
1793}
1794
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001795/*
1796 * This initializes the IO-APIC and APIC hardware if this is
1797 * a UP kernel.
1798 */
Yinghai Lu56d91f12010-12-16 19:09:24 -08001799int apic_version[MAX_LOCAL_APIC];
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001800
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001801int __init APIC_init_uniprocessor(void)
1802{
1803 if (disable_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001804 pr_info("Apic disabled\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001805 return -1;
1806 }
Jan Beulichf1182632009-01-14 12:27:35 +00001807#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001808 if (!cpu_has_apic) {
1809 disable_apic = 1;
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001810 pr_info("Apic disabled by BIOS\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001811 return -1;
1812 }
Yinghai Lufa2bd352008-08-24 02:01:50 -07001813#else
1814 if (!smp_found_config && !cpu_has_apic)
1815 return -1;
1816
1817 /*
1818 * Complain if the BIOS pretends there is one.
1819 */
1820 if (!cpu_has_apic &&
1821 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001822 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1823 boot_cpu_physical_apicid);
Yinghai Lufa2bd352008-08-24 02:01:50 -07001824 return -1;
1825 }
1826#endif
1827
Ingo Molnar72ce0162009-01-28 06:50:47 +01001828 default_setup_apic_routing();
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001829
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001830 verify_local_APIC();
Glauber Costab5841762008-05-28 13:38:28 -03001831 connect_bsp_APIC();
1832
Yinghai Lufa2bd352008-08-24 02:01:50 -07001833#ifdef CONFIG_X86_64
Glauber de Oliveira Costac70dcb72008-03-19 14:25:58 -03001834 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
Yinghai Lufa2bd352008-08-24 02:01:50 -07001835#else
1836 /*
1837 * Hack: In case of kdump, after a crash, kernel might be booting
1838 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1839 * might be zero if read from MP tables. Get it from LAPIC.
1840 */
1841# ifdef CONFIG_CRASH_DUMP
1842 boot_cpu_physical_apicid = read_apic_id();
1843# endif
1844#endif
1845 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001846 setup_local_APIC();
1847
Yinghai Lu88d0f552009-02-14 23:57:28 -08001848#ifdef CONFIG_X86_IO_APIC
Andi Kleen739f33b2008-01-30 13:30:40 +01001849 /*
1850 * Now enable IO-APICs, actually call clear_IO_APIC
Yinghai Lu98c061b2009-02-16 00:00:50 -08001851 * We need clear_IO_APIC before enabling error vector
Andi Kleen739f33b2008-01-30 13:30:40 +01001852 */
1853 if (!skip_ioapic_setup && nr_ioapics)
1854 enable_IO_APIC();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001855#endif
Andi Kleen739f33b2008-01-30 13:30:40 +01001856
Jan Beulich2fb270f2011-02-09 08:21:02 +00001857 bsp_end_local_APIC_setup();
Andi Kleen739f33b2008-01-30 13:30:40 +01001858
Yinghai Lufa2bd352008-08-24 02:01:50 -07001859#ifdef CONFIG_X86_IO_APIC
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001860 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1861 setup_IO_APIC();
Yinghai Lu98c061b2009-02-16 00:00:50 -08001862 else {
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001863 nr_ioapics = 0;
Yinghai Lu98c061b2009-02-16 00:00:50 -08001864 }
Yinghai Lufa2bd352008-08-24 02:01:50 -07001865#endif
1866
Thomas Gleixner736deca2009-08-19 12:35:53 +02001867 x86_init.timers.setup_percpu_clockev();
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001868 return 0;
1869}
1870
1871/*
1872 * Local APIC interrupts
1873 */
1874
1875/*
1876 * This interrupt should _never_ happen with our APIC/SMP architecture
1877 */
Yinghai Ludc1528d2008-08-24 02:01:53 -07001878void smp_spurious_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001879{
Yinghai Ludc1528d2008-08-24 02:01:53 -07001880 u32 v;
1881
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001882 irq_enter();
Frederic Weisbecker98ad1cc2011-10-07 18:22:09 +02001883 exit_idle();
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001884 /*
1885 * Check if this really is a spurious interrupt and ACK it
1886 * if it is a vectored one. Just in case...
1887 * Spurious interrupts should not be ACKed.
1888 */
1889 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1890 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1891 ack_APIC_irq();
1892
Hiroshi Shimamoto915b0d02008-12-08 19:19:26 -08001893 inc_irq_stat(irq_spurious_count);
1894
Yinghai Ludc1528d2008-08-24 02:01:53 -07001895 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001896 pr_info("spurious APIC interrupt on CPU#%d, "
1897 "should never happen.\n", smp_processor_id());
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001898 irq_exit();
1899}
1900
1901/*
1902 * This interrupt should never happen with our APIC/SMP architecture
1903 */
Yinghai Ludc1528d2008-08-24 02:01:53 -07001904void smp_error_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001905{
Youquan Song2b398bd2011-04-14 14:36:08 +08001906 u32 v0, v1;
1907 u32 i = 0;
1908 static const char * const error_interrupt_reason[] = {
1909 "Send CS error", /* APIC Error Bit 0 */
1910 "Receive CS error", /* APIC Error Bit 1 */
1911 "Send accept error", /* APIC Error Bit 2 */
1912 "Receive accept error", /* APIC Error Bit 3 */
1913 "Redirectable IPI", /* APIC Error Bit 4 */
1914 "Send illegal vector", /* APIC Error Bit 5 */
1915 "Received illegal vector", /* APIC Error Bit 6 */
1916 "Illegal register address", /* APIC Error Bit 7 */
1917 };
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001918
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001919 irq_enter();
Frederic Weisbecker98ad1cc2011-10-07 18:22:09 +02001920 exit_idle();
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001921 /* First tickle the hardware, only then report what went on. -- REW */
Youquan Song2b398bd2011-04-14 14:36:08 +08001922 v0 = apic_read(APIC_ESR);
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001923 apic_write(APIC_ESR, 0);
1924 v1 = apic_read(APIC_ESR);
1925 ack_APIC_irq();
1926 atomic_inc(&irq_err_count);
1927
Youquan Song2b398bd2011-04-14 14:36:08 +08001928 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
1929 smp_processor_id(), v0 , v1);
1930
1931 v1 = v1 & 0xff;
1932 while (v1) {
1933 if (v1 & 0x1)
1934 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1935 i++;
1936 v1 >>= 1;
Peter Senna Tschudin4b8073e2012-09-18 18:36:14 +02001937 }
Youquan Song2b398bd2011-04-14 14:36:08 +08001938
1939 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1940
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001941 irq_exit();
1942}
1943
Glauber Costab5841762008-05-28 13:38:28 -03001944/**
Cyrill Gorcunov36c9d672008-08-18 20:45:53 +04001945 * connect_bsp_APIC - attach the APIC to the interrupt system
1946 */
Glauber Costab5841762008-05-28 13:38:28 -03001947void __init connect_bsp_APIC(void)
1948{
Cyrill Gorcunov36c9d672008-08-18 20:45:53 +04001949#ifdef CONFIG_X86_32
1950 if (pic_mode) {
1951 /*
1952 * Do not trust the local APIC being empty at bootup.
1953 */
1954 clear_local_APIC();
1955 /*
1956 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1957 * local APIC to INT and NMI lines.
1958 */
1959 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1960 "enabling APIC mode.\n");
Cyrill Gorcunovc0eaa452009-04-12 20:47:40 +04001961 imcr_pic_to_apic();
Cyrill Gorcunov36c9d672008-08-18 20:45:53 +04001962 }
1963#endif
Ingo Molnar49040332009-01-28 12:43:18 +01001964 if (apic->enable_apic_mode)
1965 apic->enable_apic_mode();
Glauber Costab5841762008-05-28 13:38:28 -03001966}
1967
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04001968/**
1969 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1970 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1971 *
1972 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1973 * APIC is disabled.
1974 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001975void disconnect_bsp_APIC(int virt_wire_setup)
1976{
Cyrill Gorcunov1b4ee4e2008-08-18 23:12:33 +04001977 unsigned int value;
1978
Cyrill Gorcunovc177b0b2008-08-18 20:45:56 +04001979#ifdef CONFIG_X86_32
1980 if (pic_mode) {
1981 /*
1982 * Put the board back into PIC mode (has an effect only on
1983 * certain older boards). Note that APIC interrupts, including
1984 * IPIs, won't work beyond this point! The only exception are
1985 * INIT IPIs.
1986 */
1987 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1988 "entering PIC mode.\n");
Cyrill Gorcunovc0eaa452009-04-12 20:47:40 +04001989 imcr_apic_to_pic();
Cyrill Gorcunovc177b0b2008-08-18 20:45:56 +04001990 return;
1991 }
1992#endif
1993
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001994 /* Go back to Virtual Wire compatibility mode */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001995
1996 /* For the spurious interrupt use vector F, and enable it */
1997 value = apic_read(APIC_SPIV);
1998 value &= ~APIC_VECTOR_MASK;
1999 value |= APIC_SPIV_APIC_ENABLED;
2000 value |= 0xf;
2001 apic_write(APIC_SPIV, value);
2002
2003 if (!virt_wire_setup) {
2004 /*
2005 * For LVT0 make it edge triggered, active high,
2006 * external and enabled
2007 */
2008 value = apic_read(APIC_LVT0);
2009 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2010 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2011 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2012 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2013 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2014 apic_write(APIC_LVT0, value);
2015 } else {
2016 /* Disable LVT0 */
2017 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2018 }
2019
Cyrill Gorcunovc177b0b2008-08-18 20:45:56 +04002020 /*
2021 * For LVT1 make it edge triggered, active high,
2022 * nmi and enabled
2023 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01002024 value = apic_read(APIC_LVT1);
2025 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2026 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2027 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2028 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2029 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2030 apic_write(APIC_LVT1, value);
2031}
2032
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03002033void __cpuinit generic_processor_info(int apicid, int version)
2034{
Vivek Goyal14cb6dc2011-07-08 13:19:26 -04002035 int cpu, max = nr_cpu_ids;
2036 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2037 phys_cpu_present_map);
2038
2039 /*
2040 * If boot cpu has not been detected yet, then only allow upto
2041 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2042 */
2043 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2044 apicid != boot_cpu_physical_apicid) {
2045 int thiscpu = max + disabled_cpus - 1;
2046
2047 pr_warning(
2048 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2049 " reached. Keeping one slot for boot cpu."
2050 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2051
2052 disabled_cpus++;
2053 return;
2054 }
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03002055
Mike Travis3b11ce72008-12-17 15:21:39 -08002056 if (num_processors >= nr_cpu_ids) {
Mike Travis3b11ce72008-12-17 15:21:39 -08002057 int thiscpu = max + disabled_cpus;
2058
2059 pr_warning(
2060 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2061 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2062
2063 disabled_cpus++;
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03002064 return;
2065 }
2066
2067 num_processors++;
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03002068 if (apicid == boot_cpu_physical_apicid) {
2069 /*
2070 * x86_bios_cpu_apicid is required to have processors listed
2071 * in same order as logical cpu numbers. Hence the first
2072 * entry is BSP, and so on.
Yinghai Lue5fea862011-02-08 23:22:17 -08002073 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2074 * for BSP.
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03002075 */
2076 cpu = 0;
Yinghai Lue5fea862011-02-08 23:22:17 -08002077 } else
2078 cpu = cpumask_next_zero(-1, cpu_present_mask);
2079
2080 /*
2081 * Validate version
2082 */
2083 if (version == 0x0) {
2084 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2085 cpu, apicid);
2086 version = 0x10;
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03002087 }
Yinghai Lue5fea862011-02-08 23:22:17 -08002088 apic_version[apicid] = version;
2089
2090 if (version != apic_version[boot_cpu_physical_apicid]) {
2091 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2092 apic_version[boot_cpu_physical_apicid], cpu, version);
2093 }
2094
2095 physid_set(apicid, phys_cpu_present_map);
Yinghai Lue0da3362008-06-08 18:29:22 -07002096 if (apicid > max_physical_apicid)
2097 max_physical_apicid = apicid;
2098
Ingo Molnar3e5095d2009-01-27 17:07:08 +01002099#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
Tejun Heof10fcd42009-01-13 20:41:34 +09002100 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2101 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04002102#endif
Tejun Heoacb8bc02011-01-23 14:37:33 +01002103#ifdef CONFIG_X86_32
2104 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2105 apic->x86_32_early_logical_apicid(cpu);
2106#endif
Mike Travis1de88cd2008-12-16 17:34:02 -08002107 set_cpu_possible(cpu, true);
2108 set_cpu_present(cpu, true);
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03002109}
2110
Suresh Siddha0c81c742008-07-10 11:16:48 -07002111int hard_smp_processor_id(void)
2112{
2113 return read_apic_id();
2114}
Ingo Molnar1dcdd3d2009-01-28 17:55:37 +01002115
2116void default_init_apic_ldr(void)
2117{
2118 unsigned long val;
2119
2120 apic_write(APIC_DFR, APIC_DFR_VALUE);
2121 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2122 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2123 apic_write(APIC_LDR, val);
2124}
2125
Alexander Gordeevff164322012-06-07 15:15:59 +02002126int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2127 const struct cpumask *andmask,
2128 unsigned int *apicid)
Alexander Gordeev63982682012-06-05 13:23:44 +02002129{
Alexander Gordeevea3807e2012-06-14 09:49:55 +02002130 unsigned int cpu;
Alexander Gordeev63982682012-06-05 13:23:44 +02002131
2132 for_each_cpu_and(cpu, cpumask, andmask) {
2133 if (cpumask_test_cpu(cpu, cpu_online_mask))
2134 break;
2135 }
Alexander Gordeevff164322012-06-07 15:15:59 +02002136
Alexander Gordeevea3807e2012-06-14 09:49:55 +02002137 if (likely(cpu < nr_cpu_ids)) {
Alexander Gordeeva5a39152012-06-14 09:49:35 +02002138 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2139 return 0;
Alexander Gordeeva5a39152012-06-14 09:49:35 +02002140 }
Alexander Gordeevea3807e2012-06-14 09:49:55 +02002141
2142 return -EINVAL;
Alexander Gordeev63982682012-06-05 13:23:44 +02002143}
2144
Thomas Gleixner0e078e22008-01-30 13:30:20 +01002145/*
Michael S. Tsirkin1551df62012-07-15 15:56:46 +03002146 * Override the generic EOI implementation with an optimized version.
2147 * Only called during early boot when only one CPU is active and with
2148 * interrupts disabled, so we know this does not race with actual APIC driver
2149 * use.
2150 */
2151void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2152{
2153 struct apic **drv;
2154
2155 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2156 /* Should happen once for each apic */
2157 WARN_ON((*drv)->eoi_write == eoi_write);
2158 (*drv)->eoi_write = eoi_write;
2159 }
2160}
2161
2162/*
Thomas Gleixner0e078e22008-01-30 13:30:20 +01002163 * Power management
2164 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002165#ifdef CONFIG_PM
2166
2167static struct {
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04002168 /*
2169 * 'active' is true if the local APIC was enabled by us and
2170 * not the BIOS; this signifies that we are also responsible
2171 * for disabling it before entering apm/acpi suspend
2172 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002173 int active;
2174 /* r/w apic fields */
2175 unsigned int apic_id;
2176 unsigned int apic_taskpri;
2177 unsigned int apic_ldr;
2178 unsigned int apic_dfr;
2179 unsigned int apic_spiv;
2180 unsigned int apic_lvtt;
2181 unsigned int apic_lvtpc;
2182 unsigned int apic_lvt0;
2183 unsigned int apic_lvt1;
2184 unsigned int apic_lvterr;
2185 unsigned int apic_tmict;
2186 unsigned int apic_tdcr;
2187 unsigned int apic_thmr;
2188} apic_pm_state;
2189
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01002190static int lapic_suspend(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002191{
2192 unsigned long flags;
Karsten Wiesef990fff2006-12-07 02:14:11 +01002193 int maxlvt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002194
2195 if (!apic_pm_state.active)
2196 return 0;
2197
Thomas Gleixner37e650c2008-01-30 13:30:14 +01002198 maxlvt = lapic_get_maxlvt();
Karsten Wiesef990fff2006-12-07 02:14:11 +01002199
Suresh Siddha2d7a66d2008-07-11 14:24:19 -07002200 apic_pm_state.apic_id = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002201 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2202 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2203 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2204 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2205 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
Karsten Wiesef990fff2006-12-07 02:14:11 +01002206 if (maxlvt >= 4)
2207 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002208 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2209 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2210 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2211 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2212 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
Andi Kleen4efc0672009-04-28 19:07:31 +02002213#ifdef CONFIG_X86_THERMAL_VECTOR
Karsten Wiesef990fff2006-12-07 02:14:11 +01002214 if (maxlvt >= 5)
2215 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2216#endif
Cyrill Gorcunov24968cf2008-08-16 23:21:52 +04002217
Fernando Luis Vázquez Cao2b94ab22006-09-26 10:52:33 +02002218 local_irq_save(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002219 disable_local_APIC();
Suresh Siddhafc1edaf2009-04-20 13:02:27 -07002220
Suresh Siddha95a02e92012-03-30 11:47:07 -07002221 if (irq_remapping_enabled)
2222 irq_remapping_disable();
Suresh Siddhafc1edaf2009-04-20 13:02:27 -07002223
Linus Torvalds1da177e2005-04-16 15:20:36 -07002224 local_irq_restore(flags);
2225 return 0;
2226}
2227
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01002228static void lapic_resume(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002229{
2230 unsigned int l, h;
2231 unsigned long flags;
Suresh Siddha31dce142011-05-18 16:31:33 -07002232 int maxlvt;
Fenghua Yub24696b2009-03-27 14:22:44 -07002233
Linus Torvalds1da177e2005-04-16 15:20:36 -07002234 if (!apic_pm_state.active)
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01002235 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002236
Fenghua Yub24696b2009-03-27 14:22:44 -07002237 local_irq_save(flags);
Suresh Siddha95a02e92012-03-30 11:47:07 -07002238 if (irq_remapping_enabled) {
Suresh Siddha31dce142011-05-18 16:31:33 -07002239 /*
2240 * IO-APIC and PIC have their own resume routines.
2241 * We just mask them here to make sure the interrupt
2242 * subsystem is completely quiet while we enable x2apic
2243 * and interrupt-remapping.
2244 */
2245 mask_ioapic_entries();
Jacob Panb81bb372009-11-09 11:27:04 -08002246 legacy_pic->mask_all();
Fenghua Yub24696b2009-03-27 14:22:44 -07002247 }
Karsten Wiesef990fff2006-12-07 02:14:11 +01002248
Suresh Siddhafc1edaf2009-04-20 13:02:27 -07002249 if (x2apic_mode)
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002250 enable_x2apic();
Suresh Siddhacf6567f2009-03-16 17:05:00 -07002251 else {
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002252 /*
2253 * Make sure the APICBASE points to the right address
2254 *
2255 * FIXME! This will be wrong if we ever support suspend on
2256 * SMP! We'll need to do this as part of the CPU restore!
2257 */
Bryan O'Donoghuecbf28292012-04-18 17:37:39 +01002258 if (boot_cpu_data.x86 >= 6) {
2259 rdmsr(MSR_IA32_APICBASE, l, h);
2260 l &= ~MSR_IA32_APICBASE_BASE;
2261 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2262 wrmsr(MSR_IA32_APICBASE, l, h);
2263 }
Yinghai Lud5e629a2008-08-17 21:12:27 -07002264 }
Suresh Siddha6e1cb382008-07-10 11:16:58 -07002265
Fenghua Yub24696b2009-03-27 14:22:44 -07002266 maxlvt = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002267 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2268 apic_write(APIC_ID, apic_pm_state.apic_id);
2269 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2270 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2271 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2272 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2273 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2274 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002275#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
Karsten Wiesef990fff2006-12-07 02:14:11 +01002276 if (maxlvt >= 5)
2277 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2278#endif
2279 if (maxlvt >= 4)
2280 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002281 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2282 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2283 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2284 apic_write(APIC_ESR, 0);
2285 apic_read(APIC_ESR);
2286 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2287 apic_write(APIC_ESR, 0);
2288 apic_read(APIC_ESR);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002289
Suresh Siddha95a02e92012-03-30 11:47:07 -07002290 if (irq_remapping_enabled)
2291 irq_remapping_reenable(x2apic_mode);
Suresh Siddha31dce142011-05-18 16:31:33 -07002292
Linus Torvalds1da177e2005-04-16 15:20:36 -07002293 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002294}
2295
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04002296/*
2297 * This device has no shutdown method - fully functioning local APICs
2298 * are needed on every CPU up until machine_halt/restart/poweroff.
2299 */
2300
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01002301static struct syscore_ops lapic_syscore_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002302 .resume = lapic_resume,
2303 .suspend = lapic_suspend,
2304};
2305
Ashok Raje6982c62005-06-25 14:54:58 -07002306static void __cpuinit apic_pm_activate(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002307{
2308 apic_pm_state.active = 1;
2309}
2310
2311static int __init init_lapic_sysfs(void)
2312{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002313 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01002314 if (cpu_has_apic)
2315 register_syscore_ops(&lapic_syscore_ops);
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +01002316
Rafael J. Wysockif3c6ea12011-03-23 22:15:54 +01002317 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002318}
Fenghua Yub24696b2009-03-27 14:22:44 -07002319
2320/* local apic needs to resume before other devices access its registers. */
2321core_initcall(init_lapic_sysfs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002322
2323#else /* CONFIG_PM */
2324
2325static void apic_pm_activate(void) { }
2326
2327#endif /* CONFIG_PM */
2328
Yinghai Luf28c0ae2008-08-24 02:01:49 -07002329#ifdef CONFIG_X86_64
Yinghai Lue0e42142009-04-26 23:39:38 -07002330
2331static int __cpuinit apic_cluster_num(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002332{
2333 int i, clusters, zeros;
2334 unsigned id;
Yinghai Lu322850a2008-02-23 21:48:42 -08002335 u16 *bios_cpu_apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002336 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2337
Mike Travis23ca4bb2008-05-12 21:21:12 +02002338 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
Suresh Siddha376ec33f2005-05-16 21:53:32 -07002339 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002340
Mike Travis168ef542008-12-16 17:34:01 -08002341 for (i = 0; i < nr_cpu_ids; i++) {
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002342 /* are we being called early in kernel startup? */
Mike Travis693e3c52008-01-30 13:33:14 +01002343 if (bios_cpu_apicid) {
2344 id = bios_cpu_apicid[i];
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +05302345 } else if (i < nr_cpu_ids) {
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002346 if (cpu_present(i))
2347 id = per_cpu(x86_bios_cpu_apicid, i);
2348 else
2349 continue;
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +05302350 } else
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002351 break;
2352
Linus Torvalds1da177e2005-04-16 15:20:36 -07002353 if (id != BAD_APICID)
2354 __set_bit(APIC_CLUSTERID(id), clustermap);
2355 }
2356
2357 /* Problem: Partially populated chassis may not have CPUs in some of
2358 * the APIC clusters they have been allocated. Only present CPUs have
travis@sgi.com602a54a2008-01-30 13:33:21 +01002359 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2360 * Since clusters are allocated sequentially, count zeros only if
2361 * they are bounded by ones.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002362 */
2363 clusters = 0;
2364 zeros = 0;
2365 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2366 if (test_bit(i, clustermap)) {
2367 clusters += 1 + zeros;
2368 zeros = 0;
2369 } else
2370 ++zeros;
2371 }
2372
Yinghai Lue0e42142009-04-26 23:39:38 -07002373 return clusters;
2374}
2375
2376static int __cpuinitdata multi_checked;
2377static int __cpuinitdata multi;
2378
2379static int __cpuinit set_multi(const struct dmi_system_id *d)
2380{
2381 if (multi)
2382 return 0;
Cyrill Gorcunov6f0aced2009-05-01 23:54:25 +04002383 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
Yinghai Lue0e42142009-04-26 23:39:38 -07002384 multi = 1;
2385 return 0;
2386}
2387
2388static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2389 {
2390 .callback = set_multi,
2391 .ident = "IBM System Summit2",
2392 .matches = {
2393 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2394 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2395 },
2396 },
2397 {}
2398};
2399
2400static void __cpuinit dmi_check_multi(void)
2401{
2402 if (multi_checked)
2403 return;
2404
2405 dmi_check_system(multi_dmi_table);
2406 multi_checked = 1;
2407}
2408
2409/*
2410 * apic_is_clustered_box() -- Check if we can expect good TSC
2411 *
2412 * Thus far, the major user of this is IBM's Summit2 series:
2413 * Clustered boxes may have unsynced TSC problems if they are
2414 * multi-chassis.
2415 * Use DMI to check them
2416 */
2417__cpuinit int apic_is_clustered_box(void)
2418{
2419 dmi_check_multi();
2420 if (multi)
Ravikiran G Thirumalai1cb68482008-03-20 00:45:08 -07002421 return 1;
2422
Yinghai Lue0e42142009-04-26 23:39:38 -07002423 if (!is_vsmp_box())
2424 return 0;
2425
Linus Torvalds1da177e2005-04-16 15:20:36 -07002426 /*
Yinghai Lue0e42142009-04-26 23:39:38 -07002427 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2428 * not guaranteed to be synced between boards
Linus Torvalds1da177e2005-04-16 15:20:36 -07002429 */
Yinghai Lue0e42142009-04-26 23:39:38 -07002430 if (apic_cluster_num() > 1)
2431 return 1;
2432
2433 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002434}
Yinghai Luf28c0ae2008-08-24 02:01:49 -07002435#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002436
2437/*
Thomas Gleixner0e078e22008-01-30 13:30:20 +01002438 * APIC command line parameters
Linus Torvalds1da177e2005-04-16 15:20:36 -07002439 */
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002440static int __init setup_disableapic(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002441{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002442 disable_apic = 1;
Yinghai Lu9175fc02008-07-21 01:38:14 -07002443 setup_clear_cpu_cap(X86_FEATURE_APIC);
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002444 return 0;
2445}
2446early_param("disableapic", setup_disableapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002447
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002448/* same as disableapic, for compatibility */
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002449static int __init setup_nolapic(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002450{
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002451 return setup_disableapic(arg);
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002452}
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002453early_param("nolapic", setup_nolapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002454
Linus Torvalds2e7c2832007-03-23 11:32:31 -07002455static int __init parse_lapic_timer_c2_ok(char *arg)
2456{
2457 local_apic_timer_c2_ok = 1;
2458 return 0;
2459}
2460early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2461
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002462static int __init parse_disable_apic_timer(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002463{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002464 disable_apic_timer = 1;
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002465 return 0;
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002466}
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002467early_param("noapictimer", parse_disable_apic_timer);
2468
2469static int __init parse_nolapic_timer(char *arg)
2470{
2471 disable_apic_timer = 1;
2472 return 0;
2473}
2474early_param("nolapic_timer", parse_nolapic_timer);
Andi Kleen73dea472006-02-03 21:50:50 +01002475
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002476static int __init apic_set_verbosity(char *arg)
2477{
2478 if (!arg) {
2479#ifdef CONFIG_X86_64
2480 skip_ioapic_setup = 0;
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002481 return 0;
2482#endif
2483 return -EINVAL;
2484 }
2485
2486 if (strcmp("debug", arg) == 0)
2487 apic_verbosity = APIC_DEBUG;
2488 else if (strcmp("verbose", arg) == 0)
2489 apic_verbosity = APIC_VERBOSE;
2490 else {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01002491 pr_warning("APIC Verbosity level %s not recognised"
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002492 " use apic=verbose or apic=debug\n", arg);
2493 return -EINVAL;
2494 }
2495
2496 return 0;
2497}
2498early_param("apic", apic_set_verbosity);
2499
Yinghai Lu1e934dd2008-02-22 13:37:26 -08002500static int __init lapic_insert_resource(void)
2501{
2502 if (!apic_phys)
2503 return -1;
2504
2505 /* Put local APIC into the resource map. */
2506 lapic_resource.start = apic_phys;
2507 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2508 insert_resource(&iomem_resource, &lapic_resource);
2509
2510 return 0;
2511}
2512
2513/*
2514 * need call insert after e820_reserve_resources()
2515 * that is using request_resource
2516 */
2517late_initcall(lapic_insert_resource);