Dan Williams | 285f5fa | 2006-12-07 02:59:39 +0100 | [diff] [blame] | 1 | #ifndef _IOP13XX_IRQS_H_ |
| 2 | #define _IOP13XX_IRQS_H_ |
| 3 | |
| 4 | #ifndef __ASSEMBLER__ |
| 5 | #include <linux/types.h> |
| 6 | #include <asm/system.h> /* local_irq_save */ |
| 7 | #include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */ |
| 8 | |
| 9 | /* INTPND0 CP6 R0 Page 3 |
| 10 | */ |
| 11 | static inline u32 read_intpnd_0(void) |
| 12 | { |
| 13 | u32 val; |
| 14 | asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val)); |
| 15 | return val; |
| 16 | } |
| 17 | |
| 18 | /* INTPND1 CP6 R1 Page 3 |
| 19 | */ |
| 20 | static inline u32 read_intpnd_1(void) |
| 21 | { |
| 22 | u32 val; |
| 23 | asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val)); |
| 24 | return val; |
| 25 | } |
| 26 | |
| 27 | /* INTPND2 CP6 R2 Page 3 |
| 28 | */ |
| 29 | static inline u32 read_intpnd_2(void) |
| 30 | { |
| 31 | u32 val; |
| 32 | asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val)); |
| 33 | return val; |
| 34 | } |
| 35 | |
| 36 | /* INTPND3 CP6 R3 Page 3 |
| 37 | */ |
| 38 | static inline u32 read_intpnd_3(void) |
| 39 | { |
| 40 | u32 val; |
| 41 | asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); |
| 42 | return val; |
| 43 | } |
| 44 | |
| 45 | static inline void |
| 46 | iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags) |
| 47 | { |
| 48 | local_irq_save(*irq_flags); |
| 49 | *cp_flags = iop13xx_cp6_save(); |
| 50 | } |
| 51 | |
| 52 | static inline void |
| 53 | iop13xx_cp6_irq_restore(unsigned long *cp_flags, |
| 54 | unsigned long *irq_flags) |
| 55 | { |
| 56 | iop13xx_cp6_restore(*cp_flags); |
| 57 | local_irq_restore(*irq_flags); |
| 58 | } |
| 59 | #endif |
| 60 | |
| 61 | #define INTBASE 0 |
| 62 | #define INTSIZE_4 1 |
| 63 | |
| 64 | /* |
| 65 | * iop34x chipset interrupts |
| 66 | */ |
| 67 | #define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x)) |
| 68 | |
| 69 | /* |
| 70 | * On IRQ or FIQ register |
| 71 | */ |
| 72 | #define IRQ_IOP13XX_ADMA0_EOT (0) |
| 73 | #define IRQ_IOP13XX_ADMA0_EOC (1) |
| 74 | #define IRQ_IOP13XX_ADMA1_EOT (2) |
| 75 | #define IRQ_IOP13XX_ADMA1_EOC (3) |
| 76 | #define IRQ_IOP13XX_ADMA2_EOT (4) |
| 77 | #define IRQ_IOP13XX_ADMA2_EOC (5) |
| 78 | #define IRQ_IOP134_WATCHDOG (6) |
| 79 | #define IRQ_IOP13XX_RSVD_7 (7) |
| 80 | #define IRQ_IOP13XX_TIMER0 (8) |
| 81 | #define IRQ_IOP13XX_TIMER1 (9) |
| 82 | #define IRQ_IOP13XX_I2C_0 (10) |
| 83 | #define IRQ_IOP13XX_I2C_1 (11) |
| 84 | #define IRQ_IOP13XX_MSG (12) |
| 85 | #define IRQ_IOP13XX_MSGIBQ (13) |
| 86 | #define IRQ_IOP13XX_ATU_IM (14) |
| 87 | #define IRQ_IOP13XX_ATU_BIST (15) |
| 88 | #define IRQ_IOP13XX_PPMU (16) |
| 89 | #define IRQ_IOP13XX_COREPMU (17) |
| 90 | #define IRQ_IOP13XX_CORECACHE (18) |
| 91 | #define IRQ_IOP13XX_RSVD_19 (19) |
| 92 | #define IRQ_IOP13XX_RSVD_20 (20) |
| 93 | #define IRQ_IOP13XX_RSVD_21 (21) |
| 94 | #define IRQ_IOP13XX_RSVD_22 (22) |
| 95 | #define IRQ_IOP13XX_RSVD_23 (23) |
| 96 | #define IRQ_IOP13XX_XINT0 (24) |
| 97 | #define IRQ_IOP13XX_XINT1 (25) |
| 98 | #define IRQ_IOP13XX_XINT2 (26) |
| 99 | #define IRQ_IOP13XX_XINT3 (27) |
| 100 | #define IRQ_IOP13XX_XINT4 (28) |
| 101 | #define IRQ_IOP13XX_XINT5 (29) |
| 102 | #define IRQ_IOP13XX_XINT6 (30) |
| 103 | #define IRQ_IOP13XX_XINT7 (31) |
| 104 | /* IINTSRC1 bit */ |
| 105 | #define IRQ_IOP13XX_XINT8 (32) /* 0 */ |
| 106 | #define IRQ_IOP13XX_XINT9 (33) /* 1 */ |
| 107 | #define IRQ_IOP13XX_XINT10 (34) /* 2 */ |
| 108 | #define IRQ_IOP13XX_XINT11 (35) /* 3 */ |
| 109 | #define IRQ_IOP13XX_XINT12 (36) /* 4 */ |
| 110 | #define IRQ_IOP13XX_XINT13 (37) /* 5 */ |
| 111 | #define IRQ_IOP13XX_XINT14 (38) /* 6 */ |
| 112 | #define IRQ_IOP13XX_XINT15 (39) /* 7 */ |
| 113 | #define IRQ_IOP13XX_RSVD_40 (40) /* 8 */ |
| 114 | #define IRQ_IOP13XX_RSVD_41 (41) /* 9 */ |
| 115 | #define IRQ_IOP13XX_RSVD_42 (42) /* 10 */ |
| 116 | #define IRQ_IOP13XX_RSVD_43 (43) /* 11 */ |
| 117 | #define IRQ_IOP13XX_RSVD_44 (44) /* 12 */ |
| 118 | #define IRQ_IOP13XX_RSVD_45 (45) /* 13 */ |
| 119 | #define IRQ_IOP13XX_RSVD_46 (46) /* 14 */ |
| 120 | #define IRQ_IOP13XX_RSVD_47 (47) /* 15 */ |
| 121 | #define IRQ_IOP13XX_RSVD_48 (48) /* 16 */ |
| 122 | #define IRQ_IOP13XX_RSVD_49 (49) /* 17 */ |
| 123 | #define IRQ_IOP13XX_RSVD_50 (50) /* 18 */ |
| 124 | #define IRQ_IOP13XX_UART0 (51) /* 19 */ |
| 125 | #define IRQ_IOP13XX_UART1 (52) /* 20 */ |
| 126 | #define IRQ_IOP13XX_PBIE (53) /* 21 */ |
| 127 | #define IRQ_IOP13XX_ATU_CRW (54) /* 22 */ |
| 128 | #define IRQ_IOP13XX_ATU_ERR (55) /* 23 */ |
| 129 | #define IRQ_IOP13XX_MCU_ERR (56) /* 24 */ |
| 130 | #define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */ |
| 131 | #define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */ |
| 132 | #define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */ |
| 133 | #define IRQ_IOP13XX_RSVD_60 (60) /* 28 */ |
| 134 | #define IRQ_IOP13XX_RSVD_61 (61) /* 29 */ |
| 135 | #define IRQ_IOP13XX_MSG_ERR (62) /* 30 */ |
| 136 | #define IRQ_IOP13XX_RSVD_63 (63) /* 31 */ |
| 137 | /* IINTSRC2 bit */ |
| 138 | #define IRQ_IOP13XX_INTERPROC (64) /* 0 */ |
| 139 | #define IRQ_IOP13XX_RSVD_65 (65) /* 1 */ |
| 140 | #define IRQ_IOP13XX_RSVD_66 (66) /* 2 */ |
| 141 | #define IRQ_IOP13XX_RSVD_67 (67) /* 3 */ |
| 142 | #define IRQ_IOP13XX_RSVD_68 (68) /* 4 */ |
| 143 | #define IRQ_IOP13XX_RSVD_69 (69) /* 5 */ |
| 144 | #define IRQ_IOP13XX_RSVD_70 (70) /* 6 */ |
| 145 | #define IRQ_IOP13XX_RSVD_71 (71) /* 7 */ |
| 146 | #define IRQ_IOP13XX_RSVD_72 (72) /* 8 */ |
| 147 | #define IRQ_IOP13XX_RSVD_73 (73) /* 9 */ |
| 148 | #define IRQ_IOP13XX_RSVD_74 (74) /* 10 */ |
| 149 | #define IRQ_IOP13XX_RSVD_75 (75) /* 11 */ |
| 150 | #define IRQ_IOP13XX_RSVD_76 (76) /* 12 */ |
| 151 | #define IRQ_IOP13XX_RSVD_77 (77) /* 13 */ |
| 152 | #define IRQ_IOP13XX_RSVD_78 (78) /* 14 */ |
| 153 | #define IRQ_IOP13XX_RSVD_79 (79) /* 15 */ |
| 154 | #define IRQ_IOP13XX_RSVD_80 (80) /* 16 */ |
| 155 | #define IRQ_IOP13XX_RSVD_81 (81) /* 17 */ |
| 156 | #define IRQ_IOP13XX_RSVD_82 (82) /* 18 */ |
| 157 | #define IRQ_IOP13XX_RSVD_83 (83) /* 19 */ |
| 158 | #define IRQ_IOP13XX_RSVD_84 (84) /* 20 */ |
| 159 | #define IRQ_IOP13XX_RSVD_85 (85) /* 21 */ |
| 160 | #define IRQ_IOP13XX_RSVD_86 (86) /* 22 */ |
| 161 | #define IRQ_IOP13XX_RSVD_87 (87) /* 23 */ |
| 162 | #define IRQ_IOP13XX_RSVD_88 (88) /* 24 */ |
| 163 | #define IRQ_IOP13XX_RSVD_89 (89) /* 25 */ |
| 164 | #define IRQ_IOP13XX_RSVD_90 (90) /* 26 */ |
| 165 | #define IRQ_IOP13XX_RSVD_91 (91) /* 27 */ |
| 166 | #define IRQ_IOP13XX_RSVD_92 (92) /* 28 */ |
| 167 | #define IRQ_IOP13XX_RSVD_93 (93) /* 29 */ |
| 168 | #define IRQ_IOP13XX_SIB_ERR (94) /* 30 */ |
| 169 | #define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */ |
| 170 | /* IINTSRC3 bit */ |
| 171 | #define IRQ_IOP13XX_I2C_2 (96) /* 0 */ |
| 172 | #define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */ |
| 173 | #define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */ |
| 174 | #define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */ |
| 175 | #define IRQ_IOP13XX_IMU (100) /* 4 */ |
| 176 | #define IRQ_IOP13XX_RSVD_101 (101) /* 5 */ |
| 177 | #define IRQ_IOP13XX_RSVD_102 (102) /* 6 */ |
| 178 | #define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */ |
| 179 | #define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */ |
| 180 | #define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */ |
| 181 | #define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */ |
| 182 | #define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */ |
| 183 | #define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */ |
| 184 | #define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */ |
| 185 | #define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ |
| 186 | #define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ |
| 187 | #define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ |
| 188 | #define IRQ_IOP13XX_RSVD_113 (113) /* 17 */ |
| 189 | #define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ |
| 190 | #define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ |
| 191 | #define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ |
| 192 | #define IRQ_IOP13XX_RSVD_117 (117) /* 21 */ |
| 193 | #define IRQ_IOP13XX_RSVD_118 (118) /* 22 */ |
| 194 | #define IRQ_IOP13XX_RSVD_119 (119) /* 23 */ |
| 195 | #define IRQ_IOP13XX_RSVD_120 (120) /* 24 */ |
| 196 | #define IRQ_IOP13XX_RSVD_121 (121) /* 25 */ |
| 197 | #define IRQ_IOP13XX_RSVD_122 (122) /* 26 */ |
| 198 | #define IRQ_IOP13XX_RSVD_123 (123) /* 27 */ |
| 199 | #define IRQ_IOP13XX_RSVD_124 (124) /* 28 */ |
| 200 | #define IRQ_IOP13XX_RSVD_125 (125) /* 29 */ |
| 201 | #define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ |
| 202 | #define IRQ_IOP13XX_HPI (127) /* 31 */ |
| 203 | |
| 204 | #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) |
| 205 | #define NR_IRQS NR_IOP13XX_IRQS |
| 206 | |
| 207 | #endif /* _IOP13XX_IRQ_H_ */ |