Maxime Coquelin | 48a6092 | 2015-06-10 21:19:36 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) Maxime Coquelin 2015 |
| 3 | * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> |
| 4 | * License terms: GNU General Public License (GPL), version 2 |
| 5 | * |
| 6 | * Inspired by st-asc.c from STMicroelectronics (c) |
| 7 | */ |
| 8 | |
| 9 | #if defined(CONFIG_SERIAL_STM32_USART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
| 10 | #define SUPPORT_SYSRQ |
| 11 | #endif |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/serial.h> |
| 15 | #include <linux/console.h> |
| 16 | #include <linux/sysrq.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/irq.h> |
| 20 | #include <linux/tty.h> |
| 21 | #include <linux/tty_flip.h> |
| 22 | #include <linux/delay.h> |
| 23 | #include <linux/spinlock.h> |
| 24 | #include <linux/pm_runtime.h> |
| 25 | #include <linux/of.h> |
| 26 | #include <linux/of_platform.h> |
| 27 | #include <linux/serial_core.h> |
| 28 | #include <linux/clk.h> |
| 29 | |
| 30 | #define DRIVER_NAME "stm32-usart" |
| 31 | |
| 32 | /* Register offsets */ |
| 33 | #define USART_SR 0x00 |
| 34 | #define USART_DR 0x04 |
| 35 | #define USART_BRR 0x08 |
| 36 | #define USART_CR1 0x0c |
| 37 | #define USART_CR2 0x10 |
| 38 | #define USART_CR3 0x14 |
| 39 | #define USART_GTPR 0x18 |
| 40 | |
| 41 | /* USART_SR */ |
| 42 | #define USART_SR_PE BIT(0) |
| 43 | #define USART_SR_FE BIT(1) |
| 44 | #define USART_SR_NF BIT(2) |
| 45 | #define USART_SR_ORE BIT(3) |
| 46 | #define USART_SR_IDLE BIT(4) |
| 47 | #define USART_SR_RXNE BIT(5) |
| 48 | #define USART_SR_TC BIT(6) |
| 49 | #define USART_SR_TXE BIT(7) |
| 50 | #define USART_SR_LBD BIT(8) |
| 51 | #define USART_SR_CTS BIT(9) |
| 52 | #define USART_SR_ERR_MASK (USART_SR_LBD | USART_SR_ORE | \ |
| 53 | USART_SR_FE | USART_SR_PE) |
| 54 | /* Dummy bits */ |
| 55 | #define USART_SR_DUMMY_RX BIT(16) |
| 56 | |
| 57 | /* USART_DR */ |
| 58 | #define USART_DR_MASK GENMASK(8, 0) |
| 59 | |
| 60 | /* USART_BRR */ |
| 61 | #define USART_BRR_DIV_F_MASK GENMASK(3, 0) |
| 62 | #define USART_BRR_DIV_M_MASK GENMASK(15, 4) |
| 63 | #define USART_BRR_DIV_M_SHIFT 4 |
| 64 | |
| 65 | /* USART_CR1 */ |
| 66 | #define USART_CR1_SBK BIT(0) |
| 67 | #define USART_CR1_RWU BIT(1) |
| 68 | #define USART_CR1_RE BIT(2) |
| 69 | #define USART_CR1_TE BIT(3) |
| 70 | #define USART_CR1_IDLEIE BIT(4) |
| 71 | #define USART_CR1_RXNEIE BIT(5) |
| 72 | #define USART_CR1_TCIE BIT(6) |
| 73 | #define USART_CR1_TXEIE BIT(7) |
| 74 | #define USART_CR1_PEIE BIT(8) |
| 75 | #define USART_CR1_PS BIT(9) |
| 76 | #define USART_CR1_PCE BIT(10) |
| 77 | #define USART_CR1_WAKE BIT(11) |
| 78 | #define USART_CR1_M BIT(12) |
| 79 | #define USART_CR1_UE BIT(13) |
| 80 | #define USART_CR1_OVER8 BIT(15) |
| 81 | #define USART_CR1_IE_MASK GENMASK(8, 4) |
| 82 | |
| 83 | /* USART_CR2 */ |
| 84 | #define USART_CR2_ADD_MASK GENMASK(3, 0) |
| 85 | #define USART_CR2_LBDL BIT(5) |
| 86 | #define USART_CR2_LBDIE BIT(6) |
| 87 | #define USART_CR2_LBCL BIT(8) |
| 88 | #define USART_CR2_CPHA BIT(9) |
| 89 | #define USART_CR2_CPOL BIT(10) |
| 90 | #define USART_CR2_CLKEN BIT(11) |
| 91 | #define USART_CR2_STOP_2B BIT(13) |
| 92 | #define USART_CR2_STOP_MASK GENMASK(13, 12) |
| 93 | #define USART_CR2_LINEN BIT(14) |
| 94 | |
| 95 | /* USART_CR3 */ |
| 96 | #define USART_CR3_EIE BIT(0) |
| 97 | #define USART_CR3_IREN BIT(1) |
| 98 | #define USART_CR3_IRLP BIT(2) |
| 99 | #define USART_CR3_HDSEL BIT(3) |
| 100 | #define USART_CR3_NACK BIT(4) |
| 101 | #define USART_CR3_SCEN BIT(5) |
| 102 | #define USART_CR3_DMAR BIT(6) |
| 103 | #define USART_CR3_DMAT BIT(7) |
| 104 | #define USART_CR3_RTSE BIT(8) |
| 105 | #define USART_CR3_CTSE BIT(9) |
| 106 | #define USART_CR3_CTSIE BIT(10) |
| 107 | #define USART_CR3_ONEBIT BIT(11) |
| 108 | |
| 109 | /* USART_GTPR */ |
| 110 | #define USART_GTPR_PSC_MASK GENMASK(7, 0) |
| 111 | #define USART_GTPR_GT_MASK GENMASK(15, 8) |
| 112 | |
| 113 | #define DRIVER_NAME "stm32-usart" |
| 114 | #define STM32_SERIAL_NAME "ttyS" |
| 115 | #define STM32_MAX_PORTS 6 |
| 116 | |
| 117 | struct stm32_port { |
| 118 | struct uart_port port; |
| 119 | struct clk *clk; |
| 120 | bool hw_flow_control; |
| 121 | }; |
| 122 | |
| 123 | static struct stm32_port stm32_ports[STM32_MAX_PORTS]; |
| 124 | static struct uart_driver stm32_usart_driver; |
| 125 | |
| 126 | static void stm32_stop_tx(struct uart_port *port); |
| 127 | |
| 128 | static inline struct stm32_port *to_stm32_port(struct uart_port *port) |
| 129 | { |
| 130 | return container_of(port, struct stm32_port, port); |
| 131 | } |
| 132 | |
| 133 | static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) |
| 134 | { |
| 135 | u32 val; |
| 136 | |
| 137 | val = readl_relaxed(port->membase + reg); |
| 138 | val |= bits; |
| 139 | writel_relaxed(val, port->membase + reg); |
| 140 | } |
| 141 | |
| 142 | static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) |
| 143 | { |
| 144 | u32 val; |
| 145 | |
| 146 | val = readl_relaxed(port->membase + reg); |
| 147 | val &= ~bits; |
| 148 | writel_relaxed(val, port->membase + reg); |
| 149 | } |
| 150 | |
| 151 | static void stm32_receive_chars(struct uart_port *port) |
| 152 | { |
| 153 | struct tty_port *tport = &port->state->port; |
| 154 | unsigned long c; |
| 155 | u32 sr; |
| 156 | char flag; |
| 157 | |
| 158 | if (port->irq_wake) |
| 159 | pm_wakeup_event(tport->tty->dev, 0); |
| 160 | |
| 161 | while ((sr = readl_relaxed(port->membase + USART_SR)) & USART_SR_RXNE) { |
| 162 | sr |= USART_SR_DUMMY_RX; |
| 163 | c = readl_relaxed(port->membase + USART_DR); |
| 164 | flag = TTY_NORMAL; |
| 165 | port->icount.rx++; |
| 166 | |
| 167 | if (sr & USART_SR_ERR_MASK) { |
| 168 | if (sr & USART_SR_LBD) { |
| 169 | port->icount.brk++; |
| 170 | if (uart_handle_break(port)) |
| 171 | continue; |
| 172 | } else if (sr & USART_SR_ORE) { |
| 173 | port->icount.overrun++; |
| 174 | } else if (sr & USART_SR_PE) { |
| 175 | port->icount.parity++; |
| 176 | } else if (sr & USART_SR_FE) { |
| 177 | port->icount.frame++; |
| 178 | } |
| 179 | |
| 180 | sr &= port->read_status_mask; |
| 181 | |
| 182 | if (sr & USART_SR_LBD) |
| 183 | flag = TTY_BREAK; |
| 184 | else if (sr & USART_SR_PE) |
| 185 | flag = TTY_PARITY; |
| 186 | else if (sr & USART_SR_FE) |
| 187 | flag = TTY_FRAME; |
| 188 | } |
| 189 | |
| 190 | if (uart_handle_sysrq_char(port, c)) |
| 191 | continue; |
| 192 | uart_insert_char(port, sr, USART_SR_ORE, c, flag); |
| 193 | } |
| 194 | |
| 195 | spin_unlock(&port->lock); |
| 196 | tty_flip_buffer_push(tport); |
| 197 | spin_lock(&port->lock); |
| 198 | } |
| 199 | |
| 200 | static void stm32_transmit_chars(struct uart_port *port) |
| 201 | { |
| 202 | struct circ_buf *xmit = &port->state->xmit; |
| 203 | |
| 204 | if (port->x_char) { |
| 205 | writel_relaxed(port->x_char, port->membase + USART_DR); |
| 206 | port->x_char = 0; |
| 207 | port->icount.tx++; |
| 208 | return; |
| 209 | } |
| 210 | |
| 211 | if (uart_tx_stopped(port)) { |
| 212 | stm32_stop_tx(port); |
| 213 | return; |
| 214 | } |
| 215 | |
| 216 | if (uart_circ_empty(xmit)) { |
| 217 | stm32_stop_tx(port); |
| 218 | return; |
| 219 | } |
| 220 | |
| 221 | writel_relaxed(xmit->buf[xmit->tail], port->membase + USART_DR); |
| 222 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
| 223 | port->icount.tx++; |
| 224 | |
| 225 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 226 | uart_write_wakeup(port); |
| 227 | |
| 228 | if (uart_circ_empty(xmit)) |
| 229 | stm32_stop_tx(port); |
| 230 | } |
| 231 | |
| 232 | static irqreturn_t stm32_interrupt(int irq, void *ptr) |
| 233 | { |
| 234 | struct uart_port *port = ptr; |
| 235 | u32 sr; |
| 236 | |
| 237 | spin_lock(&port->lock); |
| 238 | |
| 239 | sr = readl_relaxed(port->membase + USART_SR); |
| 240 | |
| 241 | if (sr & USART_SR_RXNE) |
| 242 | stm32_receive_chars(port); |
| 243 | |
| 244 | if (sr & USART_SR_TXE) |
| 245 | stm32_transmit_chars(port); |
| 246 | |
| 247 | spin_unlock(&port->lock); |
| 248 | |
| 249 | return IRQ_HANDLED; |
| 250 | } |
| 251 | |
| 252 | static unsigned int stm32_tx_empty(struct uart_port *port) |
| 253 | { |
| 254 | return readl_relaxed(port->membase + USART_SR) & USART_SR_TXE; |
| 255 | } |
| 256 | |
| 257 | static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 258 | { |
| 259 | if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) |
| 260 | stm32_set_bits(port, USART_CR3, USART_CR3_RTSE); |
| 261 | else |
| 262 | stm32_clr_bits(port, USART_CR3, USART_CR3_RTSE); |
| 263 | } |
| 264 | |
| 265 | static unsigned int stm32_get_mctrl(struct uart_port *port) |
| 266 | { |
| 267 | /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ |
| 268 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; |
| 269 | } |
| 270 | |
| 271 | /* Transmit stop */ |
| 272 | static void stm32_stop_tx(struct uart_port *port) |
| 273 | { |
| 274 | stm32_clr_bits(port, USART_CR1, USART_CR1_TXEIE); |
| 275 | } |
| 276 | |
| 277 | /* There are probably characters waiting to be transmitted. */ |
| 278 | static void stm32_start_tx(struct uart_port *port) |
| 279 | { |
| 280 | struct circ_buf *xmit = &port->state->xmit; |
| 281 | |
| 282 | if (uart_circ_empty(xmit)) |
| 283 | return; |
| 284 | |
| 285 | stm32_set_bits(port, USART_CR1, USART_CR1_TXEIE | USART_CR1_TE); |
| 286 | } |
| 287 | |
| 288 | /* Throttle the remote when input buffer is about to overflow. */ |
| 289 | static void stm32_throttle(struct uart_port *port) |
| 290 | { |
| 291 | unsigned long flags; |
| 292 | |
| 293 | spin_lock_irqsave(&port->lock, flags); |
| 294 | stm32_clr_bits(port, USART_CR1, USART_CR1_RXNEIE); |
| 295 | spin_unlock_irqrestore(&port->lock, flags); |
| 296 | } |
| 297 | |
| 298 | /* Unthrottle the remote, the input buffer can now accept data. */ |
| 299 | static void stm32_unthrottle(struct uart_port *port) |
| 300 | { |
| 301 | unsigned long flags; |
| 302 | |
| 303 | spin_lock_irqsave(&port->lock, flags); |
| 304 | stm32_set_bits(port, USART_CR1, USART_CR1_RXNEIE); |
| 305 | spin_unlock_irqrestore(&port->lock, flags); |
| 306 | } |
| 307 | |
| 308 | /* Receive stop */ |
| 309 | static void stm32_stop_rx(struct uart_port *port) |
| 310 | { |
| 311 | stm32_clr_bits(port, USART_CR1, USART_CR1_RXNEIE); |
| 312 | } |
| 313 | |
| 314 | /* Handle breaks - ignored by us */ |
| 315 | static void stm32_break_ctl(struct uart_port *port, int break_state) |
| 316 | { |
| 317 | } |
| 318 | |
| 319 | static int stm32_startup(struct uart_port *port) |
| 320 | { |
| 321 | const char *name = to_platform_device(port->dev)->name; |
| 322 | u32 val; |
| 323 | int ret; |
| 324 | |
| 325 | ret = request_irq(port->irq, stm32_interrupt, IRQF_NO_SUSPEND, |
| 326 | name, port); |
| 327 | if (ret) |
| 328 | return ret; |
| 329 | |
| 330 | val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; |
| 331 | stm32_set_bits(port, USART_CR1, val); |
| 332 | |
| 333 | return 0; |
| 334 | } |
| 335 | |
| 336 | static void stm32_shutdown(struct uart_port *port) |
| 337 | { |
| 338 | u32 val; |
| 339 | |
| 340 | val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; |
| 341 | stm32_set_bits(port, USART_CR1, val); |
| 342 | |
| 343 | free_irq(port->irq, port); |
| 344 | } |
| 345 | |
| 346 | static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, |
| 347 | struct ktermios *old) |
| 348 | { |
| 349 | struct stm32_port *stm32_port = to_stm32_port(port); |
| 350 | unsigned int baud; |
| 351 | u32 usartdiv, mantissa, fraction, oversampling; |
| 352 | tcflag_t cflag = termios->c_cflag; |
| 353 | u32 cr1, cr2, cr3; |
| 354 | unsigned long flags; |
| 355 | |
| 356 | if (!stm32_port->hw_flow_control) |
| 357 | cflag &= ~CRTSCTS; |
| 358 | |
| 359 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); |
| 360 | |
| 361 | spin_lock_irqsave(&port->lock, flags); |
| 362 | |
| 363 | /* Stop serial port and reset value */ |
| 364 | writel_relaxed(0, port->membase + USART_CR1); |
| 365 | |
| 366 | cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE | USART_CR1_RXNEIE; |
| 367 | cr2 = 0; |
| 368 | cr3 = 0; |
| 369 | |
| 370 | if (cflag & CSTOPB) |
| 371 | cr2 |= USART_CR2_STOP_2B; |
| 372 | |
| 373 | if (cflag & PARENB) { |
| 374 | cr1 |= USART_CR1_PCE; |
| 375 | if ((cflag & CSIZE) == CS8) |
| 376 | cr1 |= USART_CR1_M; |
| 377 | } |
| 378 | |
| 379 | if (cflag & PARODD) |
| 380 | cr1 |= USART_CR1_PS; |
| 381 | |
| 382 | port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); |
| 383 | if (cflag & CRTSCTS) { |
| 384 | port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; |
| 385 | cr3 |= USART_CR3_CTSE; |
| 386 | } |
| 387 | |
| 388 | usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); |
| 389 | |
| 390 | /* |
| 391 | * The USART supports 16 or 8 times oversampling. |
| 392 | * By default we prefer 16 times oversampling, so that the receiver |
| 393 | * has a better tolerance to clock deviations. |
| 394 | * 8 times oversampling is only used to achieve higher speeds. |
| 395 | */ |
| 396 | if (usartdiv < 16) { |
| 397 | oversampling = 8; |
| 398 | stm32_set_bits(port, USART_CR1, USART_CR1_OVER8); |
| 399 | } else { |
| 400 | oversampling = 16; |
| 401 | stm32_clr_bits(port, USART_CR1, USART_CR1_OVER8); |
| 402 | } |
| 403 | |
| 404 | mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; |
| 405 | fraction = usartdiv % oversampling; |
| 406 | writel_relaxed(mantissa | fraction, port->membase + USART_BRR); |
| 407 | |
| 408 | uart_update_timeout(port, cflag, baud); |
| 409 | |
| 410 | port->read_status_mask = USART_SR_ORE; |
| 411 | if (termios->c_iflag & INPCK) |
| 412 | port->read_status_mask |= USART_SR_PE | USART_SR_FE; |
| 413 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
| 414 | port->read_status_mask |= USART_SR_LBD; |
| 415 | |
| 416 | /* Characters to ignore */ |
| 417 | port->ignore_status_mask = 0; |
| 418 | if (termios->c_iflag & IGNPAR) |
| 419 | port->ignore_status_mask = USART_SR_PE | USART_SR_FE; |
| 420 | if (termios->c_iflag & IGNBRK) { |
| 421 | port->ignore_status_mask |= USART_SR_LBD; |
| 422 | /* |
| 423 | * If we're ignoring parity and break indicators, |
| 424 | * ignore overruns too (for real raw support). |
| 425 | */ |
| 426 | if (termios->c_iflag & IGNPAR) |
| 427 | port->ignore_status_mask |= USART_SR_ORE; |
| 428 | } |
| 429 | |
| 430 | /* Ignore all characters if CREAD is not set */ |
| 431 | if ((termios->c_cflag & CREAD) == 0) |
| 432 | port->ignore_status_mask |= USART_SR_DUMMY_RX; |
| 433 | |
| 434 | writel_relaxed(cr3, port->membase + USART_CR3); |
| 435 | writel_relaxed(cr2, port->membase + USART_CR2); |
| 436 | writel_relaxed(cr1, port->membase + USART_CR1); |
| 437 | |
| 438 | spin_unlock_irqrestore(&port->lock, flags); |
| 439 | } |
| 440 | |
| 441 | static const char *stm32_type(struct uart_port *port) |
| 442 | { |
| 443 | return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; |
| 444 | } |
| 445 | |
| 446 | static void stm32_release_port(struct uart_port *port) |
| 447 | { |
| 448 | } |
| 449 | |
| 450 | static int stm32_request_port(struct uart_port *port) |
| 451 | { |
| 452 | return 0; |
| 453 | } |
| 454 | |
| 455 | static void stm32_config_port(struct uart_port *port, int flags) |
| 456 | { |
| 457 | if (flags & UART_CONFIG_TYPE) |
| 458 | port->type = PORT_STM32; |
| 459 | } |
| 460 | |
| 461 | static int |
| 462 | stm32_verify_port(struct uart_port *port, struct serial_struct *ser) |
| 463 | { |
| 464 | /* No user changeable parameters */ |
| 465 | return -EINVAL; |
| 466 | } |
| 467 | |
| 468 | static void stm32_pm(struct uart_port *port, unsigned int state, |
| 469 | unsigned int oldstate) |
| 470 | { |
| 471 | struct stm32_port *stm32port = container_of(port, |
| 472 | struct stm32_port, port); |
| 473 | unsigned long flags = 0; |
| 474 | |
| 475 | switch (state) { |
| 476 | case UART_PM_STATE_ON: |
| 477 | clk_prepare_enable(stm32port->clk); |
| 478 | break; |
| 479 | case UART_PM_STATE_OFF: |
| 480 | spin_lock_irqsave(&port->lock, flags); |
| 481 | stm32_clr_bits(port, USART_CR1, USART_CR1_UE); |
| 482 | spin_unlock_irqrestore(&port->lock, flags); |
| 483 | clk_disable_unprepare(stm32port->clk); |
| 484 | break; |
| 485 | } |
| 486 | } |
| 487 | |
| 488 | static const struct uart_ops stm32_uart_ops = { |
| 489 | .tx_empty = stm32_tx_empty, |
| 490 | .set_mctrl = stm32_set_mctrl, |
| 491 | .get_mctrl = stm32_get_mctrl, |
| 492 | .stop_tx = stm32_stop_tx, |
| 493 | .start_tx = stm32_start_tx, |
| 494 | .throttle = stm32_throttle, |
| 495 | .unthrottle = stm32_unthrottle, |
| 496 | .stop_rx = stm32_stop_rx, |
| 497 | .break_ctl = stm32_break_ctl, |
| 498 | .startup = stm32_startup, |
| 499 | .shutdown = stm32_shutdown, |
| 500 | .set_termios = stm32_set_termios, |
| 501 | .pm = stm32_pm, |
| 502 | .type = stm32_type, |
| 503 | .release_port = stm32_release_port, |
| 504 | .request_port = stm32_request_port, |
| 505 | .config_port = stm32_config_port, |
| 506 | .verify_port = stm32_verify_port, |
| 507 | }; |
| 508 | |
| 509 | static int stm32_init_port(struct stm32_port *stm32port, |
| 510 | struct platform_device *pdev) |
| 511 | { |
| 512 | struct uart_port *port = &stm32port->port; |
| 513 | struct resource *res; |
| 514 | int ret; |
| 515 | |
| 516 | port->iotype = UPIO_MEM; |
| 517 | port->flags = UPF_BOOT_AUTOCONF; |
| 518 | port->ops = &stm32_uart_ops; |
| 519 | port->dev = &pdev->dev; |
| 520 | port->irq = platform_get_irq(pdev, 0); |
| 521 | |
| 522 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 523 | port->membase = devm_ioremap_resource(&pdev->dev, res); |
| 524 | if (IS_ERR(port->membase)) |
| 525 | return PTR_ERR(port->membase); |
| 526 | port->mapbase = res->start; |
| 527 | |
| 528 | spin_lock_init(&port->lock); |
| 529 | |
| 530 | stm32port->clk = devm_clk_get(&pdev->dev, NULL); |
| 531 | if (IS_ERR(stm32port->clk)) |
| 532 | return PTR_ERR(stm32port->clk); |
| 533 | |
| 534 | /* Ensure that clk rate is correct by enabling the clk */ |
| 535 | ret = clk_prepare_enable(stm32port->clk); |
| 536 | if (ret) |
| 537 | return ret; |
| 538 | |
| 539 | stm32port->port.uartclk = clk_get_rate(stm32port->clk); |
| 540 | if (!stm32port->port.uartclk) |
| 541 | ret = -EINVAL; |
| 542 | |
| 543 | clk_disable_unprepare(stm32port->clk); |
| 544 | |
| 545 | return ret; |
| 546 | } |
| 547 | |
| 548 | static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) |
| 549 | { |
| 550 | struct device_node *np = pdev->dev.of_node; |
| 551 | int id; |
| 552 | |
| 553 | if (!np) |
| 554 | return NULL; |
| 555 | |
| 556 | id = of_alias_get_id(np, "serial"); |
| 557 | if (id < 0) |
| 558 | id = 0; |
| 559 | |
| 560 | if (WARN_ON(id >= STM32_MAX_PORTS)) |
| 561 | return NULL; |
| 562 | |
| 563 | stm32_ports[id].hw_flow_control = of_property_read_bool(np, |
| 564 | "auto-flow-control"); |
| 565 | stm32_ports[id].port.line = id; |
| 566 | return &stm32_ports[id]; |
| 567 | } |
| 568 | |
| 569 | #ifdef CONFIG_OF |
| 570 | static const struct of_device_id stm32_match[] = { |
| 571 | { .compatible = "st,stm32-usart", }, |
| 572 | { .compatible = "st,stm32-uart", }, |
| 573 | {}, |
| 574 | }; |
| 575 | |
| 576 | MODULE_DEVICE_TABLE(of, stm32_match); |
| 577 | #endif |
| 578 | |
| 579 | static int stm32_serial_probe(struct platform_device *pdev) |
| 580 | { |
| 581 | int ret; |
| 582 | struct stm32_port *stm32port; |
| 583 | |
| 584 | stm32port = stm32_of_get_stm32_port(pdev); |
| 585 | if (!stm32port) |
| 586 | return -ENODEV; |
| 587 | |
| 588 | ret = stm32_init_port(stm32port, pdev); |
| 589 | if (ret) |
| 590 | return ret; |
| 591 | |
| 592 | ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); |
| 593 | if (ret) |
| 594 | return ret; |
| 595 | |
| 596 | platform_set_drvdata(pdev, &stm32port->port); |
| 597 | |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | static int stm32_serial_remove(struct platform_device *pdev) |
| 602 | { |
| 603 | struct uart_port *port = platform_get_drvdata(pdev); |
| 604 | |
| 605 | return uart_remove_one_port(&stm32_usart_driver, port); |
| 606 | } |
| 607 | |
| 608 | |
| 609 | #ifdef CONFIG_SERIAL_STM32_CONSOLE |
| 610 | static void stm32_console_putchar(struct uart_port *port, int ch) |
| 611 | { |
| 612 | while (!(readl_relaxed(port->membase + USART_SR) & USART_SR_TXE)) |
| 613 | cpu_relax(); |
| 614 | |
| 615 | writel_relaxed(ch, port->membase + USART_DR); |
| 616 | } |
| 617 | |
| 618 | static void stm32_console_write(struct console *co, const char *s, unsigned cnt) |
| 619 | { |
| 620 | struct uart_port *port = &stm32_ports[co->index].port; |
| 621 | unsigned long flags; |
| 622 | u32 old_cr1, new_cr1; |
| 623 | int locked = 1; |
| 624 | |
| 625 | local_irq_save(flags); |
| 626 | if (port->sysrq) |
| 627 | locked = 0; |
| 628 | else if (oops_in_progress) |
| 629 | locked = spin_trylock(&port->lock); |
| 630 | else |
| 631 | spin_lock(&port->lock); |
| 632 | |
| 633 | /* Save and disable interrupts */ |
| 634 | old_cr1 = readl_relaxed(port->membase + USART_CR1); |
| 635 | new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; |
| 636 | writel_relaxed(new_cr1, port->membase + USART_CR1); |
| 637 | |
| 638 | uart_console_write(port, s, cnt, stm32_console_putchar); |
| 639 | |
| 640 | /* Restore interrupt state */ |
| 641 | writel_relaxed(old_cr1, port->membase + USART_CR1); |
| 642 | |
| 643 | if (locked) |
| 644 | spin_unlock(&port->lock); |
| 645 | local_irq_restore(flags); |
| 646 | } |
| 647 | |
| 648 | static int stm32_console_setup(struct console *co, char *options) |
| 649 | { |
| 650 | struct stm32_port *stm32port; |
| 651 | int baud = 9600; |
| 652 | int bits = 8; |
| 653 | int parity = 'n'; |
| 654 | int flow = 'n'; |
| 655 | |
| 656 | if (co->index >= STM32_MAX_PORTS) |
| 657 | return -ENODEV; |
| 658 | |
| 659 | stm32port = &stm32_ports[co->index]; |
| 660 | |
| 661 | /* |
| 662 | * This driver does not support early console initialization |
| 663 | * (use ARM early printk support instead), so we only expect |
| 664 | * this to be called during the uart port registration when the |
| 665 | * driver gets probed and the port should be mapped at that point. |
| 666 | */ |
| 667 | if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) |
| 668 | return -ENXIO; |
| 669 | |
| 670 | if (options) |
| 671 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
| 672 | |
| 673 | return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); |
| 674 | } |
| 675 | |
| 676 | static struct console stm32_console = { |
| 677 | .name = STM32_SERIAL_NAME, |
| 678 | .device = uart_console_device, |
| 679 | .write = stm32_console_write, |
| 680 | .setup = stm32_console_setup, |
| 681 | .flags = CON_PRINTBUFFER, |
| 682 | .index = -1, |
| 683 | .data = &stm32_usart_driver, |
| 684 | }; |
| 685 | |
| 686 | #define STM32_SERIAL_CONSOLE (&stm32_console) |
| 687 | |
| 688 | #else |
| 689 | #define STM32_SERIAL_CONSOLE NULL |
| 690 | #endif /* CONFIG_SERIAL_STM32_CONSOLE */ |
| 691 | |
| 692 | static struct uart_driver stm32_usart_driver = { |
| 693 | .driver_name = DRIVER_NAME, |
| 694 | .dev_name = STM32_SERIAL_NAME, |
| 695 | .major = 0, |
| 696 | .minor = 0, |
| 697 | .nr = STM32_MAX_PORTS, |
| 698 | .cons = STM32_SERIAL_CONSOLE, |
| 699 | }; |
| 700 | |
| 701 | static struct platform_driver stm32_serial_driver = { |
| 702 | .probe = stm32_serial_probe, |
| 703 | .remove = stm32_serial_remove, |
| 704 | .driver = { |
| 705 | .name = DRIVER_NAME, |
| 706 | .of_match_table = of_match_ptr(stm32_match), |
| 707 | }, |
| 708 | }; |
| 709 | |
| 710 | static int __init usart_init(void) |
| 711 | { |
| 712 | static char banner[] __initdata = "STM32 USART driver initialized"; |
| 713 | int ret; |
| 714 | |
| 715 | pr_info("%s\n", banner); |
| 716 | |
| 717 | ret = uart_register_driver(&stm32_usart_driver); |
| 718 | if (ret) |
| 719 | return ret; |
| 720 | |
| 721 | ret = platform_driver_register(&stm32_serial_driver); |
| 722 | if (ret) |
| 723 | uart_unregister_driver(&stm32_usart_driver); |
| 724 | |
| 725 | return ret; |
| 726 | } |
| 727 | |
| 728 | static void __exit usart_exit(void) |
| 729 | { |
| 730 | platform_driver_unregister(&stm32_serial_driver); |
| 731 | uart_unregister_driver(&stm32_usart_driver); |
| 732 | } |
| 733 | |
| 734 | module_init(usart_init); |
| 735 | module_exit(usart_exit); |
| 736 | |
| 737 | MODULE_ALIAS("platform:" DRIVER_NAME); |
| 738 | MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); |
| 739 | MODULE_LICENSE("GPL v2"); |