Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 1 | # |
| 2 | # EDAC Kconfig |
Doug Thompson | 4577ca5 | 2009-04-02 16:58:43 -0700 | [diff] [blame] | 3 | # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 4 | # Licensed and distributed under the GPL |
| 5 | # |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 6 | |
Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 7 | menuconfig EDAC |
GeunSik Lim | e24aca6 | 2009-06-17 16:28:02 -0700 | [diff] [blame] | 8 | bool "EDAC (Error Detection And Correction) reporting" |
Martin Schwidefsky | e25df12 | 2007-05-10 15:45:57 +0200 | [diff] [blame] | 9 | depends on HAS_IOMEM |
Andrew Morton | 4c6a1c1 | 2007-07-26 10:41:10 -0700 | [diff] [blame] | 10 | depends on X86 || PPC |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 11 | help |
| 12 | EDAC is designed to report errors in the core system. |
| 13 | These are low-level errors that are reported in the CPU or |
Douglas Thompson | 8cb2a39 | 2007-07-19 01:50:12 -0700 | [diff] [blame] | 14 | supporting chipset or other subsystems: |
| 15 | memory errors, cache errors, PCI errors, thermal throttling, etc.. |
| 16 | If unsure, select 'Y'. |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 17 | |
Tim Small | 57c432b | 2006-03-09 17:33:50 -0800 | [diff] [blame] | 18 | If this code is reporting problems on your system, please |
| 19 | see the EDAC project web pages for more information at: |
| 20 | |
| 21 | <http://bluesmoke.sourceforge.net/> |
| 22 | |
| 23 | and: |
| 24 | |
| 25 | <http://buttersideup.com/edacwiki> |
| 26 | |
| 27 | There is also a mailing list for the EDAC project, which can |
| 28 | be found via the sourceforge page. |
| 29 | |
Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 30 | if EDAC |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 31 | |
| 32 | comment "Reporting subsystems" |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 33 | |
| 34 | config EDAC_DEBUG |
| 35 | bool "Debugging" |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 36 | help |
| 37 | This turns on debugging information for the entire EDAC |
| 38 | sub-system. You can insert module with "debug_level=x", current |
| 39 | there're four debug levels (x=0,1,2,3 from low to high). |
| 40 | Usually you should select 'N'. |
| 41 | |
Borislav Petkov | 9cdeb40 | 2010-09-02 18:33:24 +0200 | [diff] [blame] | 42 | config EDAC_DECODE_MCE |
Borislav Petkov | 0d18b2e | 2009-10-02 15:31:48 +0200 | [diff] [blame] | 43 | tristate "Decode MCEs in human-readable form (only on AMD for now)" |
| 44 | depends on CPU_SUP_AMD && X86_MCE |
| 45 | default y |
| 46 | ---help--- |
| 47 | Enable this option if you want to decode Machine Check Exceptions |
| 48 | occuring on your machine in human-readable form. |
| 49 | |
| 50 | You should definitely say Y here in case you want to decode MCEs |
| 51 | which occur really early upon boot, before the module infrastructure |
| 52 | has been initialized. |
| 53 | |
Borislav Petkov | 9cdeb40 | 2010-09-02 18:33:24 +0200 | [diff] [blame] | 54 | config EDAC_MCE_INJ |
| 55 | tristate "Simple MCE injection interface over /sysfs" |
| 56 | depends on EDAC_DECODE_MCE |
| 57 | default n |
| 58 | help |
| 59 | This is a simple interface to inject MCEs over /sysfs and test |
| 60 | the MCE decoding code in EDAC. |
| 61 | |
| 62 | This is currently AMD-only. |
| 63 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 64 | config EDAC_MM_EDAC |
| 65 | tristate "Main Memory EDAC (Error Detection And Correction) reporting" |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 66 | help |
| 67 | Some systems are able to detect and correct errors in main |
| 68 | memory. EDAC can report statistics on memory error |
| 69 | detection and correction (EDAC - or commonly referred to ECC |
| 70 | errors). EDAC will also try to decode where these errors |
| 71 | occurred so that a particular failing memory module can be |
| 72 | replaced. If unsure, select 'Y'. |
| 73 | |
Mauro Carvalho Chehab | 696e409 | 2009-07-23 06:57:45 -0300 | [diff] [blame] | 74 | config EDAC_MCE |
Mauro Carvalho Chehab | 963c5ba | 2009-07-09 22:04:30 -0300 | [diff] [blame] | 75 | bool |
Mauro Carvalho Chehab | 696e409 | 2009-07-23 06:57:45 -0300 | [diff] [blame] | 76 | |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 77 | config EDAC_AMD64 |
| 78 | tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h" |
Andreas Herrmann | 23ac4ae | 2010-09-17 18:03:43 +0200 | [diff] [blame] | 79 | depends on EDAC_MM_EDAC && AMD_NB && X86_64 && PCI && EDAC_DECODE_MCE |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 80 | help |
Borislav Petkov | 3d37329 | 2009-05-20 20:18:46 +0200 | [diff] [blame] | 81 | Support for error detection and correction on the AMD 64 |
| 82 | Families of Memory Controllers (K8, F10h and F11h) |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 83 | |
| 84 | config EDAC_AMD64_ERROR_INJECTION |
Borislav Petkov | 9cdeb40 | 2010-09-02 18:33:24 +0200 | [diff] [blame] | 85 | bool "Sysfs HW Error injection facilities" |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 86 | depends on EDAC_AMD64 |
| 87 | help |
| 88 | Recent Opterons (Family 10h and later) provide for Memory Error |
| 89 | Injection into the ECC detection circuits. The amd64_edac module |
| 90 | allows the operator/user to inject Uncorrectable and Correctable |
| 91 | errors into DRAM. |
| 92 | |
| 93 | When enabled, in each of the respective memory controller directories |
| 94 | (/sys/devices/system/edac/mc/mcX), there are 3 input files: |
| 95 | |
| 96 | - inject_section (0..3, 16-byte section of 64-byte cacheline), |
| 97 | - inject_word (0..8, 16-bit word of 16-byte section), |
| 98 | - inject_ecc_vector (hex ecc vector: select bits of inject word) |
| 99 | |
| 100 | In addition, there are two control files, inject_read and inject_write, |
| 101 | which trigger the DRAM ECC Read and Write respectively. |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 102 | |
| 103 | config EDAC_AMD76X |
| 104 | tristate "AMD 76x (760, 762, 768)" |
Dave Jones | 90cbc45 | 2006-02-03 03:04:11 -0800 | [diff] [blame] | 105 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 106 | help |
| 107 | Support for error detection and correction on the AMD 76x |
| 108 | series of chipsets used with the Athlon processor. |
| 109 | |
| 110 | config EDAC_E7XXX |
| 111 | tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" |
Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 112 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 113 | help |
| 114 | Support for error detection and correction on the Intel |
| 115 | E7205, E7500, E7501 and E7505 server chipsets. |
| 116 | |
| 117 | config EDAC_E752X |
Andrei Konovalov | 5135b79 | 2008-04-29 01:03:13 -0700 | [diff] [blame] | 118 | tristate "Intel e752x (e7520, e7525, e7320) and 3100" |
Randy Dunlap | da960a6 | 2006-03-31 02:30:34 -0800 | [diff] [blame] | 119 | depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 120 | help |
| 121 | Support for error detection and correction on the Intel |
| 122 | E7520, E7525, E7320 server chipsets. |
| 123 | |
Tim Small | 5a2c675 | 2007-07-19 01:49:42 -0700 | [diff] [blame] | 124 | config EDAC_I82443BXGX |
| 125 | tristate "Intel 82443BX/GX (440BX/GX)" |
| 126 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Andrew Morton | 28f96eea | 2007-07-19 01:49:45 -0700 | [diff] [blame] | 127 | depends on BROKEN |
Tim Small | 5a2c675 | 2007-07-19 01:49:42 -0700 | [diff] [blame] | 128 | help |
| 129 | Support for error detection and correction on the Intel |
| 130 | 82443BX/GX memory controllers (440BX/GX chipsets). |
| 131 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 132 | config EDAC_I82875P |
| 133 | tristate "Intel 82875p (D82875P, E7210)" |
Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 134 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 135 | help |
| 136 | Support for error detection and correction on the Intel |
| 137 | DP82785P and E7210 server chipsets. |
| 138 | |
Ranganathan Desikan | 420390f | 2007-07-19 01:50:31 -0700 | [diff] [blame] | 139 | config EDAC_I82975X |
| 140 | tristate "Intel 82975x (D82975x)" |
| 141 | depends on EDAC_MM_EDAC && PCI && X86 |
| 142 | help |
| 143 | Support for error detection and correction on the Intel |
| 144 | DP82975x server chipsets. |
| 145 | |
Jason Uhlenkott | 535c6a5 | 2007-07-19 01:49:48 -0700 | [diff] [blame] | 146 | config EDAC_I3000 |
| 147 | tristate "Intel 3000/3010" |
Jason Uhlenkott | f5c0454 | 2008-02-07 00:15:01 -0800 | [diff] [blame] | 148 | depends on EDAC_MM_EDAC && PCI && X86 |
Jason Uhlenkott | 535c6a5 | 2007-07-19 01:49:48 -0700 | [diff] [blame] | 149 | help |
| 150 | Support for error detection and correction on the Intel |
| 151 | 3000 and 3010 server chipsets. |
| 152 | |
Jason Uhlenkott | dd8ef1d | 2009-09-23 15:57:27 -0700 | [diff] [blame] | 153 | config EDAC_I3200 |
| 154 | tristate "Intel 3200" |
| 155 | depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL |
| 156 | help |
| 157 | Support for error detection and correction on the Intel |
| 158 | 3200 and 3210 server chipsets. |
| 159 | |
Hitoshi Mitake | df8bc08c | 2008-10-29 14:00:50 -0700 | [diff] [blame] | 160 | config EDAC_X38 |
| 161 | tristate "Intel X38" |
| 162 | depends on EDAC_MM_EDAC && PCI && X86 |
| 163 | help |
| 164 | Support for error detection and correction on the Intel |
| 165 | X38 server chipsets. |
| 166 | |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 167 | config EDAC_I5400 |
| 168 | tristate "Intel 5400 (Seaburg) chipsets" |
| 169 | depends on EDAC_MM_EDAC && PCI && X86 |
| 170 | help |
| 171 | Support for error detection and correction the Intel |
| 172 | i5400 MCH chipset (Seaburg). |
| 173 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 174 | config EDAC_I7CORE |
| 175 | tristate "Intel i7 Core (Nehalem) processors" |
| 176 | depends on EDAC_MM_EDAC && PCI && X86 |
Mauro Carvalho Chehab | 696e409 | 2009-07-23 06:57:45 -0300 | [diff] [blame] | 177 | select EDAC_MCE |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 178 | help |
| 179 | Support for error detection and correction the Intel |
Mauro Carvalho Chehab | 696e409 | 2009-07-23 06:57:45 -0300 | [diff] [blame] | 180 | i7 Core (Nehalem) Integrated Memory Controller that exists on |
| 181 | newer processors like i7 Core, i7 Core Extreme, Xeon 35xx |
| 182 | and Xeon 55xx processors. |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 183 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 184 | config EDAC_I82860 |
| 185 | tristate "Intel 82860" |
Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 186 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 187 | help |
| 188 | Support for error detection and correction on the Intel |
| 189 | 82860 chipset. |
| 190 | |
| 191 | config EDAC_R82600 |
| 192 | tristate "Radisys 82600 embedded chipset" |
Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 193 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 194 | help |
| 195 | Support for error detection and correction on the Radisys |
| 196 | 82600 embedded chipset. |
| 197 | |
Eric Wollesen | eb60705 | 2007-07-19 01:49:39 -0700 | [diff] [blame] | 198 | config EDAC_I5000 |
| 199 | tristate "Intel Greencreek/Blackford chipset" |
| 200 | depends on EDAC_MM_EDAC && X86 && PCI |
| 201 | help |
| 202 | Support for error detection and correction the Intel |
| 203 | Greekcreek/Blackford chipsets. |
| 204 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 205 | config EDAC_I5100 |
| 206 | tristate "Intel San Clemente MCH" |
| 207 | depends on EDAC_MM_EDAC && X86 && PCI |
| 208 | help |
| 209 | Support for error detection and correction the Intel |
| 210 | San Clemente MCH. |
| 211 | |
Mauro Carvalho Chehab | fcaf780 | 2010-08-24 23:22:57 -0300 | [diff] [blame] | 212 | config EDAC_I7300 |
| 213 | tristate "Intel Clarksboro MCH" |
| 214 | depends on EDAC_MM_EDAC && X86 && PCI |
| 215 | help |
| 216 | Support for error detection and correction the Intel |
| 217 | Clarksboro MCH (Intel 7300 chipset). |
| 218 | |
Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 219 | config EDAC_MPC85XX |
Ira W. Snyder | b484625 | 2009-09-23 15:57:25 -0700 | [diff] [blame] | 220 | tristate "Freescale MPC83xx / MPC85xx" |
Anton Vorontsov | 1cd8521 | 2010-07-20 13:24:27 -0700 | [diff] [blame] | 221 | depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx) |
Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 222 | help |
| 223 | Support for error detection and correction on the Freescale |
Ira W. Snyder | b484625 | 2009-09-23 15:57:25 -0700 | [diff] [blame] | 224 | MPC8349, MPC8560, MPC8540, MPC8548 |
Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 225 | |
Dave Jiang | 4f4aeea | 2008-02-07 00:14:56 -0800 | [diff] [blame] | 226 | config EDAC_MV64X60 |
| 227 | tristate "Marvell MV64x60" |
| 228 | depends on EDAC_MM_EDAC && MV64X60 |
| 229 | help |
| 230 | Support for error detection and correction on the Marvell |
| 231 | MV64360 and MV64460 chipsets. |
| 232 | |
Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 233 | config EDAC_PASEMI |
| 234 | tristate "PA Semi PWRficient" |
| 235 | depends on EDAC_MM_EDAC && PCI |
Doug Thompson | ddcc305 | 2007-07-26 10:41:16 -0700 | [diff] [blame] | 236 | depends on PPC_PASEMI |
Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 237 | help |
| 238 | Support for error detection and correction on PA Semi |
| 239 | PWRficient. |
| 240 | |
Benjamin Herrenschmidt | 48764e4 | 2008-02-07 00:14:53 -0800 | [diff] [blame] | 241 | config EDAC_CELL |
| 242 | tristate "Cell Broadband Engine memory controller" |
Benjamin Krill | def434c | 2008-11-27 16:15:44 +0100 | [diff] [blame] | 243 | depends on EDAC_MM_EDAC && PPC_CELL_COMMON |
Benjamin Herrenschmidt | 48764e4 | 2008-02-07 00:14:53 -0800 | [diff] [blame] | 244 | help |
| 245 | Support for error detection and correction on the |
| 246 | Cell Broadband Engine internal memory controller |
| 247 | on platform without a hypervisor |
Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 248 | |
Grant Erickson | dba7a77 | 2009-04-02 16:58:45 -0700 | [diff] [blame] | 249 | config EDAC_PPC4XX |
| 250 | tristate "PPC4xx IBM DDR2 Memory Controller" |
| 251 | depends on EDAC_MM_EDAC && 4xx |
| 252 | help |
| 253 | This enables support for EDAC on the ECC memory used |
| 254 | with the IBM DDR2 memory controller found in various |
| 255 | PowerPC 4xx embedded processors such as the 405EX[r], |
| 256 | 440SP, 440SPe, 460EX, 460GT and 460SX. |
| 257 | |
Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 258 | config EDAC_AMD8131 |
| 259 | tristate "AMD8131 HyperTransport PCI-X Tunnel" |
Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 260 | depends on EDAC_MM_EDAC && PCI && PPC_MAPLE |
Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 261 | help |
| 262 | Support for error detection and correction on the |
| 263 | AMD8131 HyperTransport PCI-X Tunnel chip. |
Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 264 | Note, add more Kconfig dependency if it's adopted |
| 265 | on some machine other than Maple. |
Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 266 | |
Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 267 | config EDAC_AMD8111 |
| 268 | tristate "AMD8111 HyperTransport I/O Hub" |
Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 269 | depends on EDAC_MM_EDAC && PCI && PPC_MAPLE |
Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 270 | help |
| 271 | Support for error detection and correction on the |
| 272 | AMD8111 HyperTransport I/O Hub chip. |
Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 273 | Note, add more Kconfig dependency if it's adopted |
| 274 | on some machine other than Maple. |
Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 275 | |
Harry Ciao | 2a9036a | 2009-06-17 16:27:58 -0700 | [diff] [blame] | 276 | config EDAC_CPC925 |
| 277 | tristate "IBM CPC925 Memory Controller (PPC970FX)" |
| 278 | depends on EDAC_MM_EDAC && PPC64 |
| 279 | help |
| 280 | Support for error detection and correction on the |
| 281 | IBM CPC925 Bridge and Memory Controller, which is |
| 282 | a companion chip to the PowerPC 970 family of |
| 283 | processors. |
| 284 | |
Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 285 | endif # EDAC |