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srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301/*
Linus Walleij1804edd2010-09-23 09:03:40 +02002 * Copyright (C) 2009 ST-Ericsson SA
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05303 * Copyright (C) 2009 STMicroelectronics
4 *
5 * I2C master mode controller driver, used in Nomadik 8815
6 * and Ux500 platforms.
7 *
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
14 */
15#include <linux/init.h>
16#include <linux/module.h>
Alessandro Rubini23560212012-06-11 22:56:38 +020017#include <linux/amba/bus.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
srinidhi kasagar3f9900f2010-02-01 19:44:54 +053019#include <linux/interrupt.h>
20#include <linux/i2c.h>
21#include <linux/err.h>
22#include <linux/clk.h>
23#include <linux/io.h>
Rabin Vincentb0e751a2011-05-13 12:30:07 +020024#include <linux/pm_runtime.h>
Alessandro Rubiniaf97bac2012-06-11 22:56:26 +020025#include <linux/platform_data/i2c-nomadik.h>
Lee Jones43fea582012-08-06 11:09:57 +010026#include <linux/of.h>
Patrice Chotard24e9e152013-01-24 09:47:22 +010027#include <linux/pinctrl/consumer.h>
srinidhi kasagar3f9900f2010-02-01 19:44:54 +053028
29#define DRIVER_NAME "nmk-i2c"
30
31/* I2C Controller register offsets */
32#define I2C_CR (0x000)
33#define I2C_SCR (0x004)
34#define I2C_HSMCR (0x008)
35#define I2C_MCR (0x00C)
36#define I2C_TFR (0x010)
37#define I2C_SR (0x014)
38#define I2C_RFR (0x018)
39#define I2C_TFTR (0x01C)
40#define I2C_RFTR (0x020)
41#define I2C_DMAR (0x024)
42#define I2C_BRCR (0x028)
43#define I2C_IMSCR (0x02C)
44#define I2C_RISR (0x030)
45#define I2C_MISR (0x034)
46#define I2C_ICR (0x038)
47
48/* Control registers */
49#define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
50#define I2C_CR_OM (0x3 << 1) /* Operating mode */
51#define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
52#define I2C_CR_SM (0x3 << 4) /* Speed mode */
53#define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
54#define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
55#define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
56#define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
57#define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
58#define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
59#define I2C_CR_LM (0x1 << 12) /* Loopback mode */
60#define I2C_CR_FON (0x3 << 13) /* Filtering on */
61#define I2C_CR_FS (0x3 << 15) /* Force stop enable */
62
63/* Master controller (MCR) register */
64#define I2C_MCR_OP (0x1 << 0) /* Operation */
65#define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +020066#define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
srinidhi kasagar3f9900f2010-02-01 19:44:54 +053067#define I2C_MCR_SB (0x1 << 11) /* Extended address */
68#define I2C_MCR_AM (0x3 << 12) /* Address type */
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +020069#define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
70#define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
srinidhi kasagar3f9900f2010-02-01 19:44:54 +053071
72/* Status register (SR) */
73#define I2C_SR_OP (0x3 << 0) /* Operation */
74#define I2C_SR_STATUS (0x3 << 2) /* controller status */
75#define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
76#define I2C_SR_TYPE (0x3 << 7) /* Receive type */
77#define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
78
79/* Interrupt mask set/clear (IMSCR) bits */
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +020080#define I2C_IT_TXFE (0x1 << 0)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +053081#define I2C_IT_TXFNE (0x1 << 1)
82#define I2C_IT_TXFF (0x1 << 2)
83#define I2C_IT_TXFOVR (0x1 << 3)
84#define I2C_IT_RXFE (0x1 << 4)
85#define I2C_IT_RXFNF (0x1 << 5)
86#define I2C_IT_RXFF (0x1 << 6)
87#define I2C_IT_RFSR (0x1 << 16)
88#define I2C_IT_RFSE (0x1 << 17)
89#define I2C_IT_WTSR (0x1 << 18)
90#define I2C_IT_MTD (0x1 << 19)
91#define I2C_IT_STD (0x1 << 20)
92#define I2C_IT_MAL (0x1 << 24)
93#define I2C_IT_BERR (0x1 << 25)
94#define I2C_IT_MTDWS (0x1 << 28)
95
96#define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
97
98/* some bits in ICR are reserved */
99#define I2C_CLEAR_ALL_INTS 0x131f007f
100
101/* first three msb bits are reserved */
102#define IRQ_MASK(mask) (mask & 0x1fffffff)
103
104/* maximum threshold value */
105#define MAX_I2C_FIFO_THRESHOLD 15
106
Linus Walleij3a205be2013-06-10 00:00:58 +0200107/**
108 * struct i2c_vendor_data - per-vendor variations
109 * @has_mtdws: variant has the MTDWS bit
110 * @fifodepth: variant FIFO depth
111 */
112struct i2c_vendor_data {
113 bool has_mtdws;
114 u32 fifodepth;
115};
116
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530117enum i2c_status {
118 I2C_NOP,
119 I2C_ON_GOING,
120 I2C_OK,
121 I2C_ABORT
122};
123
124/* operation */
125enum i2c_operation {
126 I2C_NO_OPERATION = 0xff,
127 I2C_WRITE = 0x00,
128 I2C_READ = 0x01
129};
130
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530131/**
132 * struct i2c_nmk_client - client specific data
133 * @slave_adr: 7-bit slave address
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300134 * @count: no. bytes to be transferred
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530135 * @buffer: client data buffer
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300136 * @xfer_bytes: bytes transferred till now
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530137 * @operation: current I2C operation
138 */
139struct i2c_nmk_client {
140 unsigned short slave_adr;
141 unsigned long count;
142 unsigned char *buffer;
143 unsigned long xfer_bytes;
144 enum i2c_operation operation;
145};
146
147/**
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200148 * struct nmk_i2c_dev - private data structure of the controller.
Linus Walleij3a205be2013-06-10 00:00:58 +0200149 * @vendor: vendor data for this variant.
Alessandro Rubini23560212012-06-11 22:56:38 +0200150 * @adev: parent amba device.
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200151 * @adap: corresponding I2C adapter.
152 * @irq: interrupt line for the controller.
153 * @virtbase: virtual io memory area.
154 * @clk: hardware i2c block clock.
155 * @cfg: machine provided controller configuration.
156 * @cli: holder of client specific data.
157 * @stop: stop condition.
158 * @xfer_complete: acknowledge completion for a I2C message.
159 * @result: controller propogated result.
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200160 * @busy: Busy doing transfer.
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530161 */
162struct nmk_i2c_dev {
Linus Walleij3a205be2013-06-10 00:00:58 +0200163 struct i2c_vendor_data *vendor;
Alessandro Rubini23560212012-06-11 22:56:38 +0200164 struct amba_device *adev;
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200165 struct i2c_adapter adap;
166 int irq;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530167 void __iomem *virtbase;
168 struct clk *clk;
169 struct nmk_i2c_controller cfg;
170 struct i2c_nmk_client cli;
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200171 int stop;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530172 struct completion xfer_complete;
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200173 int result;
Jonas Aberga20d2392011-05-13 12:29:02 +0200174 bool busy;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530175};
176
177/* controller's abort causes */
178static const char *abort_causes[] = {
179 "no ack received after address transmission",
180 "no ack received during data phase",
181 "ack received after xmission of master code",
182 "master lost arbitration",
183 "slave restarts",
184 "slave reset",
185 "overflow, maxsize is 2047 bytes",
186};
187
188static inline void i2c_set_bit(void __iomem *reg, u32 mask)
189{
190 writel(readl(reg) | mask, reg);
191}
192
193static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
194{
195 writel(readl(reg) & ~mask, reg);
196}
197
198/**
199 * flush_i2c_fifo() - This function flushes the I2C FIFO
200 * @dev: private data of I2C Driver
201 *
202 * This function flushes the I2C Tx and Rx FIFOs. It returns
203 * 0 on successful flushing of FIFO
204 */
205static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
206{
207#define LOOP_ATTEMPTS 10
208 int i;
209 unsigned long timeout;
210
211 /*
212 * flush the transmit and receive FIFO. The flushing
213 * operation takes several cycles before to be completed.
214 * On the completion, the I2C internal logic clears these
215 * bits, until then no one must access Tx, Rx FIFO and
216 * should poll on these bits waiting for the completion.
217 */
218 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
219
220 for (i = 0; i < LOOP_ATTEMPTS; i++) {
Virupax Sadashivpetimathcd20e4f2011-05-13 12:29:46 +0200221 timeout = jiffies + dev->adap.timeout;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530222
223 while (!time_after(jiffies, timeout)) {
224 if ((readl(dev->virtbase + I2C_CR) &
225 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
226 return 0;
227 }
228 }
229
Alessandro Rubini23560212012-06-11 22:56:38 +0200230 dev_err(&dev->adev->dev,
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200231 "flushing operation timed out giving up after %d attempts",
232 LOOP_ATTEMPTS);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530233
234 return -ETIMEDOUT;
235}
236
237/**
238 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
239 * @dev: private data of I2C Driver
240 */
241static void disable_all_interrupts(struct nmk_i2c_dev *dev)
242{
243 u32 mask = IRQ_MASK(0);
244 writel(mask, dev->virtbase + I2C_IMSCR);
245}
246
247/**
248 * clear_all_interrupts() - Clear all interrupts of I2C Controller
249 * @dev: private data of I2C Driver
250 */
251static void clear_all_interrupts(struct nmk_i2c_dev *dev)
252{
253 u32 mask;
254 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
255 writel(mask, dev->virtbase + I2C_ICR);
256}
257
258/**
259 * init_hw() - initialize the I2C hardware
260 * @dev: private data of I2C Driver
261 */
262static int init_hw(struct nmk_i2c_dev *dev)
263{
264 int stat;
265
266 stat = flush_i2c_fifo(dev);
267 if (stat)
Jonas Aberga20d2392011-05-13 12:29:02 +0200268 goto exit;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530269
270 /* disable the controller */
271 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
272
273 disable_all_interrupts(dev);
274
275 clear_all_interrupts(dev);
276
277 dev->cli.operation = I2C_NO_OPERATION;
278
Jonas Aberga20d2392011-05-13 12:29:02 +0200279exit:
Jonas Aberga20d2392011-05-13 12:29:02 +0200280 return stat;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530281}
282
283/* enable peripheral, master mode operation */
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200284#define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530285
286/**
287 * load_i2c_mcr_reg() - load the MCR register
288 * @dev: private data of controller
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530289 * @flags: message flags
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530290 */
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530291static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530292{
293 u32 mcr = 0;
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530294 unsigned short slave_adr_3msb_bits;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530295
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530296 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
297
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530298 if (unlikely(flags & I2C_M_TEN)) {
299 /* 10-bit address transaction */
300 mcr |= GEN_MASK(2, I2C_MCR_AM, 12);
301 /*
302 * Get the top 3 bits.
303 * EA10 represents extended address in MCR. This includes
304 * the extension (MSB bits) of the 7 bit address loaded
305 * in A7
306 */
307 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
308
309 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
310 } else {
311 /* 7-bit address transaction */
312 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
313 }
314
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530315 /* start byte procedure not applied */
316 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
317
318 /* check the operation, master read/write? */
319 if (dev->cli.operation == I2C_WRITE)
320 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
321 else
322 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
323
324 /* stop or repeated start? */
325 if (dev->stop)
326 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
327 else
328 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
329
330 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
331
332 return mcr;
333}
334
335/**
336 * setup_i2c_controller() - setup the controller
337 * @dev: private data of controller
338 */
339static void setup_i2c_controller(struct nmk_i2c_dev *dev)
340{
341 u32 brcr1, brcr2;
342 u32 i2c_clk, div;
343
344 writel(0x0, dev->virtbase + I2C_CR);
345 writel(0x0, dev->virtbase + I2C_HSMCR);
346 writel(0x0, dev->virtbase + I2C_TFTR);
347 writel(0x0, dev->virtbase + I2C_RFTR);
348 writel(0x0, dev->virtbase + I2C_DMAR);
349
350 /*
351 * set the slsu:
352 *
353 * slsu defines the data setup time after SCL clock
354 * stretching in terms of i2c clk cycles. The
355 * needed setup time for the three modes are 250ns,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300356 * 100ns, 10ns respectively thus leading to the values
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530357 * of 14, 6, 2 for a 48 MHz i2c clk.
358 */
359 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
360
361 i2c_clk = clk_get_rate(dev->clk);
362
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530363 /*
364 * The spec says, in case of std. mode the divider is
365 * 2 whereas it is 3 for fast and fastplus mode of
366 * operation. TODO - high speed support.
367 */
368 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
369
370 /*
371 * generate the mask for baud rate counters. The controller
372 * has two baud rate counters. One is used for High speed
373 * operation, and the other is for std, fast mode, fast mode
374 * plus operation. Currently we do not supprt high speed mode
375 * so set brcr1 to 0.
376 */
377 brcr1 = 0 << 16;
378 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
379
380 /* set the baud rate counter register */
381 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
382
383 /*
384 * set the speed mode. Currently we support
385 * only standard and fast mode of operation
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300386 * TODO - support for fast mode plus (up to 1Mb/s)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530387 * and high speed (up to 3.4 Mb/s)
388 */
389 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
Alessandro Rubini23560212012-06-11 22:56:38 +0200390 dev_err(&dev->adev->dev,
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200391 "do not support this mode defaulting to std. mode\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530392 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
393 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
394 writel(I2C_FREQ_MODE_STANDARD << 4,
395 dev->virtbase + I2C_CR);
396 }
397 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
398
399 /* set the Tx and Rx FIFO threshold */
400 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
401 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
402}
403
404/**
405 * read_i2c() - Read from I2C client device
406 * @dev: private data of I2C Driver
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530407 * @flags: message flags
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530408 *
409 * This function reads from i2c client device when controller is in
410 * master mode. There is a completion timeout. If there is no transfer
411 * before timeout error is returned.
412 */
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530413static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530414{
415 u32 status = 0;
Wolfram Sang876ae852013-01-24 11:27:46 +0100416 u32 mcr, irq_mask;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530417 int timeout;
418
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530419 mcr = load_i2c_mcr_reg(dev, flags);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530420 writel(mcr, dev->virtbase + I2C_MCR);
421
422 /* load the current CR value */
423 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
424 dev->virtbase + I2C_CR);
425
426 /* enable the controller */
427 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
428
429 init_completion(&dev->xfer_complete);
430
431 /* enable interrupts by setting the mask */
432 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
433 I2C_IT_MAL | I2C_IT_BERR);
434
Linus Walleij3a205be2013-06-10 00:00:58 +0200435 if (dev->stop || !dev->vendor->has_mtdws)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530436 irq_mask |= I2C_IT_MTD;
437 else
438 irq_mask |= I2C_IT_MTDWS;
439
440 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
441
442 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
443 dev->virtbase + I2C_IMSCR);
444
srinidhi kasagar4b723a42011-08-09 20:17:22 +0200445 timeout = wait_for_completion_timeout(
Virupax Sadashivpetimathcd20e4f2011-05-13 12:29:46 +0200446 &dev->xfer_complete, dev->adap.timeout);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530447
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530448 if (timeout == 0) {
Virupax Sadashivpetimath0511f642011-05-13 12:30:53 +0200449 /* Controller timed out */
Alessandro Rubini23560212012-06-11 22:56:38 +0200450 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
Virupax Sadashivpetimath4cb3f532011-05-13 12:29:55 +0200451 dev->cli.slave_adr);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530452 status = -ETIMEDOUT;
453 }
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530454 return status;
455}
456
Virupax Sadashivpetimath55355342011-05-13 12:30:34 +0200457static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
458{
459 int count;
460
461 for (count = (no_bytes - 2);
462 (count > 0) &&
463 (dev->cli.count != 0);
464 count--) {
465 /* write to the Tx FIFO */
466 writeb(*dev->cli.buffer,
467 dev->virtbase + I2C_TFR);
468 dev->cli.buffer++;
469 dev->cli.count--;
470 dev->cli.xfer_bytes++;
471 }
472
473}
474
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530475/**
476 * write_i2c() - Write data to I2C client.
477 * @dev: private data of I2C Driver
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530478 * @flags: message flags
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530479 *
480 * This function writes data to I2C client
481 */
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530482static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530483{
484 u32 status = 0;
Wolfram Sang876ae852013-01-24 11:27:46 +0100485 u32 mcr, irq_mask;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530486 int timeout;
487
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530488 mcr = load_i2c_mcr_reg(dev, flags);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530489
490 writel(mcr, dev->virtbase + I2C_MCR);
491
492 /* load the current CR value */
493 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
494 dev->virtbase + I2C_CR);
495
496 /* enable the controller */
497 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
498
499 init_completion(&dev->xfer_complete);
500
501 /* enable interrupts by settings the masks */
Virupax Sadashivpetimath55355342011-05-13 12:30:34 +0200502 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
503
504 /* Fill the TX FIFO with transmit data */
505 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
506
507 if (dev->cli.count != 0)
508 irq_mask |= I2C_IT_TXFNE;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530509
510 /*
511 * check if we want to transfer a single or multiple bytes, if so
512 * set the MTDWS bit (Master Transaction Done Without Stop)
513 * to start repeated start operation
514 */
Linus Walleij3a205be2013-06-10 00:00:58 +0200515 if (dev->stop || !dev->vendor->has_mtdws)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530516 irq_mask |= I2C_IT_MTD;
517 else
518 irq_mask |= I2C_IT_MTDWS;
519
520 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
521
522 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
523 dev->virtbase + I2C_IMSCR);
524
srinidhi kasagar4b723a42011-08-09 20:17:22 +0200525 timeout = wait_for_completion_timeout(
Virupax Sadashivpetimathcd20e4f2011-05-13 12:29:46 +0200526 &dev->xfer_complete, dev->adap.timeout);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530527
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530528 if (timeout == 0) {
Virupax Sadashivpetimath0511f642011-05-13 12:30:53 +0200529 /* Controller timed out */
Alessandro Rubini23560212012-06-11 22:56:38 +0200530 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
Virupax Sadashivpetimath4cb3f532011-05-13 12:29:55 +0200531 dev->cli.slave_adr);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530532 status = -ETIMEDOUT;
533 }
534
535 return status;
536}
537
538/**
Linus Walleij82a44132011-05-13 12:31:01 +0200539 * nmk_i2c_xfer_one() - transmit a single I2C message
540 * @dev: device with a message encoded into it
541 * @flags: message flags
542 */
543static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
544{
545 int status;
546
547 if (flags & I2C_M_RD) {
548 /* read operation */
549 dev->cli.operation = I2C_READ;
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530550 status = read_i2c(dev, flags);
Linus Walleij82a44132011-05-13 12:31:01 +0200551 } else {
552 /* write operation */
553 dev->cli.operation = I2C_WRITE;
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530554 status = write_i2c(dev, flags);
Linus Walleij82a44132011-05-13 12:31:01 +0200555 }
556
557 if (status || (dev->result)) {
558 u32 i2c_sr;
559 u32 cause;
560
561 i2c_sr = readl(dev->virtbase + I2C_SR);
562 /*
563 * Check if the controller I2C operation status
564 * is set to ABORT(11b).
565 */
566 if (((i2c_sr >> 2) & 0x3) == 0x3) {
567 /* get the abort cause */
568 cause = (i2c_sr >> 4) & 0x7;
Alessandro Rubini23560212012-06-11 22:56:38 +0200569 dev_err(&dev->adev->dev, "%s\n",
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200570 cause >= ARRAY_SIZE(abort_causes) ?
Linus Walleij82a44132011-05-13 12:31:01 +0200571 "unknown reason" :
572 abort_causes[cause]);
573 }
574
575 (void) init_hw(dev);
576
577 status = status ? status : dev->result;
578 }
579
580 return status;
581}
582
583/**
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530584 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
Linus Walleij1804edd2010-09-23 09:03:40 +0200585 * @i2c_adap: Adapter pointer to the controller
586 * @msgs: Pointer to data to be written.
587 * @num_msgs: Number of messages to be executed
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530588 *
589 * This is the function called by the generic kernel i2c_transfer()
590 * or i2c_smbus...() API calls. Note that this code is protected by the
591 * semaphore set in the kernel i2c_transfer() function.
592 *
593 * NOTE:
594 * READ TRANSFER : We impose a restriction of the first message to be the
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200595 * index message for any read transaction.
596 * - a no index is coded as '0',
597 * - 2byte big endian index is coded as '3'
598 * !!! msg[0].buf holds the actual index.
599 * This is compatible with generic messages of smbus emulator
600 * that send a one byte index.
601 * eg. a I2C transation to read 2 bytes from index 0
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530602 * idx = 0;
603 * msg[0].addr = client->addr;
604 * msg[0].flags = 0x0;
605 * msg[0].len = 1;
606 * msg[0].buf = &idx;
607 *
608 * msg[1].addr = client->addr;
609 * msg[1].flags = I2C_M_RD;
610 * msg[1].len = 2;
611 * msg[1].buf = rd_buff
612 * i2c_transfer(adap, msg, 2);
613 *
614 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
615 * If you want to emulate an SMBUS write transaction put the
616 * index as first byte(or first and second) in the payload.
617 * eg. a I2C transation to write 2 bytes from index 1
618 * wr_buff[0] = 0x1;
619 * wr_buff[1] = 0x23;
620 * wr_buff[2] = 0x46;
621 * msg[0].flags = 0x0;
622 * msg[0].len = 3;
623 * msg[0].buf = wr_buff;
624 * i2c_transfer(adap, msg, 1);
625 *
626 * To read or write a block of data (multiple bytes) using SMBUS emulation
627 * please use the i2c_smbus_read_i2c_block_data()
628 * or i2c_smbus_write_i2c_block_data() API
629 */
630static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
631 struct i2c_msg msgs[], int num_msgs)
632{
633 int status;
634 int i;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530635 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200636 int j;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530637
Jonas Aberga20d2392011-05-13 12:29:02 +0200638 dev->busy = true;
639
Alessandro Rubini23560212012-06-11 22:56:38 +0200640 pm_runtime_get_sync(&dev->adev->dev);
Jonas Aberga20d2392011-05-13 12:29:02 +0200641
Philippe Begnic817315f2012-10-10 13:02:26 +0200642 status = clk_prepare_enable(dev->clk);
643 if (status) {
644 dev_err(&dev->adev->dev, "can't prepare_enable clock\n");
645 goto out_clk;
646 }
Linus Walleij8ef4f4e2010-09-23 09:03:55 +0200647
Patrice Chotard24e9e152013-01-24 09:47:22 +0100648 /* Optionaly enable pins to be muxed in and configured */
Linus Walleijac844b622013-06-05 15:38:02 +0200649 pinctrl_pm_select_default_state(&dev->adev->dev);
Patrice Chotard24e9e152013-01-24 09:47:22 +0100650
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200651 status = init_hw(dev);
652 if (status)
653 goto out;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530654
Linus Walleij82a44132011-05-13 12:31:01 +0200655 /* Attempt three times to send the message queue */
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200656 for (j = 0; j < 3; j++) {
657 /* setup the i2c controller */
658 setup_i2c_controller(dev);
Jonas Aberga20d2392011-05-13 12:29:02 +0200659
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200660 for (i = 0; i < num_msgs; i++) {
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200661 dev->cli.slave_adr = msgs[i].addr;
662 dev->cli.buffer = msgs[i].buf;
663 dev->cli.count = msgs[i].len;
664 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
665 dev->result = 0;
666
Linus Walleij82a44132011-05-13 12:31:01 +0200667 status = nmk_i2c_xfer_one(dev, msgs[i].flags);
668 if (status != 0)
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200669 break;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530670 }
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200671 if (status == 0)
672 break;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530673 }
Jonas Aberga20d2392011-05-13 12:29:02 +0200674
675out:
Philippe Begnic817315f2012-10-10 13:02:26 +0200676 clk_disable_unprepare(dev->clk);
677out_clk:
Patrice Chotard24e9e152013-01-24 09:47:22 +0100678 /* Optionally let pins go into idle state */
Linus Walleijac844b622013-06-05 15:38:02 +0200679 pinctrl_pm_select_idle_state(&dev->adev->dev);
Patrice Chotard24e9e152013-01-24 09:47:22 +0100680
Alessandro Rubini23560212012-06-11 22:56:38 +0200681 pm_runtime_put_sync(&dev->adev->dev);
Jonas Aberga20d2392011-05-13 12:29:02 +0200682
683 dev->busy = false;
Linus Walleij8ef4f4e2010-09-23 09:03:55 +0200684
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530685 /* return the no. messages processed */
686 if (status)
687 return status;
688 else
689 return num_msgs;
690}
691
692/**
693 * disable_interrupts() - disable the interrupts
694 * @dev: private data of controller
Linus Walleij1804edd2010-09-23 09:03:40 +0200695 * @irq: interrupt number
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530696 */
697static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
698{
699 irq = IRQ_MASK(irq);
700 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
701 dev->virtbase + I2C_IMSCR);
702 return 0;
703}
704
705/**
706 * i2c_irq_handler() - interrupt routine
707 * @irq: interrupt number
708 * @arg: data passed to the handler
709 *
710 * This is the interrupt handler for the i2c driver. Currently
711 * it handles the major interrupts like Rx & Tx FIFO management
712 * interrupts, master transaction interrupts, arbitration and
713 * bus error interrupts. The rest of the interrupts are treated as
714 * unhandled.
715 */
716static irqreturn_t i2c_irq_handler(int irq, void *arg)
717{
718 struct nmk_i2c_dev *dev = arg;
719 u32 tft, rft;
720 u32 count;
Wolfram Sang876ae852013-01-24 11:27:46 +0100721 u32 misr, src;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530722
723 /* load Tx FIFO and Rx FIFO threshold values */
724 tft = readl(dev->virtbase + I2C_TFTR);
725 rft = readl(dev->virtbase + I2C_RFTR);
726
727 /* read interrupt status register */
728 misr = readl(dev->virtbase + I2C_MISR);
729
730 src = __ffs(misr);
731 switch ((1 << src)) {
732
733 /* Transmit FIFO nearly empty interrupt */
734 case I2C_IT_TXFNE:
735 {
736 if (dev->cli.operation == I2C_READ) {
737 /*
738 * in read operation why do we care for writing?
739 * so disable the Transmit FIFO interrupt
740 */
741 disable_interrupts(dev, I2C_IT_TXFNE);
742 } else {
Virupax Sadashivpetimath55355342011-05-13 12:30:34 +0200743 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530744 /*
745 * if done, close the transfer by disabling the
746 * corresponding TXFNE interrupt
747 */
748 if (dev->cli.count == 0)
749 disable_interrupts(dev, I2C_IT_TXFNE);
750 }
751 }
752 break;
753
754 /*
755 * Rx FIFO nearly full interrupt.
756 * This is set when the numer of entries in Rx FIFO is
757 * greater or equal than the threshold value programmed
758 * in RFT
759 */
760 case I2C_IT_RXFNF:
761 for (count = rft; count > 0; count--) {
762 /* Read the Rx FIFO */
763 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
764 dev->cli.buffer++;
765 }
766 dev->cli.count -= rft;
767 dev->cli.xfer_bytes += rft;
768 break;
769
770 /* Rx FIFO full */
771 case I2C_IT_RXFF:
772 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
773 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
774 dev->cli.buffer++;
775 }
776 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
777 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
778 break;
779
780 /* Master Transaction Done with/without stop */
781 case I2C_IT_MTD:
782 case I2C_IT_MTDWS:
783 if (dev->cli.operation == I2C_READ) {
Rabin Vincent1df3ab12010-04-27 10:31:08 +0530784 while (!(readl(dev->virtbase + I2C_RISR)
785 & I2C_IT_RXFE)) {
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530786 if (dev->cli.count == 0)
787 break;
788 *dev->cli.buffer =
789 readb(dev->virtbase + I2C_RFR);
790 dev->cli.buffer++;
791 dev->cli.count--;
792 dev->cli.xfer_bytes++;
793 }
794 }
795
Virupax Sadashivpetimathb5e890f2011-05-13 12:30:42 +0200796 disable_all_interrupts(dev);
797 clear_all_interrupts(dev);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530798
799 if (dev->cli.count) {
Virupax Sadashivpetimath99381be2011-05-13 12:29:28 +0200800 dev->result = -EIO;
Alessandro Rubini23560212012-06-11 22:56:38 +0200801 dev_err(&dev->adev->dev,
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200802 "%lu bytes still remain to be xfered\n",
803 dev->cli.count);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530804 (void) init_hw(dev);
805 }
806 complete(&dev->xfer_complete);
807
808 break;
809
810 /* Master Arbitration lost interrupt */
811 case I2C_IT_MAL:
Virupax Sadashivpetimath99381be2011-05-13 12:29:28 +0200812 dev->result = -EIO;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530813 (void) init_hw(dev);
814
815 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
816 complete(&dev->xfer_complete);
817
818 break;
819
820 /*
821 * Bus Error interrupt.
822 * This happens when an unexpected start/stop condition occurs
823 * during the transaction.
824 */
825 case I2C_IT_BERR:
Virupax Sadashivpetimath99381be2011-05-13 12:29:28 +0200826 dev->result = -EIO;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530827 /* get the status */
828 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
829 (void) init_hw(dev);
830
831 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
832 complete(&dev->xfer_complete);
833
834 break;
835
836 /*
837 * Tx FIFO overrun interrupt.
838 * This is set when a write operation in Tx FIFO is performed and
839 * the Tx FIFO is full.
840 */
841 case I2C_IT_TXFOVR:
Virupax Sadashivpetimath99381be2011-05-13 12:29:28 +0200842 dev->result = -EIO;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530843 (void) init_hw(dev);
844
Alessandro Rubini23560212012-06-11 22:56:38 +0200845 dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530846 complete(&dev->xfer_complete);
847
848 break;
849
850 /* unhandled interrupts by this driver - TODO*/
851 case I2C_IT_TXFE:
852 case I2C_IT_TXFF:
853 case I2C_IT_RXFE:
854 case I2C_IT_RFSR:
855 case I2C_IT_RFSE:
856 case I2C_IT_WTSR:
857 case I2C_IT_STD:
Alessandro Rubini23560212012-06-11 22:56:38 +0200858 dev_err(&dev->adev->dev, "unhandled Interrupt\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530859 break;
860 default:
Alessandro Rubini23560212012-06-11 22:56:38 +0200861 dev_err(&dev->adev->dev, "spurious Interrupt..\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530862 break;
863 }
864
865 return IRQ_HANDLED;
866}
867
Jonas Aberga20d2392011-05-13 12:29:02 +0200868
869#ifdef CONFIG_PM
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200870static int nmk_i2c_suspend(struct device *dev)
Jonas Aberga20d2392011-05-13 12:29:02 +0200871{
Alessandro Rubini23560212012-06-11 22:56:38 +0200872 struct amba_device *adev = to_amba_device(dev);
873 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
Jonas Aberga20d2392011-05-13 12:29:02 +0200874
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200875 if (nmk_i2c->busy)
Jonas Aberga20d2392011-05-13 12:29:02 +0200876 return -EBUSY;
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200877
Linus Walleijac844b622013-06-05 15:38:02 +0200878 pinctrl_pm_select_sleep_state(dev);
Patrice Chotard24e9e152013-01-24 09:47:22 +0100879
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200880 return 0;
881}
882
883static int nmk_i2c_resume(struct device *dev)
884{
Patrice Chotard24e9e152013-01-24 09:47:22 +0100885 /* First go to the default state */
Linus Walleijac844b622013-06-05 15:38:02 +0200886 pinctrl_pm_select_default_state(dev);
Patrice Chotard24e9e152013-01-24 09:47:22 +0100887 /* Then let's idle the pins until the next transfer happens */
Linus Walleijac844b622013-06-05 15:38:02 +0200888 pinctrl_pm_select_idle_state(dev);
889
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200890 return 0;
Jonas Aberga20d2392011-05-13 12:29:02 +0200891}
892#else
893#define nmk_i2c_suspend NULL
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200894#define nmk_i2c_resume NULL
Jonas Aberga20d2392011-05-13 12:29:02 +0200895#endif
896
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200897/*
898 * We use noirq so that we suspend late and resume before the wakeup interrupt
899 * to ensure that we do the !pm_runtime_suspended() check in resume before
900 * there has been a regular pm runtime resume (via pm_runtime_get_sync()).
901 */
902static const struct dev_pm_ops nmk_i2c_pm = {
903 .suspend_noirq = nmk_i2c_suspend,
904 .resume_noirq = nmk_i2c_resume,
905};
906
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530907static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
908{
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530909 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530910}
911
912static const struct i2c_algorithm nmk_i2c_algo = {
913 .master_xfer = nmk_i2c_xfer,
914 .functionality = nmk_i2c_functionality
915};
916
Lee Jonesb007a3e2012-08-07 12:27:24 +0100917static struct nmk_i2c_controller u8500_i2c = {
918 /*
919 * Slave data setup time; 250ns, 100ns, and 10ns, which
920 * is 14, 6 and 2 respectively for a 48Mhz i2c clock.
921 */
922 .slsu = 0xe,
923 .tft = 1, /* Tx FIFO threshold */
924 .rft = 8, /* Rx FIFO threshold */
925 .clk_freq = 400000, /* fast mode operation */
926 .timeout = 200, /* Slave response timeout(ms) */
927 .sm = I2C_FREQ_MODE_FAST,
928};
929
Lee Jones43fea582012-08-06 11:09:57 +0100930static void nmk_i2c_of_probe(struct device_node *np,
931 struct nmk_i2c_controller *pdata)
932{
933 of_property_read_u32(np, "clock-frequency", &pdata->clk_freq);
934
935 /* This driver only supports 'standard' and 'fast' modes of operation. */
936 if (pdata->clk_freq <= 100000)
937 pdata->sm = I2C_FREQ_MODE_STANDARD;
938 else
939 pdata->sm = I2C_FREQ_MODE_FAST;
940}
941
Alessandro Rubini23560212012-06-11 22:56:38 +0200942static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530943{
944 int ret = 0;
Jingoo Han6d4028c2013-07-30 16:59:33 +0900945 struct nmk_i2c_controller *pdata = dev_get_platdata(&adev->dev);
Lee Jones43fea582012-08-06 11:09:57 +0100946 struct device_node *np = adev->dev.of_node;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530947 struct nmk_i2c_dev *dev;
948 struct i2c_adapter *adap;
Linus Walleij3a205be2013-06-10 00:00:58 +0200949 struct i2c_vendor_data *vendor = id->data;
950 u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530951
Lee Jones43fea582012-08-06 11:09:57 +0100952 if (!pdata) {
953 if (np) {
954 pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL);
955 if (!pdata) {
956 ret = -ENOMEM;
957 goto err_no_mem;
958 }
959 /* Provide the default configuration as a base. */
960 memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller));
961 nmk_i2c_of_probe(np, pdata);
962 } else
963 /* No i2c configuration found, using the default. */
964 pdata = &u8500_i2c;
965 }
Lee Jonesb007a3e2012-08-07 12:27:24 +0100966
Linus Walleij3a205be2013-06-10 00:00:58 +0200967 if (pdata->tft > max_fifo_threshold) {
968 dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
969 pdata->tft, max_fifo_threshold);
970 pdata->tft = max_fifo_threshold;
971 }
972
973 if (pdata->rft > max_fifo_threshold) {
974 dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
975 pdata->rft, max_fifo_threshold);
976 pdata->rft = max_fifo_threshold;
977 }
978
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530979 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
980 if (!dev) {
Alessandro Rubini23560212012-06-11 22:56:38 +0200981 dev_err(&adev->dev, "cannot allocate memory\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530982 ret = -ENOMEM;
983 goto err_no_mem;
984 }
Linus Walleij3a205be2013-06-10 00:00:58 +0200985 dev->vendor = vendor;
Jonas Aberga20d2392011-05-13 12:29:02 +0200986 dev->busy = false;
Alessandro Rubini23560212012-06-11 22:56:38 +0200987 dev->adev = adev;
988 amba_set_drvdata(adev, dev);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530989
Linus Walleijac844b622013-06-05 15:38:02 +0200990 /* Select default pin state */
991 pinctrl_pm_select_default_state(&adev->dev);
992 /* If possible, let's go to idle until the first transfer */
993 pinctrl_pm_select_idle_state(&adev->dev);
Patrice Chotard24e9e152013-01-24 09:47:22 +0100994
Alessandro Rubini23560212012-06-11 22:56:38 +0200995 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530996 if (!dev->virtbase) {
997 ret = -ENOMEM;
998 goto err_no_ioremap;
999 }
1000
Alessandro Rubini23560212012-06-11 22:56:38 +02001001 dev->irq = adev->irq[0];
Yong Zhang43110512011-09-21 17:28:33 +08001002 ret = request_irq(dev->irq, i2c_irq_handler, 0,
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301003 DRIVER_NAME, dev);
1004 if (ret) {
Alessandro Rubini23560212012-06-11 22:56:38 +02001005 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301006 goto err_irq;
1007 }
1008
Alessandro Rubini23560212012-06-11 22:56:38 +02001009 pm_suspend_ignore_children(&adev->dev, true);
Rabin Vincentb0e751a2011-05-13 12:30:07 +02001010
Alessandro Rubini23560212012-06-11 22:56:38 +02001011 dev->clk = clk_get(&adev->dev, NULL);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301012 if (IS_ERR(dev->clk)) {
Alessandro Rubini23560212012-06-11 22:56:38 +02001013 dev_err(&adev->dev, "could not get i2c clock\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301014 ret = PTR_ERR(dev->clk);
1015 goto err_no_clk;
1016 }
1017
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301018 adap = &dev->adap;
Lee Jones43fea582012-08-06 11:09:57 +01001019 adap->dev.of_node = np;
Alessandro Rubini23560212012-06-11 22:56:38 +02001020 adap->dev.parent = &adev->dev;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301021 adap->owner = THIS_MODULE;
1022 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1023 adap->algo = &nmk_i2c_algo;
Lee Jones98582d92012-04-17 15:52:26 +01001024 adap->timeout = msecs_to_jiffies(pdata->timeout);
Linus Walleij6d779a42010-11-30 16:59:29 +01001025 snprintf(adap->name, sizeof(adap->name),
Linus Walleijd15b8572013-06-15 22:38:14 +02001026 "Nomadik I2C at %pR", &adev->res);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301027
1028 /* fetch the controller configuration from machine */
1029 dev->cfg.clk_freq = pdata->clk_freq;
1030 dev->cfg.slsu = pdata->slsu;
1031 dev->cfg.tft = pdata->tft;
1032 dev->cfg.rft = pdata->rft;
1033 dev->cfg.sm = pdata->sm;
1034
1035 i2c_set_adapdata(adap, dev);
1036
Alessandro Rubini23560212012-06-11 22:56:38 +02001037 dev_info(&adev->dev,
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +02001038 "initialize %s on virtual base %p\n",
1039 adap->name, dev->virtbase);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301040
Linus Walleijd15b8572013-06-15 22:38:14 +02001041 ret = i2c_add_adapter(adap);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301042 if (ret) {
Alessandro Rubini23560212012-06-11 22:56:38 +02001043 dev_err(&adev->dev, "failed to add adapter\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301044 goto err_add_adap;
1045 }
1046
Alessandro Rubini23560212012-06-11 22:56:38 +02001047 pm_runtime_put(&adev->dev);
1048
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301049 return 0;
1050
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301051 err_add_adap:
1052 clk_put(dev->clk);
1053 err_no_clk:
1054 free_irq(dev->irq, dev);
1055 err_irq:
1056 iounmap(dev->virtbase);
1057 err_no_ioremap:
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301058 kfree(dev);
1059 err_no_mem:
1060
1061 return ret;
1062}
1063
Alessandro Rubini23560212012-06-11 22:56:38 +02001064static int nmk_i2c_remove(struct amba_device *adev)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301065{
Alessandro Rubini23560212012-06-11 22:56:38 +02001066 struct resource *res = &adev->res;
1067 struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301068
1069 i2c_del_adapter(&dev->adap);
1070 flush_i2c_fifo(dev);
1071 disable_all_interrupts(dev);
1072 clear_all_interrupts(dev);
1073 /* disable the controller */
1074 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
1075 free_irq(dev->irq, dev);
1076 iounmap(dev->virtbase);
Rabin Vincenta1c27672010-04-27 10:31:07 +05301077 if (res)
1078 release_mem_region(res->start, resource_size(res));
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301079 clk_put(dev->clk);
Alessandro Rubini23560212012-06-11 22:56:38 +02001080 pm_runtime_disable(&adev->dev);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301081 kfree(dev);
1082
1083 return 0;
1084}
1085
Linus Walleij3a205be2013-06-10 00:00:58 +02001086static struct i2c_vendor_data vendor_stn8815 = {
1087 .has_mtdws = false,
1088 .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */
1089};
1090
1091static struct i2c_vendor_data vendor_db8500 = {
1092 .has_mtdws = true,
1093 .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */
1094};
1095
Alessandro Rubini23560212012-06-11 22:56:38 +02001096static struct amba_id nmk_i2c_ids[] = {
1097 {
1098 .id = 0x00180024,
1099 .mask = 0x00ffffff,
Linus Walleij3a205be2013-06-10 00:00:58 +02001100 .data = &vendor_stn8815,
Alessandro Rubini23560212012-06-11 22:56:38 +02001101 },
1102 {
1103 .id = 0x00380024,
1104 .mask = 0x00ffffff,
Linus Walleij3a205be2013-06-10 00:00:58 +02001105 .data = &vendor_db8500,
Alessandro Rubini23560212012-06-11 22:56:38 +02001106 },
1107 {},
1108};
1109
1110MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
1111
1112static struct amba_driver nmk_i2c_driver = {
1113 .drv = {
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301114 .owner = THIS_MODULE,
1115 .name = DRIVER_NAME,
Rabin Vincentb0e751a2011-05-13 12:30:07 +02001116 .pm = &nmk_i2c_pm,
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301117 },
Alessandro Rubini23560212012-06-11 22:56:38 +02001118 .id_table = nmk_i2c_ids,
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301119 .probe = nmk_i2c_probe,
Alessandro Rubini23560212012-06-11 22:56:38 +02001120 .remove = nmk_i2c_remove,
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301121};
1122
1123static int __init nmk_i2c_init(void)
1124{
Alessandro Rubini23560212012-06-11 22:56:38 +02001125 return amba_driver_register(&nmk_i2c_driver);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301126}
1127
1128static void __exit nmk_i2c_exit(void)
1129{
Alessandro Rubini23560212012-06-11 22:56:38 +02001130 amba_driver_unregister(&nmk_i2c_driver);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301131}
1132
1133subsys_initcall(nmk_i2c_init);
1134module_exit(nmk_i2c_exit);
1135
1136MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1137MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1138MODULE_LICENSE("GPL");