Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 1 | /* |
Anson Huang | 848db4a | 2014-01-07 12:46:04 -0500 | [diff] [blame] | 2 | * Copyright 2013-2014 Freescale Semiconductor, Inc. |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #include <linux/clk.h> |
| 11 | #include <linux/clkdev.h> |
| 12 | #include <linux/err.h> |
| 13 | #include <linux/of.h> |
| 14 | #include <linux/of_address.h> |
| 15 | #include <linux/of_irq.h> |
| 16 | #include <dt-bindings/clock/imx6sl-clock.h> |
| 17 | |
| 18 | #include "clk.h" |
| 19 | #include "common.h" |
| 20 | |
Anson Huang | 6e6cdf6 | 2014-02-11 16:25:48 +0800 | [diff] [blame] | 21 | #define CCSR 0xc |
| 22 | #define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2) |
| 23 | #define CACRR 0x10 |
| 24 | #define CDHIPR 0x48 |
| 25 | #define BM_CDHIPR_ARM_PODF_BUSY (1 << 16) |
| 26 | #define ARM_WAIT_DIV_396M 2 |
| 27 | #define ARM_WAIT_DIV_792M 4 |
| 28 | #define ARM_WAIT_DIV_996M 6 |
| 29 | |
| 30 | #define PLL_ARM 0x0 |
| 31 | #define BM_PLL_ARM_DIV_SELECT (0x7f << 0) |
| 32 | #define BM_PLL_ARM_POWERDOWN (1 << 12) |
| 33 | #define BM_PLL_ARM_ENABLE (1 << 13) |
| 34 | #define BM_PLL_ARM_LOCK (1 << 31) |
| 35 | #define PLL_ARM_DIV_792M 66 |
| 36 | |
Liu Ying | b21c22e | 2014-01-15 14:19:34 +0800 | [diff] [blame] | 37 | static const char *step_sels[] = { "osc", "pll2_pfd2", }; |
| 38 | static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; |
| 39 | static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", }; |
| 40 | static const char *ocram_sels[] = { "periph", "ocram_alt_sels", }; |
| 41 | static const char *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", }; |
| 42 | static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; |
| 43 | static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; |
| 44 | static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; |
| 45 | static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; |
Fabio Estevam | bad66c3 | 2014-08-19 15:21:11 -0300 | [diff] [blame] | 46 | static const char *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; |
| 47 | static const char *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", }; |
Liu Ying | b21c22e | 2014-01-15 14:19:34 +0800 | [diff] [blame] | 48 | static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; |
| 49 | static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; |
| 50 | static const char *perclk_sels[] = { "ipg", "osc", }; |
Fancy Fang | e37c1ad | 2014-09-04 16:33:12 +0800 | [diff] [blame] | 51 | static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", }; |
| 52 | static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", }; |
Liu Ying | b21c22e | 2014-01-15 14:19:34 +0800 | [diff] [blame] | 53 | static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; |
| 54 | static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; |
| 55 | static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; |
| 56 | static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; |
| 57 | static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; |
| 58 | static const char *ecspi_sels[] = { "pll3_60m", "osc", }; |
| 59 | static const char *uart_sels[] = { "pll3_80m", "osc", }; |
Shawn Guo | e90f419 | 2014-09-01 14:29:53 +0800 | [diff] [blame] | 60 | static const char *lvds_sels[] = { |
| 61 | "pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video", |
| 62 | "dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1", |
| 63 | "pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy", |
| 64 | "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", |
| 65 | }; |
| 66 | static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", }; |
| 67 | static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; |
| 68 | static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; |
| 69 | static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; |
| 70 | static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; |
| 71 | static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; |
| 72 | static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; |
| 73 | static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 74 | |
| 75 | static struct clk_div_table clk_enet_ref_table[] = { |
| 76 | { .val = 0, .div = 20, }, |
| 77 | { .val = 1, .div = 10, }, |
| 78 | { .val = 2, .div = 5, }, |
| 79 | { .val = 3, .div = 4, }, |
| 80 | { } |
| 81 | }; |
| 82 | |
| 83 | static struct clk_div_table post_div_table[] = { |
| 84 | { .val = 2, .div = 1, }, |
| 85 | { .val = 1, .div = 2, }, |
| 86 | { .val = 0, .div = 4, }, |
| 87 | { } |
| 88 | }; |
| 89 | |
| 90 | static struct clk_div_table video_div_table[] = { |
| 91 | { .val = 0, .div = 1, }, |
| 92 | { .val = 1, .div = 2, }, |
| 93 | { .val = 2, .div = 1, }, |
| 94 | { .val = 3, .div = 4, }, |
| 95 | { } |
| 96 | }; |
| 97 | |
Shengjiu Wang | dbaf381 | 2014-09-09 17:13:25 +0800 | [diff] [blame] | 98 | static unsigned int share_count_ssi1; |
| 99 | static unsigned int share_count_ssi2; |
| 100 | static unsigned int share_count_ssi3; |
| 101 | |
Shawn Guo | 4e5d0d6 | 2013-11-16 22:33:16 +0800 | [diff] [blame] | 102 | static struct clk *clks[IMX6SL_CLK_END]; |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 103 | static struct clk_onecell_data clk_data; |
Anson Huang | 6e6cdf6 | 2014-02-11 16:25:48 +0800 | [diff] [blame] | 104 | static void __iomem *ccm_base; |
| 105 | static void __iomem *anatop_base; |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 106 | |
Anson Huang | 17626b7 | 2014-01-22 15:14:47 +0800 | [diff] [blame] | 107 | static const u32 clks_init_on[] __initconst = { |
| 108 | IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, |
| 109 | }; |
| 110 | |
Anson Huang | 751f7e9 | 2014-01-09 16:03:16 +0800 | [diff] [blame] | 111 | /* |
| 112 | * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken |
| 113 | * during WAIT mode entry process could cause cache memory |
| 114 | * corruption. |
| 115 | * |
| 116 | * Software workaround: |
| 117 | * To prevent this issue from occurring, software should ensure that the |
| 118 | * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before |
| 119 | * entering WAIT mode. |
| 120 | * |
| 121 | * This function will set the ARM clk to max value within the 12:5 limit. |
Anson Huang | 6e6cdf6 | 2014-02-11 16:25:48 +0800 | [diff] [blame] | 122 | * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz), |
| 123 | * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since |
| 124 | * the clk APIs can NOT be called in idle thread(may cause kernel schedule |
| 125 | * as there is sleep function in PLL wait function), so here we just slow |
| 126 | * down ARM to below freq according to previous freq: |
| 127 | * |
| 128 | * run mode wait mode |
| 129 | * 396MHz -> 132MHz; |
| 130 | * 792MHz -> 158.4MHz; |
| 131 | * 996MHz -> 142.3MHz; |
Anson Huang | 751f7e9 | 2014-01-09 16:03:16 +0800 | [diff] [blame] | 132 | */ |
Anson Huang | 6e6cdf6 | 2014-02-11 16:25:48 +0800 | [diff] [blame] | 133 | static int imx6sl_get_arm_divider_for_wait(void) |
| 134 | { |
| 135 | if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { |
| 136 | return ARM_WAIT_DIV_396M; |
| 137 | } else { |
| 138 | if ((readl_relaxed(anatop_base + PLL_ARM) & |
| 139 | BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M) |
| 140 | return ARM_WAIT_DIV_792M; |
| 141 | else |
| 142 | return ARM_WAIT_DIV_996M; |
| 143 | } |
| 144 | } |
| 145 | |
| 146 | static void imx6sl_enable_pll_arm(bool enable) |
| 147 | { |
| 148 | static u32 saved_pll_arm; |
| 149 | u32 val; |
| 150 | |
| 151 | if (enable) { |
| 152 | saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); |
| 153 | val |= BM_PLL_ARM_ENABLE; |
| 154 | val &= ~BM_PLL_ARM_POWERDOWN; |
| 155 | writel_relaxed(val, anatop_base + PLL_ARM); |
| 156 | while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) |
| 157 | ; |
| 158 | } else { |
| 159 | writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); |
| 160 | } |
| 161 | } |
| 162 | |
Anson Huang | 751f7e9 | 2014-01-09 16:03:16 +0800 | [diff] [blame] | 163 | void imx6sl_set_wait_clk(bool enter) |
| 164 | { |
Anson Huang | 6e6cdf6 | 2014-02-11 16:25:48 +0800 | [diff] [blame] | 165 | static unsigned long saved_arm_div; |
| 166 | int arm_div_for_wait = imx6sl_get_arm_divider_for_wait(); |
| 167 | |
| 168 | /* |
| 169 | * According to hardware design, arm podf change need |
| 170 | * PLL1 clock enabled. |
| 171 | */ |
| 172 | if (arm_div_for_wait == ARM_WAIT_DIV_396M) |
| 173 | imx6sl_enable_pll_arm(true); |
Anson Huang | 751f7e9 | 2014-01-09 16:03:16 +0800 | [diff] [blame] | 174 | |
| 175 | if (enter) { |
Anson Huang | 6e6cdf6 | 2014-02-11 16:25:48 +0800 | [diff] [blame] | 176 | saved_arm_div = readl_relaxed(ccm_base + CACRR); |
| 177 | writel_relaxed(arm_div_for_wait, ccm_base + CACRR); |
Anson Huang | 751f7e9 | 2014-01-09 16:03:16 +0800 | [diff] [blame] | 178 | } else { |
Anson Huang | 6e6cdf6 | 2014-02-11 16:25:48 +0800 | [diff] [blame] | 179 | writel_relaxed(saved_arm_div, ccm_base + CACRR); |
Anson Huang | 751f7e9 | 2014-01-09 16:03:16 +0800 | [diff] [blame] | 180 | } |
Anson Huang | 6e6cdf6 | 2014-02-11 16:25:48 +0800 | [diff] [blame] | 181 | while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) |
| 182 | ; |
| 183 | |
| 184 | if (arm_div_for_wait == ARM_WAIT_DIV_396M) |
| 185 | imx6sl_enable_pll_arm(false); |
Anson Huang | 751f7e9 | 2014-01-09 16:03:16 +0800 | [diff] [blame] | 186 | } |
| 187 | |
Shawn Guo | 53bb71d | 2013-05-21 09:58:51 +0800 | [diff] [blame] | 188 | static void __init imx6sl_clocks_init(struct device_node *ccm_node) |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 189 | { |
| 190 | struct device_node *np; |
| 191 | void __iomem *base; |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 192 | int i; |
Anson Huang | 848db4a | 2014-01-07 12:46:04 -0500 | [diff] [blame] | 193 | int ret; |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 194 | |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 195 | clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
| 196 | clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); |
| 197 | clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); |
Shawn Guo | e90f419 | 2014-09-01 14:29:53 +0800 | [diff] [blame] | 198 | /* Clock source from external clock via CLK1 PAD */ |
| 199 | clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 200 | |
| 201 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); |
| 202 | base = of_iomap(np, 0); |
| 203 | WARN_ON(!base); |
Anson Huang | 6e6cdf6 | 2014-02-11 16:25:48 +0800 | [diff] [blame] | 204 | anatop_base = base; |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 205 | |
Shawn Guo | e90f419 | 2014-09-01 14:29:53 +0800 | [diff] [blame] | 206 | clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
| 207 | clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
| 208 | clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
| 209 | clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
| 210 | clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
| 211 | clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
| 212 | clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
| 213 | |
| 214 | /* type name parent_name base div_mask */ |
| 215 | clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); |
| 216 | clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); |
| 217 | clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); |
| 218 | clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); |
| 219 | clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); |
| 220 | clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); |
| 221 | clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); |
| 222 | |
| 223 | clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); |
| 224 | clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); |
| 225 | clks[IMX6SL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); |
| 226 | clks[IMX6SL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); |
| 227 | clks[IMX6SL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); |
| 228 | clks[IMX6SL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); |
| 229 | clks[IMX6SL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); |
| 230 | |
| 231 | /* Do not bypass PLLs initially */ |
| 232 | clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]); |
| 233 | clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]); |
| 234 | clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]); |
| 235 | clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]); |
| 236 | clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]); |
| 237 | clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]); |
| 238 | clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]); |
| 239 | |
| 240 | clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); |
| 241 | clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); |
| 242 | clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); |
| 243 | clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); |
| 244 | clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); |
| 245 | clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); |
Shawn Guo | 69d9a3f | 2014-09-12 10:40:28 +0800 | [diff] [blame] | 246 | clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); |
Shawn Guo | e90f419 | 2014-09-01 14:29:53 +0800 | [diff] [blame] | 247 | |
| 248 | clks[IMX6SL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); |
| 249 | clks[IMX6SL_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12)); |
| 250 | clks[IMX6SL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 251 | |
| 252 | /* |
| 253 | * usbphy1 and usbphy2 are implemented as dummy gates using reserve |
| 254 | * bit 20. They are used by phy driver to keep the refcount of |
| 255 | * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be |
| 256 | * turned on during boot, and software will not need to control it |
| 257 | * anymore after that. |
| 258 | */ |
| 259 | clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); |
| 260 | clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); |
| 261 | clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); |
| 262 | clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); |
| 263 | |
| 264 | /* dev name parent_name flags reg shift width div: flags, div_table lock */ |
| 265 | clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); |
Nicolin Chen | 238fb18 | 2013-12-13 23:44:07 +0800 | [diff] [blame] | 266 | clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 267 | clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); |
| 268 | clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); |
| 269 | clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); |
| 270 | |
| 271 | /* name parent_name reg idx */ |
| 272 | clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0); |
| 273 | clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1); |
| 274 | clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2); |
| 275 | clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0); |
| 276 | clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1); |
| 277 | clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2); |
| 278 | clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3); |
| 279 | |
| 280 | /* name parent_name mult div */ |
| 281 | clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2); |
| 282 | clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); |
| 283 | clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); |
| 284 | clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); |
| 285 | |
Shawn Guo | 53bb71d | 2013-05-21 09:58:51 +0800 | [diff] [blame] | 286 | np = ccm_node; |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 287 | base = of_iomap(np, 0); |
| 288 | WARN_ON(!base); |
Anson Huang | 6e6cdf6 | 2014-02-11 16:25:48 +0800 | [diff] [blame] | 289 | ccm_base = base; |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 290 | |
Shawn Guo | 9ba64fe | 2013-10-17 10:07:09 +0800 | [diff] [blame] | 291 | /* Reuse imx6q pm code */ |
| 292 | imx6q_pm_set_ccm_base(base); |
| 293 | |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 294 | /* name reg shift width parent_names num_parents */ |
| 295 | clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); |
| 296 | clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); |
| 297 | clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels)); |
| 298 | clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels)); |
| 299 | clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); |
| 300 | clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); |
| 301 | clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); |
| 302 | clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); |
Fabio Estevam | bad66c3 | 2014-08-19 15:21:11 -0300 | [diff] [blame] | 303 | clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); |
| 304 | clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels)); |
Liu Ying | dfd8714 | 2013-07-04 17:57:17 +0800 | [diff] [blame] | 305 | clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 306 | clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 307 | clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 308 | clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
| 309 | clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 310 | clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 311 | clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| 312 | clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup); |
Fancy Fang | e37c1ad | 2014-09-04 16:33:12 +0800 | [diff] [blame] | 313 | clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels)); |
| 314 | clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels)); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 315 | clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); |
| 316 | clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); |
| 317 | clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); |
| 318 | clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels)); |
| 319 | clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); |
| 320 | clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); |
| 321 | clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); |
| 322 | clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); |
| 323 | clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); |
| 324 | |
| 325 | /* name reg shift width busy: reg, shift parent_names num_parents */ |
| 326 | clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); |
| 327 | clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); |
| 328 | |
| 329 | /* name parent_name reg shift width */ |
| 330 | clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3); |
| 331 | clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3); |
| 332 | clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3); |
| 333 | clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); |
| 334 | clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); |
| 335 | clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3); |
| 336 | clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); |
| 337 | clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); |
| 338 | clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); |
| 339 | clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); |
| 340 | clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); |
| 341 | clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); |
| 342 | clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); |
| 343 | clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); |
| 344 | clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); |
| 345 | clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); |
Liu Ying | dfd8714 | 2013-07-04 17:57:17 +0800 | [diff] [blame] | 346 | clks[IMX6SL_CLK_PERCLK] = imx_clk_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 347 | clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); |
| 348 | clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); |
| 349 | clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); |
| 350 | clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); |
| 351 | clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); |
| 352 | clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); |
Liu Ying | dfd8714 | 2013-07-04 17:57:17 +0800 | [diff] [blame] | 353 | clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 354 | clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); |
| 355 | clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); |
| 356 | clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); |
| 357 | clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3); |
| 358 | clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3); |
| 359 | clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3); |
| 360 | clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3); |
| 361 | clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); |
| 362 | clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6); |
| 363 | |
| 364 | /* name parent_name reg shift width busy: reg, shift */ |
| 365 | clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); |
| 366 | clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2); |
| 367 | clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); |
| 368 | |
| 369 | /* name parent_name reg shift */ |
| 370 | clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); |
| 371 | clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); |
| 372 | clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); |
| 373 | clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); |
Fugang Duan | 4ca2ad5 | 2014-05-19 15:46:41 +0800 | [diff] [blame] | 374 | clks[IMX6SL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 375 | clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); |
| 376 | clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); |
| 377 | clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16); |
| 378 | clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20); |
| 379 | clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22); |
| 380 | clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26); |
| 381 | clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); |
| 382 | clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); |
| 383 | clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); |
| 384 | clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); |
| 385 | clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0); |
| 386 | clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2); |
| 387 | clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4); |
| 388 | clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6); |
| 389 | clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8); |
| 390 | clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10); |
| 391 | clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); |
| 392 | clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); |
| 393 | clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); |
| 394 | clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); |
| 395 | clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); |
| 396 | clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); |
Nicolin Chen | 8962a5d | 2013-12-13 23:44:08 +0800 | [diff] [blame] | 397 | clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 398 | clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); |
Shengjiu Wang | dbaf381 | 2014-09-09 17:13:25 +0800 | [diff] [blame] | 399 | clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); |
| 400 | clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); |
| 401 | clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); |
| 402 | clks[IMX6SL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); |
| 403 | clks[IMX6SL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); |
| 404 | clks[IMX6SL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 405 | clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); |
| 406 | clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); |
| 407 | clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); |
| 408 | clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); |
| 409 | clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); |
| 410 | clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); |
| 411 | clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); |
| 412 | |
Alexander Shiyan | 229be9c | 2014-06-10 19:40:26 +0400 | [diff] [blame] | 413 | imx_check_clocks(clks, ARRAY_SIZE(clks)); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 414 | |
| 415 | clk_data.clks = clks; |
| 416 | clk_data.clk_num = ARRAY_SIZE(clks); |
| 417 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
| 418 | |
Anson Huang | 848db4a | 2014-01-07 12:46:04 -0500 | [diff] [blame] | 419 | /* Ensure the AHB clk is at 132MHz. */ |
| 420 | ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); |
| 421 | if (ret) |
| 422 | pr_warn("%s: failed to set AHB clock rate %d!\n", |
| 423 | __func__, ret); |
| 424 | |
Anson Huang | 17626b7 | 2014-01-22 15:14:47 +0800 | [diff] [blame] | 425 | /* |
| 426 | * Make sure those always on clocks are enabled to maintain the correct |
| 427 | * usecount and enabling/disabling of parent PLLs. |
| 428 | */ |
| 429 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
| 430 | clk_prepare_enable(clks[clks_init_on[i]]); |
| 431 | |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 432 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { |
| 433 | clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); |
| 434 | clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); |
| 435 | } |
| 436 | |
Nicolin Chen | 4390e62 | 2013-12-13 23:37:52 +0800 | [diff] [blame] | 437 | /* Audio-related clocks configuration */ |
| 438 | clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); |
| 439 | |
Fabio Estevam | 0783a56 | 2014-08-19 15:21:12 -0300 | [diff] [blame] | 440 | /* set PLL5 video as lcdif pix parent clock */ |
| 441 | clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL], |
| 442 | clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); |
| 443 | |
| 444 | clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], |
| 445 | clks[IMX6SL_CLK_PLL2_PFD2]); |
| 446 | |
Philipp Zabel | e7c57ec | 2014-01-29 17:10:04 +0100 | [diff] [blame] | 447 | /* Set initial power mode */ |
| 448 | imx6q_set_lpm(WAIT_CLOCKED); |
Shawn Guo | 45fe681 | 2013-05-03 11:06:46 +0800 | [diff] [blame] | 449 | } |
Shawn Guo | 53bb71d | 2013-05-21 09:58:51 +0800 | [diff] [blame] | 450 | CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); |