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David Brownella603a7f2008-10-15 12:15:39 +02001/*
2 * twl4030.h - header for TWL4030 PM and audio CODEC device
3 *
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
5 *
6 * Based on tlv320aic23.c:
7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
Balaji T Kfc7b92f2009-12-13 21:23:33 +010025#ifndef __TWL_H_
26#define __TWL_H_
David Brownella603a7f2008-10-15 12:15:39 +020027
David Brownell9d834062009-08-25 19:24:14 -070028#include <linux/types.h>
29#include <linux/input/matrix_keypad.h>
30
David Brownella603a7f2008-10-15 12:15:39 +020031/*
32 * Using the twl4030 core we address registers using a pair
33 * { module id, relative register offset }
34 * which that core then maps to the relevant
35 * { i2c slave, absolute register address }
36 *
37 * The module IDs are meaningful only to the twl4030 core code,
38 * which uses them as array indices to look up the first register
39 * address each module uses within a given i2c slave.
40 */
41
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010042/* Module IDs for similar functionalities found in twl4030/twl6030 */
43enum twl_module_ids {
44 TWL_MODULE_USB,
45 TWL_MODULE_PIH,
46 TWL_MODULE_MAIN_CHARGE,
47 TWL_MODULE_PM_MASTER,
48 TWL_MODULE_PM_RECEIVER,
49
50 TWL_MODULE_RTC,
51 TWL_MODULE_PWM,
52 TWL_MODULE_LED,
53 TWL_MODULE_SECURED_REG,
54
55 TWL_MODULE_LAST,
56};
57
58/* Modules only available in twl4030 series */
Peter Ujfalusida059ec2012-11-13 09:28:48 +010059enum twl4030_module_ids {
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010060 TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST,
Peter Ujfalusida059ec2012-11-13 09:28:48 +010061 TWL4030_MODULE_GPIO,
62 TWL4030_MODULE_INTBR,
Peter Ujfalusida059ec2012-11-13 09:28:48 +010063 TWL4030_MODULE_TEST,
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010064 TWL4030_MODULE_KEYPAD,
65
Peter Ujfalusida059ec2012-11-13 09:28:48 +010066 TWL4030_MODULE_MADC,
67 TWL4030_MODULE_INTERRUPTS,
Peter Ujfalusida059ec2012-11-13 09:28:48 +010068 TWL4030_MODULE_PRECHARGE,
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010069 TWL4030_MODULE_BACKUP,
Peter Ujfalusida059ec2012-11-13 09:28:48 +010070 TWL4030_MODULE_INT,
Ilkka Koskinen1920a612009-11-10 17:26:15 +020071
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010072 TWL5031_MODULE_ACCESSORY,
73 TWL5031_MODULE_INTERRUPTS,
74
Peter Ujfalusida059ec2012-11-13 09:28:48 +010075 TWL4030_MODULE_LAST,
76};
David Brownella603a7f2008-10-15 12:15:39 +020077
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010078/* Modules only available in twl6030 series */
79enum twl6030_module_ids {
80 TWL6030_MODULE_ID0 = TWL_MODULE_LAST,
81 TWL6030_MODULE_ID1,
82 TWL6030_MODULE_ID2,
83 TWL6030_MODULE_GPADC,
84 TWL6030_MODULE_GASGAUGE,
Balaji T Kfa0d9762010-02-19 12:39:38 +010085
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010086 TWL6030_MODULE_LAST,
87};
88
89/* Until the clients has been converted to use TWL_MODULE_LED */
90#define TWL4030_MODULE_LED TWL_MODULE_LED
Balaji T Kfc7b92f2009-12-13 21:23:33 +010091
92#define GPIO_INTR_OFFSET 0
93#define KEYPAD_INTR_OFFSET 1
94#define BCI_INTR_OFFSET 2
95#define MADC_INTR_OFFSET 3
96#define USB_INTR_OFFSET 4
Graeme Gregory6523b142011-05-12 14:27:56 +010097#define CHARGERFAULT_INTR_OFFSET 5
Balaji T Kfc7b92f2009-12-13 21:23:33 +010098#define BCI_PRES_INTR_OFFSET 9
99#define USB_PRES_INTR_OFFSET 10
100#define RTC_INTR_OFFSET 11
Balaji T Ke8deb282009-12-14 00:25:31 +0100101
102/*
103 * Offset from TWL6030_IRQ_BASE / pdata->irq_base
104 */
105#define PWR_INTR_OFFSET 0
106#define HOTDIE_INTR_OFFSET 12
107#define SMPSLDO_INTR_OFFSET 13
108#define BATDETECT_INTR_OFFSET 14
109#define SIMDETECT_INTR_OFFSET 15
110#define MMCDETECT_INTR_OFFSET 16
111#define GASGAUGE_INTR_OFFSET 17
112#define USBOTG_INTR_OFFSET 4
113#define CHARGER_INTR_OFFSET 2
114#define RSV_INTR_OFFSET 0
115
116/* INT register offsets */
117#define REG_INT_STS_A 0x00
118#define REG_INT_STS_B 0x01
119#define REG_INT_STS_C 0x02
120
121#define REG_INT_MSK_LINE_A 0x03
122#define REG_INT_MSK_LINE_B 0x04
123#define REG_INT_MSK_LINE_C 0x05
124
125#define REG_INT_MSK_STS_A 0x06
126#define REG_INT_MSK_STS_B 0x07
127#define REG_INT_MSK_STS_C 0x08
128
129/* MASK INT REG GROUP A */
130#define TWL6030_PWR_INT_MASK 0x07
131#define TWL6030_RTC_INT_MASK 0x18
132#define TWL6030_HOTDIE_INT_MASK 0x20
133#define TWL6030_SMPSLDOA_INT_MASK 0xC0
134
135/* MASK INT REG GROUP B */
136#define TWL6030_SMPSLDOB_INT_MASK 0x01
137#define TWL6030_BATDETECT_INT_MASK 0x02
138#define TWL6030_SIMDETECT_INT_MASK 0x04
139#define TWL6030_MMCDETECT_INT_MASK 0x08
140#define TWL6030_GPADC_INT_MASK 0x60
141#define TWL6030_GASGAUGE_INT_MASK 0x80
142
143/* MASK INT REG GROUP C */
144#define TWL6030_USBOTG_INT_MASK 0x0F
145#define TWL6030_CHARGER_CTRL_INT_MASK 0x10
146#define TWL6030_CHARGER_FAULT_INT_MASK 0x60
147
kishore kadiyala72f2e2c2010-09-24 17:13:20 +0000148#define TWL6030_MMCCTRL 0xEE
149#define VMMC_AUTO_OFF (0x1 << 3)
150#define SW_FC (0x1 << 2)
151#define STS_MMC 0x1
152
153#define TWL6030_CFG_INPUT_PUPD3 0xF2
154#define MMC_PU (0x1 << 3)
155#define MMC_PD (0x1 << 2)
156
Lesly A Mca972d12011-04-14 17:57:53 +0530157#define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF)
158#define TWL_SIL_REV(rev) ((rev) >> 24)
159#define TWL_SIL_5030 0x09002F
160#define TWL5030_REV_1_0 0x00
161#define TWL5030_REV_1_1 0x10
162#define TWL5030_REV_1_2 0x30
Balaji T Ke8deb282009-12-14 00:25:31 +0100163
164#define TWL4030_CLASS_ID 0x4030
165#define TWL6030_CLASS_ID 0x6030
166unsigned int twl_rev(void);
167#define GET_TWL_REV (twl_rev())
168#define TWL_CLASS_IS(class, id) \
169static inline int twl_class_is_ ##class(void) \
170{ \
171 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
172}
173
174TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
175TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
176
David Brownella603a7f2008-10-15 12:15:39 +0200177/*
David Brownella603a7f2008-10-15 12:15:39 +0200178 * Read and write several 8-bit registers at once.
David Brownella603a7f2008-10-15 12:15:39 +0200179 */
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100180int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
181int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
David Brownella603a7f2008-10-15 12:15:39 +0200182
Peter Ujfalusifbc6ae32013-01-16 14:53:59 +0100183/*
184 * Read and write single 8-bit registers
185 */
186static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) {
187 return twl_i2c_write(mod_no, &val, reg, 1);
188}
189
190static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) {
191 return twl_i2c_read(mod_no, val, reg, 1);
192}
193
Lesly A Mca972d12011-04-14 17:57:53 +0530194int twl_get_type(void);
195int twl_get_version(void);
Peter Ujfalusi2275c542012-09-10 13:46:22 +0300196int twl_get_hfclk_rate(void);
Lesly A Mca972d12011-04-14 17:57:53 +0530197
Balaji T Ke8deb282009-12-14 00:25:31 +0100198int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
199int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
200
kishore kadiyala72f2e2c2010-09-24 17:13:20 +0000201/* Card detect Configuration for MMC1 Controller on OMAP4 */
202#ifdef CONFIG_TWL4030_CORE
203int twl6030_mmc_card_detect_config(void);
204#else
205static inline int twl6030_mmc_card_detect_config(void)
206{
207 pr_debug("twl6030_mmc_card_detect_config not supported\n");
208 return 0;
209}
210#endif
211
212/* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */
213#ifdef CONFIG_TWL4030_CORE
214int twl6030_mmc_card_detect(struct device *dev, int slot);
215#else
216static inline int twl6030_mmc_card_detect(struct device *dev, int slot)
217{
218 pr_debug("Call back twl6030_mmc_card_detect not supported\n");
219 return -EIO;
220}
221#endif
David Brownella603a7f2008-10-15 12:15:39 +0200222/*----------------------------------------------------------------------*/
223
224/*
225 * NOTE: at up to 1024 registers, this is a big chip.
226 *
227 * Avoid putting register declarations in this file, instead of into
228 * a driver-private file, unless some of the registers in a block
229 * need to be shared with other drivers. One example is blocks that
230 * have Secondary IRQ Handler (SIH) registers.
231 */
232
233#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
234#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
235#define TWL4030_SIH_CTRL_COR_MASK BIT(2)
236
237/*----------------------------------------------------------------------*/
238
239/*
240 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
241 */
242
243#define REG_GPIODATAIN1 0x0
244#define REG_GPIODATAIN2 0x1
245#define REG_GPIODATAIN3 0x2
246#define REG_GPIODATADIR1 0x3
247#define REG_GPIODATADIR2 0x4
248#define REG_GPIODATADIR3 0x5
249#define REG_GPIODATAOUT1 0x6
250#define REG_GPIODATAOUT2 0x7
251#define REG_GPIODATAOUT3 0x8
252#define REG_CLEARGPIODATAOUT1 0x9
253#define REG_CLEARGPIODATAOUT2 0xA
254#define REG_CLEARGPIODATAOUT3 0xB
255#define REG_SETGPIODATAOUT1 0xC
256#define REG_SETGPIODATAOUT2 0xD
257#define REG_SETGPIODATAOUT3 0xE
258#define REG_GPIO_DEBEN1 0xF
259#define REG_GPIO_DEBEN2 0x10
260#define REG_GPIO_DEBEN3 0x11
261#define REG_GPIO_CTRL 0x12
262#define REG_GPIOPUPDCTR1 0x13
263#define REG_GPIOPUPDCTR2 0x14
264#define REG_GPIOPUPDCTR3 0x15
265#define REG_GPIOPUPDCTR4 0x16
266#define REG_GPIOPUPDCTR5 0x17
267#define REG_GPIO_ISR1A 0x19
268#define REG_GPIO_ISR2A 0x1A
269#define REG_GPIO_ISR3A 0x1B
270#define REG_GPIO_IMR1A 0x1C
271#define REG_GPIO_IMR2A 0x1D
272#define REG_GPIO_IMR3A 0x1E
273#define REG_GPIO_ISR1B 0x1F
274#define REG_GPIO_ISR2B 0x20
275#define REG_GPIO_ISR3B 0x21
276#define REG_GPIO_IMR1B 0x22
277#define REG_GPIO_IMR2B 0x23
278#define REG_GPIO_IMR3B 0x24
279#define REG_GPIO_EDR1 0x28
280#define REG_GPIO_EDR2 0x29
281#define REG_GPIO_EDR3 0x2A
282#define REG_GPIO_EDR4 0x2B
283#define REG_GPIO_EDR5 0x2C
284#define REG_GPIO_SIH_CTRL 0x2D
285
286/* Up to 18 signals are available as GPIOs, when their
287 * pins are not assigned to another use (such as ULPI/USB).
288 */
289#define TWL4030_GPIO_MAX 18
290
291/*----------------------------------------------------------------------*/
292
Moiz Sonasatha29aaf52010-02-16 18:57:21 -0600293/*Interface Bit Register (INTBR) offsets
294 *(Use TWL_4030_MODULE_INTBR)
295 */
296
Lesly A Mca972d12011-04-14 17:57:53 +0530297#define REG_IDCODE_7_0 0x00
298#define REG_IDCODE_15_8 0x01
299#define REG_IDCODE_16_23 0x02
300#define REG_IDCODE_31_24 0x03
Moiz Sonasatha29aaf52010-02-16 18:57:21 -0600301#define REG_GPPUPDCTR1 0x0F
Lesly A Mca972d12011-04-14 17:57:53 +0530302#define REG_UNLOCK_TEST_REG 0x12
Moiz Sonasatha29aaf52010-02-16 18:57:21 -0600303
304/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
305
306#define I2C_SCL_CTRL_PU BIT(0)
307#define I2C_SDA_CTRL_PU BIT(2)
308#define SR_I2C_SCL_CTRL_PU BIT(4)
309#define SR_I2C_SDA_CTRL_PU BIT(6)
310
Lesly A Mca972d12011-04-14 17:57:53 +0530311#define TWL_EEPROM_R_UNLOCK 0x49
312
Moiz Sonasatha29aaf52010-02-16 18:57:21 -0600313/*----------------------------------------------------------------------*/
314
David Brownella603a7f2008-10-15 12:15:39 +0200315/*
316 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
317 * ... SIH/interrupt only
318 */
319
320#define TWL4030_KEYPAD_KEYP_ISR1 0x11
321#define TWL4030_KEYPAD_KEYP_IMR1 0x12
322#define TWL4030_KEYPAD_KEYP_ISR2 0x13
323#define TWL4030_KEYPAD_KEYP_IMR2 0x14
324#define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
325#define TWL4030_KEYPAD_KEYP_EDR 0x16
326#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
327
328/*----------------------------------------------------------------------*/
329
330/*
331 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
332 * ... SIH/interrupt only
333 */
334
335#define TWL4030_MADC_ISR1 0x61
336#define TWL4030_MADC_IMR1 0x62
337#define TWL4030_MADC_ISR2 0x63
338#define TWL4030_MADC_IMR2 0x64
339#define TWL4030_MADC_SIR 0x65 /* test register */
340#define TWL4030_MADC_EDR 0x66
341#define TWL4030_MADC_SIH_CTRL 0x67
342
343/*----------------------------------------------------------------------*/
344
345/*
346 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
347 */
348
349#define TWL4030_INTERRUPTS_BCIISR1A 0x0
350#define TWL4030_INTERRUPTS_BCIISR2A 0x1
351#define TWL4030_INTERRUPTS_BCIIMR1A 0x2
352#define TWL4030_INTERRUPTS_BCIIMR2A 0x3
353#define TWL4030_INTERRUPTS_BCIISR1B 0x4
354#define TWL4030_INTERRUPTS_BCIISR2B 0x5
355#define TWL4030_INTERRUPTS_BCIIMR1B 0x6
356#define TWL4030_INTERRUPTS_BCIIMR2B 0x7
357#define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
358#define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
359#define TWL4030_INTERRUPTS_BCIEDR1 0xa
360#define TWL4030_INTERRUPTS_BCIEDR2 0xb
361#define TWL4030_INTERRUPTS_BCIEDR3 0xc
362#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
363
364/*----------------------------------------------------------------------*/
365
366/*
367 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
368 */
369
370#define TWL4030_INT_PWR_ISR1 0x0
371#define TWL4030_INT_PWR_IMR1 0x1
372#define TWL4030_INT_PWR_ISR2 0x2
373#define TWL4030_INT_PWR_IMR2 0x3
374#define TWL4030_INT_PWR_SIR 0x4 /* test register */
375#define TWL4030_INT_PWR_EDR1 0x5
376#define TWL4030_INT_PWR_EDR2 0x6
377#define TWL4030_INT_PWR_SIH_CTRL 0x7
378
379/*----------------------------------------------------------------------*/
380
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200381/*
382 * Accessory Interrupts
383 */
384#define TWL5031_ACIIMR_LSB 0x05
385#define TWL5031_ACIIMR_MSB 0x06
386#define TWL5031_ACIIDR_LSB 0x07
387#define TWL5031_ACIIDR_MSB 0x08
388#define TWL5031_ACCISR1 0x0F
389#define TWL5031_ACCIMR1 0x10
390#define TWL5031_ACCISR2 0x11
391#define TWL5031_ACCIMR2 0x12
392#define TWL5031_ACCSIR 0x13
393#define TWL5031_ACCEDR1 0x14
394#define TWL5031_ACCSIHCTRL 0x15
395
396/*----------------------------------------------------------------------*/
397
398/*
399 * Battery Charger Controller
400 */
401
402#define TWL5031_INTERRUPTS_BCIISR1 0x0
403#define TWL5031_INTERRUPTS_BCIIMR1 0x1
404#define TWL5031_INTERRUPTS_BCIISR2 0x2
405#define TWL5031_INTERRUPTS_BCIIMR2 0x3
406#define TWL5031_INTERRUPTS_BCISIR 0x4
407#define TWL5031_INTERRUPTS_BCIEDR1 0x5
408#define TWL5031_INTERRUPTS_BCIEDR2 0x6
409#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
410
411/*----------------------------------------------------------------------*/
412
Felipe Balbi89712052010-09-10 17:10:21 +0200413/*
414 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER)
415 */
416
417#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00
418#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01
419#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02
420#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03
421#define TWL4030_PM_MASTER_STS_BOOT 0x04
422#define TWL4030_PM_MASTER_CFG_BOOT 0x05
423#define TWL4030_PM_MASTER_SHUNDAN 0x06
424#define TWL4030_PM_MASTER_BOOT_BCI 0x07
425#define TWL4030_PM_MASTER_CFG_PWRANA1 0x08
426#define TWL4030_PM_MASTER_CFG_PWRANA2 0x09
427#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b
428#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c
429#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d
430#define TWL4030_PM_MASTER_PROTECT_KEY 0x0e
431#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f
432#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10
433#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11
434#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12
435#define TWL4030_PM_MASTER_STS_P123_STATE 0x13
436#define TWL4030_PM_MASTER_PB_CFG 0x14
437#define TWL4030_PM_MASTER_PB_WORD_MSB 0x15
438#define TWL4030_PM_MASTER_PB_WORD_LSB 0x16
439#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c
440#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d
441#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e
442#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f
443#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20
444#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21
445#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22
446#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23
447#define TWL4030_PM_MASTER_MEMORY_DATA 0x24
448
449#define TWL4030_PM_MASTER_KEY_CFG1 0xc0
450#define TWL4030_PM_MASTER_KEY_CFG2 0x0c
451
452#define TWL4030_PM_MASTER_KEY_TST1 0xe0
453#define TWL4030_PM_MASTER_KEY_TST2 0x0e
454
455#define TWL4030_PM_MASTER_GLOBAL_TST 0xb6
456
457/*----------------------------------------------------------------------*/
458
David Brownellfa16a5c2009-02-08 10:37:06 -0800459/* Power bus message definitions */
460
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200461/* The TWL4030/5030 splits its power-management resources (the various
462 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
463 * P3. These groups can then be configured to transition between sleep, wait-on
464 * and active states by sending messages to the power bus. See Section 5.4.2
465 * Power Resources of TWL4030 TRM
466 */
David Brownellfa16a5c2009-02-08 10:37:06 -0800467
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200468/* Processor groups */
469#define DEV_GRP_NULL 0x0
470#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
471#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
472#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
473
474/* Resource groups */
475#define RES_GRP_RES 0x0 /* Reserved */
476#define RES_GRP_PP 0x1 /* Power providers */
477#define RES_GRP_RC 0x2 /* Reset and control */
David Brownellfa16a5c2009-02-08 10:37:06 -0800478#define RES_GRP_PP_RC 0x3
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200479#define RES_GRP_PR 0x4 /* Power references */
David Brownellfa16a5c2009-02-08 10:37:06 -0800480#define RES_GRP_PP_PR 0x5
481#define RES_GRP_RC_PR 0x6
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200482#define RES_GRP_ALL 0x7 /* All resource groups */
David Brownellfa16a5c2009-02-08 10:37:06 -0800483
484#define RES_TYPE2_R0 0x0
485
486#define RES_TYPE_ALL 0x7
487
Amit Kucheriab4ead612009-10-19 15:11:00 +0300488/* Resource states */
David Brownellfa16a5c2009-02-08 10:37:06 -0800489#define RES_STATE_WRST 0xF
490#define RES_STATE_ACTIVE 0xE
491#define RES_STATE_SLEEP 0x8
492#define RES_STATE_OFF 0x0
493
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200494/* Power resources */
495
496/* Power providers */
497#define RES_VAUX1 1
498#define RES_VAUX2 2
499#define RES_VAUX3 3
500#define RES_VAUX4 4
501#define RES_VMMC1 5
502#define RES_VMMC2 6
503#define RES_VPLL1 7
504#define RES_VPLL2 8
505#define RES_VSIM 9
506#define RES_VDAC 10
507#define RES_VINTANA1 11
508#define RES_VINTANA2 12
509#define RES_VINTDIG 13
510#define RES_VIO 14
511#define RES_VDD1 15
512#define RES_VDD2 16
513#define RES_VUSB_1V5 17
514#define RES_VUSB_1V8 18
515#define RES_VUSB_3V1 19
516#define RES_VUSBCP 20
517#define RES_REGEN 21
518/* Reset and control */
519#define RES_NRES_PWRON 22
520#define RES_CLKEN 23
521#define RES_SYSEN 24
522#define RES_HFCLKOUT 25
523#define RES_32KCLKOUT 26
524#define RES_RESET 27
525/* Power Reference */
Lesly A Md7ac8292011-04-14 17:57:51 +0530526#define RES_MAIN_REF 28
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200527
528#define TOTAL_RESOURCES 28
David Brownellfa16a5c2009-02-08 10:37:06 -0800529/*
530 * Power Bus Message Format ... these can be sent individually by Linux,
531 * but are usually part of downloaded scripts that are run when various
532 * power events are triggered.
533 *
534 * Broadcast Message (16 Bits):
535 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
536 * RES_STATE[3:0]
537 *
538 * Singular Message (16 Bits):
539 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
540 */
541
542#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
543 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
544 | (type) << 4 | (state))
545
546#define MSG_SINGULAR(devgrp, id, state) \
547 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
548
Rajendra Nayak441a4502009-12-13 22:19:23 +0100549#define MSG_BROADCAST_ALL(devgrp, state) \
550 ((devgrp) << 5 | (state))
551
552#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
553#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
554#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
David Brownellfa16a5c2009-02-08 10:37:06 -0800555/*----------------------------------------------------------------------*/
556
Ilkka Koskinen38a68492009-10-22 14:14:09 +0300557struct twl4030_clock_init_data {
558 bool ck32k_lowpwr_enable;
559};
560
David Brownella603a7f2008-10-15 12:15:39 +0200561struct twl4030_bci_platform_data {
562 int *battery_tmp_tbl;
563 unsigned int tblsize;
NeilBrown210d4bc2012-05-09 07:40:40 +1000564 int bb_uvolt; /* voltage to charge backup battery */
565 int bb_uamp; /* current for backup battery charging */
David Brownella603a7f2008-10-15 12:15:39 +0200566};
567
568/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
569struct twl4030_gpio_platform_data {
David Brownella30d46c2008-10-20 23:46:28 +0200570 /* package the two LED signals as output-only GPIOs? */
571 bool use_leds;
572
573 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
574 u8 mmc_cd;
575
David Brownellcabb3fc2009-01-06 14:42:26 -0800576 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
577 u32 debounce;
578
David Brownella603a7f2008-10-15 12:15:39 +0200579 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
580 * should be enabled. Else, if that bit is set in "pulldowns",
581 * that pulldown is enabled. Don't waste power by letting any
582 * digital inputs float...
583 */
584 u32 pullups;
585 u32 pulldowns;
586
587 int (*setup)(struct device *dev,
588 unsigned gpio, unsigned ngpio);
589 int (*teardown)(struct device *dev,
590 unsigned gpio, unsigned ngpio);
591};
592
593struct twl4030_madc_platform_data {
594 int irq_line;
595};
596
Thomas Weberf7223772010-03-23 19:50:16 +0100597/* Boards have unique mappings of {row, col} --> keycode.
Amit Kucheriaacf442d2009-10-05 21:43:44 -0700598 * Column and row are 8 bits each, but range only from 0..7.
David Brownell9d834062009-08-25 19:24:14 -0700599 * a PERSISTENT_KEY is "always on" and never reported.
600 */
Amit Kucheriaacf442d2009-10-05 21:43:44 -0700601#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
David Brownell9d834062009-08-25 19:24:14 -0700602
David Brownella603a7f2008-10-15 12:15:39 +0200603struct twl4030_keypad_data {
David Brownell9d834062009-08-25 19:24:14 -0700604 const struct matrix_keymap_data *keymap_data;
605 unsigned rows;
606 unsigned cols;
607 bool rep;
David Brownella603a7f2008-10-15 12:15:39 +0200608};
609
610enum twl4030_usb_mode {
611 T2_USB_MODE_ULPI = 1,
612 T2_USB_MODE_CEA2011_3PIN = 2,
613};
614
615struct twl4030_usb_data {
616 enum twl4030_usb_mode usb_mode;
Graeme Gregory521d8ec2011-05-12 14:27:55 +0100617 unsigned long features;
Hema HKe70357e2010-12-10 18:09:52 +0530618
619 int (*phy_init)(struct device *dev);
620 int (*phy_exit)(struct device *dev);
621 /* Power on/off the PHY */
622 int (*phy_power)(struct device *dev, int iD, int on);
623 /* enable/disable phy clocks */
624 int (*phy_set_clock)(struct device *dev, int on);
Hema HKd8692742011-02-17 12:06:06 +0530625 /* suspend/resume of phy */
626 int (*phy_suspend)(struct device *dev, int suspend);
David Brownella603a7f2008-10-15 12:15:39 +0200627};
628
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200629struct twl4030_ins {
630 u16 pmb_message;
631 u8 delay;
632};
633
634struct twl4030_script {
635 struct twl4030_ins *script;
636 unsigned size;
637 u8 flags;
638#define TWL4030_WRST_SCRIPT (1<<0)
639#define TWL4030_WAKEUP12_SCRIPT (1<<1)
640#define TWL4030_WAKEUP3_SCRIPT (1<<2)
641#define TWL4030_SLEEP_SCRIPT (1<<3)
642};
643
644struct twl4030_resconfig {
645 u8 resource;
646 u8 devgroup; /* Processor group that Power resource belongs to */
647 u8 type; /* Power resource addressed, 6 / broadcast message */
648 u8 type2; /* Power resource addressed, 3 / broadcast message */
Amit Kucheriab4ead612009-10-19 15:11:00 +0300649 u8 remap_off; /* off state remapping */
650 u8 remap_sleep; /* sleep state remapping */
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200651};
652
653struct twl4030_power_data {
654 struct twl4030_script **scripts;
655 unsigned num;
656 struct twl4030_resconfig *resource_config;
Aaro Koskinen56baa662009-10-19 21:24:02 +0200657#define TWL4030_RESCONFIG_UNDEF ((u8)-1)
Igor Grinberg26cc3ab2011-11-13 11:49:50 +0200658 bool use_poweroff; /* Board is wired for TWL poweroff */
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200659};
660
661extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
Mike Turquette11a441c2010-02-22 11:16:30 -0600662extern int twl4030_remove_script(u8 flags);
Igor Grinberg26cc3ab2011-11-13 11:49:50 +0200663extern void twl4030_power_off(void);
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200664
Peter Ujfalusi4ae6df52011-05-31 15:21:13 +0300665struct twl4030_codec_data {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000666 unsigned int digimic_delay; /* in ms */
Peter Ujfalusi0b83dde2009-10-22 13:26:45 +0300667 unsigned int ramp_delay_value;
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000668 unsigned int offset_cncl_path;
669 unsigned int check_defaults:1;
670 unsigned int reset_registers:1;
Peter Ujfalusi0b83dde2009-10-22 13:26:45 +0300671 unsigned int hs_extmute:1;
Peter Ujfalusi281ecd12012-09-10 13:46:27 +0300672 int hs_extmute_gpio;
Peter Ujfalusi0b83dde2009-10-22 13:26:45 +0300673};
674
Peter Ujfalusi4ae6df52011-05-31 15:21:13 +0300675struct twl4030_vibra_data {
Peter Ujfalusi0b83dde2009-10-22 13:26:45 +0300676 unsigned int coexist;
677};
678
Peter Ujfalusi4ae6df52011-05-31 15:21:13 +0300679struct twl4030_audio_data {
Peter Ujfalusicfd53242009-11-04 09:58:17 +0200680 unsigned int audio_mclk;
Peter Ujfalusi4ae6df52011-05-31 15:21:13 +0300681 struct twl4030_codec_data *codec;
682 struct twl4030_vibra_data *vibra;
Misael Lopez Cruzd62abe52010-02-23 18:10:19 -0600683
Olaya, Margarita6a1c7b72010-03-17 17:42:29 -0500684 /* twl6040 */
685 int audpwron_gpio; /* audio power-on gpio */
686 int naudint_irq; /* audio interrupt */
Misael Lopez Cruzf19b2822011-04-27 02:14:07 -0500687 unsigned int irq_base;
Peter Ujfalusi0b83dde2009-10-22 13:26:45 +0300688};
689
David Brownella603a7f2008-10-15 12:15:39 +0200690struct twl4030_platform_data {
Ilkka Koskinen38a68492009-10-22 14:14:09 +0300691 struct twl4030_clock_init_data *clock;
David Brownella603a7f2008-10-15 12:15:39 +0200692 struct twl4030_bci_platform_data *bci;
693 struct twl4030_gpio_platform_data *gpio;
694 struct twl4030_madc_platform_data *madc;
695 struct twl4030_keypad_data *keypad;
696 struct twl4030_usb_data *usb;
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200697 struct twl4030_power_data *power;
Peter Ujfalusi4ae6df52011-05-31 15:21:13 +0300698 struct twl4030_audio_data *audio;
David Brownella603a7f2008-10-15 12:15:39 +0200699
Rajendra Nayak9da66532009-12-13 22:29:47 +0100700 /* Common LDO regulators for TWL4030/TWL6030 */
David Brownelldad759f2008-12-01 00:43:58 +0100701 struct regulator_init_data *vdac;
Rajendra Nayak9da66532009-12-13 22:29:47 +0100702 struct regulator_init_data *vaux1;
703 struct regulator_init_data *vaux2;
704 struct regulator_init_data *vaux3;
Tero Kristo34a38442012-02-28 15:09:10 +0530705 struct regulator_init_data *vdd1;
706 struct regulator_init_data *vdd2;
707 struct regulator_init_data *vdd3;
Rajendra Nayak9da66532009-12-13 22:29:47 +0100708 /* TWL4030 LDO regulators */
David Brownelldad759f2008-12-01 00:43:58 +0100709 struct regulator_init_data *vpll1;
710 struct regulator_init_data *vpll2;
711 struct regulator_init_data *vmmc1;
712 struct regulator_init_data *vmmc2;
713 struct regulator_init_data *vsim;
David Brownelldad759f2008-12-01 00:43:58 +0100714 struct regulator_init_data *vaux4;
Juha Keski-Saariab4abe052009-12-11 11:12:15 +0100715 struct regulator_init_data *vio;
Juha Keski-Saariab4abe052009-12-11 11:12:15 +0100716 struct regulator_init_data *vintana1;
717 struct regulator_init_data *vintana2;
718 struct regulator_init_data *vintdig;
Rajendra Nayak9da66532009-12-13 22:29:47 +0100719 /* TWL6030 LDO regulators */
720 struct regulator_init_data *vmmc;
721 struct regulator_init_data *vpp;
722 struct regulator_init_data *vusim;
723 struct regulator_init_data *vana;
724 struct regulator_init_data *vcxio;
725 struct regulator_init_data *vusb;
Balaji T K8e6de4a2011-02-10 18:44:50 +0530726 struct regulator_init_data *clk32kg;
Peter Ujfalusi46eda3e2012-02-28 15:09:13 +0530727 struct regulator_init_data *v1v8;
728 struct regulator_init_data *v2v1;
Graeme Gregory521d8ec2011-05-12 14:27:55 +0100729 /* TWL6025 LDO regulators */
730 struct regulator_init_data *ldo1;
731 struct regulator_init_data *ldo2;
732 struct regulator_init_data *ldo3;
733 struct regulator_init_data *ldo4;
734 struct regulator_init_data *ldo5;
735 struct regulator_init_data *ldo6;
736 struct regulator_init_data *ldo7;
737 struct regulator_init_data *ldoln;
738 struct regulator_init_data *ldousb;
739 /* TWL6025 DCDC regulators */
740 struct regulator_init_data *smps3;
741 struct regulator_init_data *smps4;
742 struct regulator_init_data *vio6025;
David Brownella603a7f2008-10-15 12:15:39 +0200743};
744
Tero Kristo63bfff42012-02-16 12:27:52 +0200745struct twl_regulator_driver_data {
746 int (*set_voltage)(void *data, int target_uV);
747 int (*get_voltage)(void *data);
748 void *data;
749 unsigned long features;
750};
NeilBrownc30540d2012-05-09 05:43:59 +1000751/* chip-specific feature flags, for twl_regulator_driver_data.features */
752#define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */
753#define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */
754#define TWL5031 BIT(2) /* twl5031 has different registers */
755#define TWL6030_CLASS BIT(3) /* TWL6030 class */
756#define TWL6025_SUBCLASS BIT(4) /* TWL6025 has changed registers */
NeilBrown411a2df2012-05-09 05:44:00 +1000757#define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible
758 * but not officially supported.
759 * This flag is necessary to
760 * enable them.
761 */
Tero Kristo63bfff42012-02-16 12:27:52 +0200762
David Brownella603a7f2008-10-15 12:15:39 +0200763/*----------------------------------------------------------------------*/
764
Benoit Coussonf01b1f92012-02-29 22:38:06 +0100765int twl4030_sih_setup(struct device *dev, int module, int irq_base);
David Brownella30d46c2008-10-20 23:46:28 +0200766
David Brownella603a7f2008-10-15 12:15:39 +0200767/* Offsets to Power Registers */
768#define TWL4030_VDAC_DEV_GRP 0x3B
769#define TWL4030_VDAC_DEDICATED 0x3E
770#define TWL4030_VAUX1_DEV_GRP 0x17
771#define TWL4030_VAUX1_DEDICATED 0x1A
772#define TWL4030_VAUX2_DEV_GRP 0x1B
773#define TWL4030_VAUX2_DEDICATED 0x1E
774#define TWL4030_VAUX3_DEV_GRP 0x1F
775#define TWL4030_VAUX3_DEDICATED 0x22
776
Christoph Eggerf7ea2dc2010-01-15 15:33:46 +0100777static inline int twl4030charger_usb_en(int enable) { return 0; }
David Brownella603a7f2008-10-15 12:15:39 +0200778
David Brownelldad759f2008-12-01 00:43:58 +0100779/*----------------------------------------------------------------------*/
780
781/* Linux-specific regulator identifiers ... for now, we only support
782 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
783 * need to tie into hardware based voltage scaling (cpufreq etc), while
784 * VIO is generally fixed.
785 */
786
Rajendra Nayak441a4502009-12-13 22:19:23 +0100787/* TWL4030 SMPS/LDO's */
David Brownelldad759f2008-12-01 00:43:58 +0100788/* EXTERNAL dc-to-dc buck converters */
789#define TWL4030_REG_VDD1 0
790#define TWL4030_REG_VDD2 1
791#define TWL4030_REG_VIO 2
792
793/* EXTERNAL LDOs */
794#define TWL4030_REG_VDAC 3
795#define TWL4030_REG_VPLL1 4
796#define TWL4030_REG_VPLL2 5 /* not on all chips */
797#define TWL4030_REG_VMMC1 6
798#define TWL4030_REG_VMMC2 7 /* not on all chips */
799#define TWL4030_REG_VSIM 8 /* not on all chips */
800#define TWL4030_REG_VAUX1 9 /* not on all chips */
801#define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
802#define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
803#define TWL4030_REG_VAUX3 12 /* not on all chips */
804#define TWL4030_REG_VAUX4 13 /* not on all chips */
805
806/* INTERNAL LDOs */
807#define TWL4030_REG_VINTANA1 14
808#define TWL4030_REG_VINTANA2 15
809#define TWL4030_REG_VINTDIG 16
810#define TWL4030_REG_VUSB1V5 17
811#define TWL4030_REG_VUSB1V8 18
812#define TWL4030_REG_VUSB3V1 19
David Brownelldad759f2008-12-01 00:43:58 +0100813
Rajendra Nayak441a4502009-12-13 22:19:23 +0100814/* TWL6030 SMPS/LDO's */
Thomas Weberf7223772010-03-23 19:50:16 +0100815/* EXTERNAL dc-to-dc buck convertor controllable via SR */
Rajendra Nayak441a4502009-12-13 22:19:23 +0100816#define TWL6030_REG_VDD1 30
817#define TWL6030_REG_VDD2 31
818#define TWL6030_REG_VDD3 32
819
820/* Non SR compliant dc-to-dc buck convertors */
Thomas Weberf7223772010-03-23 19:50:16 +0100821#define TWL6030_REG_VMEM 33
Rajendra Nayak441a4502009-12-13 22:19:23 +0100822#define TWL6030_REG_V2V1 34
Thomas Weberf7223772010-03-23 19:50:16 +0100823#define TWL6030_REG_V1V29 35
Rajendra Nayak441a4502009-12-13 22:19:23 +0100824#define TWL6030_REG_V1V8 36
825
826/* EXTERNAL LDOs */
827#define TWL6030_REG_VAUX1_6030 37
828#define TWL6030_REG_VAUX2_6030 38
829#define TWL6030_REG_VAUX3_6030 39
830#define TWL6030_REG_VMMC 40
831#define TWL6030_REG_VPP 41
832#define TWL6030_REG_VUSIM 42
833#define TWL6030_REG_VANA 43
834#define TWL6030_REG_VCXIO 44
835#define TWL6030_REG_VDAC 45
836#define TWL6030_REG_VUSB 46
837
838/* INTERNAL LDOs */
839#define TWL6030_REG_VRTC 47
Balaji T K8e6de4a2011-02-10 18:44:50 +0530840#define TWL6030_REG_CLK32KG 48
Rajendra Nayak441a4502009-12-13 22:19:23 +0100841
Graeme Gregory521d8ec2011-05-12 14:27:55 +0100842/* LDOs on 6025 have different names */
843#define TWL6025_REG_LDO2 49
844#define TWL6025_REG_LDO4 50
845#define TWL6025_REG_LDO3 51
846#define TWL6025_REG_LDO5 52
847#define TWL6025_REG_LDO1 53
848#define TWL6025_REG_LDO7 54
849#define TWL6025_REG_LDO6 55
850#define TWL6025_REG_LDOLN 56
851#define TWL6025_REG_LDOUSB 57
852
853/* 6025 DCDC supplies */
854#define TWL6025_REG_SMPS3 58
855#define TWL6025_REG_SMPS4 59
856#define TWL6025_REG_VIO 60
857
858
David Brownella603a7f2008-10-15 12:15:39 +0200859#endif /* End of __TWL4030_H */