Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1 | /* |
| 2 | * arch/powerpc/kernel/mpic.c |
| 3 | * |
| 4 | * Driver for interrupt controllers following the OpenPIC standard, the |
| 5 | * common implementation beeing IBM's MPIC. This driver also can deal |
| 6 | * with various broken implementations of this HW. |
| 7 | * |
| 8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. |
Scott Wood | 22d168c | 2011-03-24 16:43:54 -0500 | [diff] [blame] | 9 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 10 | * |
| 11 | * This file is subject to the terms and conditions of the GNU General Public |
| 12 | * License. See the file COPYING in the main directory of this archive |
| 13 | * for more details. |
| 14 | */ |
| 15 | |
| 16 | #undef DEBUG |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 17 | #undef DEBUG_IPI |
| 18 | #undef DEBUG_IRQ |
| 19 | #undef DEBUG_LOW |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 20 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 21 | #include <linux/types.h> |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/irq.h> |
| 25 | #include <linux/smp.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/bootmem.h> |
| 28 | #include <linux/spinlock.h> |
| 29 | #include <linux/pci.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 31 | #include <linux/syscore_ops.h> |
Christian Dietrich | 7646223 | 2011-06-04 05:36:54 +0000 | [diff] [blame] | 32 | #include <linux/ratelimit.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 33 | |
| 34 | #include <asm/ptrace.h> |
| 35 | #include <asm/signal.h> |
| 36 | #include <asm/io.h> |
| 37 | #include <asm/pgtable.h> |
| 38 | #include <asm/irq.h> |
| 39 | #include <asm/machdep.h> |
| 40 | #include <asm/mpic.h> |
| 41 | #include <asm/smp.h> |
| 42 | |
Michael Ellerman | a7de7c7 | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 43 | #include "mpic.h" |
| 44 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 45 | #ifdef DEBUG |
| 46 | #define DBG(fmt...) printk(fmt) |
| 47 | #else |
| 48 | #define DBG(fmt...) |
| 49 | #endif |
| 50 | |
| 51 | static struct mpic *mpics; |
| 52 | static struct mpic *mpic_primary; |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 53 | static DEFINE_RAW_SPINLOCK(mpic_lock); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 54 | |
Paul Mackerras | c0c0d99 | 2005-10-01 13:49:08 +1000 | [diff] [blame] | 55 | #ifdef CONFIG_PPC32 /* XXX for now */ |
Andy Whitcroft | e40c7f0 | 2005-11-29 19:25:54 +0000 | [diff] [blame] | 56 | #ifdef CONFIG_IRQ_ALL_CPUS |
| 57 | #define distribute_irqs (1) |
| 58 | #else |
| 59 | #define distribute_irqs (0) |
| 60 | #endif |
Paul Mackerras | c0c0d99 | 2005-10-01 13:49:08 +1000 | [diff] [blame] | 61 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 62 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 63 | #ifdef CONFIG_MPIC_WEIRD |
| 64 | static u32 mpic_infos[][MPIC_IDX_END] = { |
| 65 | [0] = { /* Original OpenPIC compatible MPIC */ |
| 66 | MPIC_GREG_BASE, |
| 67 | MPIC_GREG_FEATURE_0, |
| 68 | MPIC_GREG_GLOBAL_CONF_0, |
| 69 | MPIC_GREG_VENDOR_ID, |
| 70 | MPIC_GREG_IPI_VECTOR_PRI_0, |
| 71 | MPIC_GREG_IPI_STRIDE, |
| 72 | MPIC_GREG_SPURIOUS, |
| 73 | MPIC_GREG_TIMER_FREQ, |
| 74 | |
| 75 | MPIC_TIMER_BASE, |
| 76 | MPIC_TIMER_STRIDE, |
| 77 | MPIC_TIMER_CURRENT_CNT, |
| 78 | MPIC_TIMER_BASE_CNT, |
| 79 | MPIC_TIMER_VECTOR_PRI, |
| 80 | MPIC_TIMER_DESTINATION, |
| 81 | |
| 82 | MPIC_CPU_BASE, |
| 83 | MPIC_CPU_STRIDE, |
| 84 | MPIC_CPU_IPI_DISPATCH_0, |
| 85 | MPIC_CPU_IPI_DISPATCH_STRIDE, |
| 86 | MPIC_CPU_CURRENT_TASK_PRI, |
| 87 | MPIC_CPU_WHOAMI, |
| 88 | MPIC_CPU_INTACK, |
| 89 | MPIC_CPU_EOI, |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 90 | MPIC_CPU_MCACK, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 91 | |
| 92 | MPIC_IRQ_BASE, |
| 93 | MPIC_IRQ_STRIDE, |
| 94 | MPIC_IRQ_VECTOR_PRI, |
| 95 | MPIC_VECPRI_VECTOR_MASK, |
| 96 | MPIC_VECPRI_POLARITY_POSITIVE, |
| 97 | MPIC_VECPRI_POLARITY_NEGATIVE, |
| 98 | MPIC_VECPRI_SENSE_LEVEL, |
| 99 | MPIC_VECPRI_SENSE_EDGE, |
| 100 | MPIC_VECPRI_POLARITY_MASK, |
| 101 | MPIC_VECPRI_SENSE_MASK, |
| 102 | MPIC_IRQ_DESTINATION |
| 103 | }, |
| 104 | [1] = { /* Tsi108/109 PIC */ |
| 105 | TSI108_GREG_BASE, |
| 106 | TSI108_GREG_FEATURE_0, |
| 107 | TSI108_GREG_GLOBAL_CONF_0, |
| 108 | TSI108_GREG_VENDOR_ID, |
| 109 | TSI108_GREG_IPI_VECTOR_PRI_0, |
| 110 | TSI108_GREG_IPI_STRIDE, |
| 111 | TSI108_GREG_SPURIOUS, |
| 112 | TSI108_GREG_TIMER_FREQ, |
| 113 | |
| 114 | TSI108_TIMER_BASE, |
| 115 | TSI108_TIMER_STRIDE, |
| 116 | TSI108_TIMER_CURRENT_CNT, |
| 117 | TSI108_TIMER_BASE_CNT, |
| 118 | TSI108_TIMER_VECTOR_PRI, |
| 119 | TSI108_TIMER_DESTINATION, |
| 120 | |
| 121 | TSI108_CPU_BASE, |
| 122 | TSI108_CPU_STRIDE, |
| 123 | TSI108_CPU_IPI_DISPATCH_0, |
| 124 | TSI108_CPU_IPI_DISPATCH_STRIDE, |
| 125 | TSI108_CPU_CURRENT_TASK_PRI, |
| 126 | TSI108_CPU_WHOAMI, |
| 127 | TSI108_CPU_INTACK, |
| 128 | TSI108_CPU_EOI, |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 129 | TSI108_CPU_MCACK, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 130 | |
| 131 | TSI108_IRQ_BASE, |
| 132 | TSI108_IRQ_STRIDE, |
| 133 | TSI108_IRQ_VECTOR_PRI, |
| 134 | TSI108_VECPRI_VECTOR_MASK, |
| 135 | TSI108_VECPRI_POLARITY_POSITIVE, |
| 136 | TSI108_VECPRI_POLARITY_NEGATIVE, |
| 137 | TSI108_VECPRI_SENSE_LEVEL, |
| 138 | TSI108_VECPRI_SENSE_EDGE, |
| 139 | TSI108_VECPRI_POLARITY_MASK, |
| 140 | TSI108_VECPRI_SENSE_MASK, |
| 141 | TSI108_IRQ_DESTINATION |
| 142 | }, |
| 143 | }; |
| 144 | |
| 145 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] |
| 146 | |
| 147 | #else /* CONFIG_MPIC_WEIRD */ |
| 148 | |
| 149 | #define MPIC_INFO(name) MPIC_##name |
| 150 | |
| 151 | #endif /* CONFIG_MPIC_WEIRD */ |
| 152 | |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 153 | static inline unsigned int mpic_processor_id(struct mpic *mpic) |
| 154 | { |
| 155 | unsigned int cpu = 0; |
| 156 | |
Kyle Moffett | be8bec5 | 2011-12-02 06:28:03 +0000 | [diff] [blame] | 157 | if (!(mpic->flags & MPIC_SECONDARY)) |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 158 | cpu = hard_smp_processor_id(); |
| 159 | |
| 160 | return cpu; |
| 161 | } |
| 162 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 163 | /* |
| 164 | * Register accessor functions |
| 165 | */ |
| 166 | |
| 167 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 168 | static inline u32 _mpic_read(enum mpic_reg_type type, |
| 169 | struct mpic_reg_bank *rb, |
| 170 | unsigned int reg) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 171 | { |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 172 | switch(type) { |
| 173 | #ifdef CONFIG_PPC_DCR |
| 174 | case mpic_access_dcr: |
Michael Ellerman | 83f34df | 2007-10-15 19:34:36 +1000 | [diff] [blame] | 175 | return dcr_read(rb->dhost, reg); |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 176 | #endif |
| 177 | case mpic_access_mmio_be: |
| 178 | return in_be32(rb->base + (reg >> 2)); |
| 179 | case mpic_access_mmio_le: |
| 180 | default: |
| 181 | return in_le32(rb->base + (reg >> 2)); |
| 182 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 183 | } |
| 184 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 185 | static inline void _mpic_write(enum mpic_reg_type type, |
| 186 | struct mpic_reg_bank *rb, |
| 187 | unsigned int reg, u32 value) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 188 | { |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 189 | switch(type) { |
| 190 | #ifdef CONFIG_PPC_DCR |
| 191 | case mpic_access_dcr: |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 192 | dcr_write(rb->dhost, reg, value); |
| 193 | break; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 194 | #endif |
| 195 | case mpic_access_mmio_be: |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 196 | out_be32(rb->base + (reg >> 2), value); |
| 197 | break; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 198 | case mpic_access_mmio_le: |
| 199 | default: |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 200 | out_le32(rb->base + (reg >> 2), value); |
| 201 | break; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 202 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) |
| 206 | { |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 207 | enum mpic_reg_type type = mpic->reg_type; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 208 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
| 209 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 210 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 211 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
| 212 | type = mpic_access_mmio_be; |
| 213 | return _mpic_read(type, &mpic->gregs, offset); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) |
| 217 | { |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 218 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
| 219 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 220 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 221 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 222 | } |
| 223 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 224 | static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm) |
| 225 | { |
| 226 | unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + |
| 227 | ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); |
| 228 | |
| 229 | if (tm >= 4) |
| 230 | offset += 0x1000 / 4; |
| 231 | |
| 232 | return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); |
| 233 | } |
| 234 | |
| 235 | static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value) |
| 236 | { |
| 237 | unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + |
| 238 | ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); |
| 239 | |
| 240 | if (tm >= 4) |
| 241 | offset += 0x1000 / 4; |
| 242 | |
| 243 | _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); |
| 244 | } |
| 245 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 246 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) |
| 247 | { |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 248 | unsigned int cpu = mpic_processor_id(mpic); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 249 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 250 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 251 | } |
| 252 | |
| 253 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) |
| 254 | { |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 255 | unsigned int cpu = mpic_processor_id(mpic); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 256 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 257 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) |
| 261 | { |
| 262 | unsigned int isu = src_no >> mpic->isu_shift; |
| 263 | unsigned int idx = src_no & mpic->isu_mask; |
Michael Ellerman | 11a6b29 | 2009-07-05 16:08:52 +0000 | [diff] [blame] | 264 | unsigned int val; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 265 | |
Michael Ellerman | 11a6b29 | 2009-07-05 16:08:52 +0000 | [diff] [blame] | 266 | val = _mpic_read(mpic->reg_type, &mpic->isus[isu], |
| 267 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); |
Olof Johansson | 0d72ba9 | 2007-09-08 05:13:19 +1000 | [diff] [blame] | 268 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
| 269 | if (reg == 0) |
Michael Ellerman | 11a6b29 | 2009-07-05 16:08:52 +0000 | [diff] [blame] | 270 | val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | |
| 271 | mpic->isu_reg0_shadow[src_no]; |
Olof Johansson | 0d72ba9 | 2007-09-08 05:13:19 +1000 | [diff] [blame] | 272 | #endif |
Michael Ellerman | 11a6b29 | 2009-07-05 16:08:52 +0000 | [diff] [blame] | 273 | return val; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 274 | } |
| 275 | |
| 276 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, |
| 277 | unsigned int reg, u32 value) |
| 278 | { |
| 279 | unsigned int isu = src_no >> mpic->isu_shift; |
| 280 | unsigned int idx = src_no & mpic->isu_mask; |
| 281 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 282 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 283 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
Olof Johansson | 0d72ba9 | 2007-09-08 05:13:19 +1000 | [diff] [blame] | 284 | |
| 285 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
| 286 | if (reg == 0) |
Michael Ellerman | 11a6b29 | 2009-07-05 16:08:52 +0000 | [diff] [blame] | 287 | mpic->isu_reg0_shadow[src_no] = |
| 288 | value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); |
Olof Johansson | 0d72ba9 | 2007-09-08 05:13:19 +1000 | [diff] [blame] | 289 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 290 | } |
| 291 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 292 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
| 293 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 294 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
| 295 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 296 | #define mpic_tm_read(i) _mpic_tm_read(mpic,(i)) |
| 297 | #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 298 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) |
| 299 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) |
| 300 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) |
| 301 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) |
| 302 | |
| 303 | |
| 304 | /* |
| 305 | * Low level utility functions |
| 306 | */ |
| 307 | |
| 308 | |
Becky Bruce | c51a3fdc | 2008-01-14 20:56:18 -0600 | [diff] [blame] | 309 | static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 310 | struct mpic_reg_bank *rb, unsigned int offset, |
| 311 | unsigned int size) |
| 312 | { |
| 313 | rb->base = ioremap(phys_addr + offset, size); |
| 314 | BUG_ON(rb->base == NULL); |
| 315 | } |
| 316 | |
| 317 | #ifdef CONFIG_PPC_DCR |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 318 | static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 319 | unsigned int offset, unsigned int size) |
| 320 | { |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 321 | phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0); |
Kyle Moffett | e62b760 | 2011-12-02 06:28:04 +0000 | [diff] [blame] | 322 | rb->dhost = dcr_map(mpic->node, phys_addr + offset, size); |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 323 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
| 324 | } |
| 325 | |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 326 | static inline void mpic_map(struct mpic *mpic, |
Benjamin Herrenschmidt | 5a2642f | 2009-06-22 16:47:59 +0000 | [diff] [blame] | 327 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, |
| 328 | unsigned int offset, unsigned int size) |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 329 | { |
| 330 | if (mpic->flags & MPIC_USES_DCR) |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 331 | _mpic_map_dcr(mpic, rb, offset, size); |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 332 | else |
| 333 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); |
| 334 | } |
| 335 | #else /* CONFIG_PPC_DCR */ |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 336 | #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 337 | #endif /* !CONFIG_PPC_DCR */ |
| 338 | |
| 339 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 340 | |
| 341 | /* Check if we have one of those nice broken MPICs with a flipped endian on |
| 342 | * reads from IPI registers |
| 343 | */ |
| 344 | static void __init mpic_test_broken_ipi(struct mpic *mpic) |
| 345 | { |
| 346 | u32 r; |
| 347 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 348 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
| 349 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 350 | |
| 351 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { |
| 352 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); |
| 353 | mpic->flags |= MPIC_BROKEN_IPI; |
| 354 | } |
| 355 | } |
| 356 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 357 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 358 | |
| 359 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) |
| 360 | * to force the edge setting on the MPIC and do the ack workaround. |
| 361 | */ |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 362 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 363 | { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 364 | if (source >= 128 || !mpic->fixups) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 365 | return 0; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 366 | return mpic->fixups[source].base != NULL; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 367 | } |
| 368 | |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 369 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 370 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 371 | { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 372 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 373 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 374 | if (fixup->applebase) { |
| 375 | unsigned int soff = (fixup->index >> 3) & ~3; |
| 376 | unsigned int mask = 1U << (fixup->index & 0x1f); |
| 377 | writel(mask, fixup->applebase + soff); |
| 378 | } else { |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 379 | raw_spin_lock(&mpic->fixup_lock); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 380 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); |
| 381 | writel(fixup->data, fixup->base + 4); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 382 | raw_spin_unlock(&mpic->fixup_lock); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 383 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 384 | } |
| 385 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 386 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 387 | bool level) |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 388 | { |
| 389 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
| 390 | unsigned long flags; |
| 391 | u32 tmp; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 392 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 393 | if (fixup->base == NULL) |
| 394 | return; |
| 395 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 396 | DBG("startup_ht_interrupt(0x%x) index: %d\n", |
| 397 | source, fixup->index); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 398 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 399 | /* Enable and configure */ |
| 400 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
| 401 | tmp = readl(fixup->base + 4); |
| 402 | tmp &= ~(0x23U); |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 403 | if (level) |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 404 | tmp |= 0x22; |
| 405 | writel(tmp, fixup->base + 4); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 406 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 407 | |
| 408 | #ifdef CONFIG_PM |
| 409 | /* use the lowest bit inverted to the actual HW, |
| 410 | * set if this fixup was enabled, clear otherwise */ |
| 411 | mpic->save_data[source].fixup_data = tmp | 1; |
| 412 | #endif |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 413 | } |
| 414 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 415 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 416 | { |
| 417 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
| 418 | unsigned long flags; |
| 419 | u32 tmp; |
| 420 | |
| 421 | if (fixup->base == NULL) |
| 422 | return; |
| 423 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 424 | DBG("shutdown_ht_interrupt(0x%x)\n", source); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 425 | |
| 426 | /* Disable */ |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 427 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 428 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
| 429 | tmp = readl(fixup->base + 4); |
Segher Boessenkool | 72b1381 | 2006-02-17 11:25:42 +0100 | [diff] [blame] | 430 | tmp |= 1; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 431 | writel(tmp, fixup->base + 4); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 432 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 433 | |
| 434 | #ifdef CONFIG_PM |
| 435 | /* use the lowest bit inverted to the actual HW, |
| 436 | * set if this fixup was enabled, clear otherwise */ |
| 437 | mpic->save_data[source].fixup_data = tmp & ~1; |
| 438 | #endif |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 439 | } |
| 440 | |
Michael Ellerman | 812fd1f | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 441 | #ifdef CONFIG_PCI_MSI |
| 442 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, |
| 443 | unsigned int devfn) |
| 444 | { |
| 445 | u8 __iomem *base; |
| 446 | u8 pos, flags; |
| 447 | u64 addr = 0; |
| 448 | |
| 449 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
| 450 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { |
| 451 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); |
| 452 | if (id == PCI_CAP_ID_HT) { |
| 453 | id = readb(devbase + pos + 3); |
| 454 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) |
| 455 | break; |
| 456 | } |
| 457 | } |
| 458 | |
| 459 | if (pos == 0) |
| 460 | return; |
| 461 | |
| 462 | base = devbase + pos; |
| 463 | |
| 464 | flags = readb(base + HT_MSI_FLAGS); |
| 465 | if (!(flags & HT_MSI_FLAGS_FIXED)) { |
| 466 | addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; |
| 467 | addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); |
| 468 | } |
| 469 | |
Ingo Molnar | fe33332 | 2009-01-06 14:26:03 +0000 | [diff] [blame] | 470 | printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", |
Michael Ellerman | 812fd1f | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 471 | PCI_SLOT(devfn), PCI_FUNC(devfn), |
| 472 | flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); |
| 473 | |
| 474 | if (!(flags & HT_MSI_FLAGS_ENABLE)) |
| 475 | writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); |
| 476 | } |
| 477 | #else |
| 478 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, |
| 479 | unsigned int devfn) |
| 480 | { |
| 481 | return; |
| 482 | } |
| 483 | #endif |
| 484 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 485 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
| 486 | unsigned int devfn, u32 vdid) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 487 | { |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 488 | int i, irq, n; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 489 | u8 __iomem *base; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 490 | u32 tmp; |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 491 | u8 pos; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 492 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 493 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
| 494 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { |
| 495 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); |
Brice Goglin | 46ff346 | 2006-08-31 01:55:24 -0400 | [diff] [blame] | 496 | if (id == PCI_CAP_ID_HT) { |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 497 | id = readb(devbase + pos + 3); |
Michael Ellerman | beb7cc8 | 2006-11-22 18:26:22 +1100 | [diff] [blame] | 498 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 499 | break; |
| 500 | } |
| 501 | } |
| 502 | if (pos == 0) |
| 503 | return; |
| 504 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 505 | base = devbase + pos; |
| 506 | writeb(0x01, base + 2); |
| 507 | n = (readl(base + 4) >> 16) & 0xff; |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 508 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 509 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
| 510 | " has %d irqs\n", |
| 511 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 512 | |
| 513 | for (i = 0; i <= n; i++) { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 514 | writeb(0x10 + 2 * i, base + 2); |
| 515 | tmp = readl(base + 4); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 516 | irq = (tmp >> 16) & 0xff; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 517 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
| 518 | /* mask it , will be unmasked later */ |
| 519 | tmp |= 0x1; |
| 520 | writel(tmp, base + 4); |
| 521 | mpic->fixups[irq].index = i; |
| 522 | mpic->fixups[irq].base = base; |
| 523 | /* Apple HT PIC has a non-standard way of doing EOIs */ |
| 524 | if ((vdid & 0xffff) == 0x106b) |
| 525 | mpic->fixups[irq].applebase = devbase + 0x60; |
| 526 | else |
| 527 | mpic->fixups[irq].applebase = NULL; |
| 528 | writeb(0x11 + 2 * i, base + 2); |
| 529 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 530 | } |
| 531 | } |
| 532 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 533 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 534 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 535 | { |
| 536 | unsigned int devfn; |
| 537 | u8 __iomem *cfgspace; |
| 538 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 539 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 540 | |
| 541 | /* Allocate fixups array */ |
Anton Vorontsov | ea96025 | 2009-07-01 10:59:57 +0000 | [diff] [blame] | 542 | mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 543 | BUG_ON(mpic->fixups == NULL); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 544 | |
| 545 | /* Init spinlock */ |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 546 | raw_spin_lock_init(&mpic->fixup_lock); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 547 | |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 548 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
| 549 | * so we only need to map 64kB. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 550 | */ |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 551 | cfgspace = ioremap(0xf2000000, 0x10000); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 552 | BUG_ON(cfgspace == NULL); |
| 553 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 554 | /* Now we scan all slots. We do a very quick scan, we read the header |
| 555 | * type, vendor ID and device ID only, that's plenty enough |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 556 | */ |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 557 | for (devfn = 0; devfn < 0x100; devfn++) { |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 558 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
| 559 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); |
| 560 | u32 l = readl(devbase + PCI_VENDOR_ID); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 561 | u16 s; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 562 | |
| 563 | DBG("devfn %x, l: %x\n", devfn, l); |
| 564 | |
| 565 | /* If no device, skip */ |
| 566 | if (l == 0xffffffff || l == 0x00000000 || |
| 567 | l == 0x0000ffff || l == 0xffff0000) |
| 568 | goto next; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 569 | /* Check if is supports capability lists */ |
| 570 | s = readw(devbase + PCI_STATUS); |
| 571 | if (!(s & PCI_STATUS_CAP_LIST)) |
| 572 | goto next; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 573 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 574 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
Michael Ellerman | 812fd1f | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 575 | mpic_scan_ht_msi(mpic, devbase, devfn); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 576 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 577 | next: |
| 578 | /* next device, if function 0 */ |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 579 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 580 | devfn += 7; |
| 581 | } |
| 582 | } |
| 583 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 584 | #else /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 585 | |
| 586 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
| 587 | { |
| 588 | return 0; |
| 589 | } |
| 590 | |
| 591 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
| 592 | { |
| 593 | } |
| 594 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 595 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 596 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 597 | /* Find an mpic associated with a given linux interrupt */ |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 598 | static struct mpic *mpic_find(unsigned int irq) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 599 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 600 | if (irq < NUM_ISA_INTERRUPTS) |
| 601 | return NULL; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 602 | |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 603 | return irq_get_chip_data(irq); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 604 | } |
| 605 | |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 606 | /* Determine if the linux irq is an IPI */ |
| 607 | static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) |
| 608 | { |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 609 | unsigned int src = virq_to_hw(irq); |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 610 | |
| 611 | return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); |
| 612 | } |
| 613 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 614 | /* Determine if the linux irq is a timer */ |
| 615 | static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq) |
| 616 | { |
| 617 | unsigned int src = virq_to_hw(irq); |
| 618 | |
| 619 | return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); |
| 620 | } |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 621 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 622 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
| 623 | static inline u32 mpic_physmask(u32 cpumask) |
| 624 | { |
| 625 | int i; |
| 626 | u32 mask = 0; |
| 627 | |
Milton Miller | ebc0421 | 2011-05-10 19:28:59 +0000 | [diff] [blame] | 628 | for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 629 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); |
| 630 | return mask; |
| 631 | } |
| 632 | |
| 633 | #ifdef CONFIG_SMP |
| 634 | /* Get the mpic structure from the IPI number */ |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 635 | static inline struct mpic * mpic_from_ipi(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 636 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 637 | return irq_data_get_irq_chip_data(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 638 | } |
| 639 | #endif |
| 640 | |
| 641 | /* Get the mpic structure from the irq number */ |
| 642 | static inline struct mpic * mpic_from_irq(unsigned int irq) |
| 643 | { |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 644 | return irq_get_chip_data(irq); |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 645 | } |
| 646 | |
| 647 | /* Get the mpic structure from the irq data */ |
| 648 | static inline struct mpic * mpic_from_irq_data(struct irq_data *d) |
| 649 | { |
| 650 | return irq_data_get_irq_chip_data(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 651 | } |
| 652 | |
| 653 | /* Send an EOI */ |
| 654 | static inline void mpic_eoi(struct mpic *mpic) |
| 655 | { |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 656 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
| 657 | (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 658 | } |
| 659 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 660 | /* |
| 661 | * Linux descriptor level callbacks |
| 662 | */ |
| 663 | |
| 664 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 665 | void mpic_unmask_irq(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 666 | { |
| 667 | unsigned int loops = 100000; |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 668 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 669 | unsigned int src = irqd_to_hwirq(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 670 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 671 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 672 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 673 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
| 674 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 675 | ~MPIC_VECPRI_MASK); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 676 | /* make sure mask gets to controller before we return to user */ |
| 677 | do { |
| 678 | if (!loops--) { |
Scott Wood | 8bfc5e3 | 2011-01-17 12:10:41 +0000 | [diff] [blame] | 679 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
| 680 | __func__, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 681 | break; |
| 682 | } |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 683 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 684 | } |
| 685 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 686 | void mpic_mask_irq(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 687 | { |
| 688 | unsigned int loops = 100000; |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 689 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 690 | unsigned int src = irqd_to_hwirq(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 691 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 692 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 693 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 694 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
| 695 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 696 | MPIC_VECPRI_MASK); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 697 | |
| 698 | /* make sure mask gets to controller before we return to user */ |
| 699 | do { |
| 700 | if (!loops--) { |
Scott Wood | 8bfc5e3 | 2011-01-17 12:10:41 +0000 | [diff] [blame] | 701 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
| 702 | __func__, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 703 | break; |
| 704 | } |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 705 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 706 | } |
| 707 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 708 | void mpic_end_irq(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 709 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 710 | struct mpic *mpic = mpic_from_irq_data(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 711 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 712 | #ifdef DEBUG_IRQ |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 713 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 714 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 715 | /* We always EOI on end_irq() even for edge interrupts since that |
| 716 | * should only lower the priority, the MPIC should have properly |
| 717 | * latched another edge interrupt coming in anyway |
| 718 | */ |
| 719 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 720 | mpic_eoi(mpic); |
| 721 | } |
| 722 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 723 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 724 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 725 | static void mpic_unmask_ht_irq(struct irq_data *d) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 726 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 727 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 728 | unsigned int src = irqd_to_hwirq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 729 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 730 | mpic_unmask_irq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 731 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 732 | if (irqd_is_level_type(d)) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 733 | mpic_ht_end_irq(mpic, src); |
| 734 | } |
| 735 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 736 | static unsigned int mpic_startup_ht_irq(struct irq_data *d) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 737 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 738 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 739 | unsigned int src = irqd_to_hwirq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 740 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 741 | mpic_unmask_irq(d); |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 742 | mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 743 | |
| 744 | return 0; |
| 745 | } |
| 746 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 747 | static void mpic_shutdown_ht_irq(struct irq_data *d) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 748 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 749 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 750 | unsigned int src = irqd_to_hwirq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 751 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 752 | mpic_shutdown_ht_interrupt(mpic, src); |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 753 | mpic_mask_irq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 754 | } |
| 755 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 756 | static void mpic_end_ht_irq(struct irq_data *d) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 757 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 758 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 759 | unsigned int src = irqd_to_hwirq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 760 | |
| 761 | #ifdef DEBUG_IRQ |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 762 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 763 | #endif |
| 764 | /* We always EOI on end_irq() even for edge interrupts since that |
| 765 | * should only lower the priority, the MPIC should have properly |
| 766 | * latched another edge interrupt coming in anyway |
| 767 | */ |
| 768 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 769 | if (irqd_is_level_type(d)) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 770 | mpic_ht_end_irq(mpic, src); |
| 771 | mpic_eoi(mpic); |
| 772 | } |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 773 | #endif /* !CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 774 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 775 | #ifdef CONFIG_SMP |
| 776 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 777 | static void mpic_unmask_ipi(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 778 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 779 | struct mpic *mpic = mpic_from_ipi(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 780 | unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 781 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 782 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 783 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); |
| 784 | } |
| 785 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 786 | static void mpic_mask_ipi(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 787 | { |
| 788 | /* NEVER disable an IPI... that's just plain wrong! */ |
| 789 | } |
| 790 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 791 | static void mpic_end_ipi(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 792 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 793 | struct mpic *mpic = mpic_from_ipi(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 794 | |
| 795 | /* |
| 796 | * IPIs are marked IRQ_PER_CPU. This has the side effect of |
| 797 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from |
| 798 | * applying to them. We EOI them late to avoid re-entering. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 799 | */ |
| 800 | mpic_eoi(mpic); |
| 801 | } |
| 802 | |
| 803 | #endif /* CONFIG_SMP */ |
| 804 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 805 | static void mpic_unmask_tm(struct irq_data *d) |
| 806 | { |
| 807 | struct mpic *mpic = mpic_from_irq_data(d); |
| 808 | unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; |
| 809 | |
Dmitry Eremin-Solenikov | 77ef489 | 2011-05-30 01:56:09 +0000 | [diff] [blame] | 810 | DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src); |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 811 | mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK); |
| 812 | mpic_tm_read(src); |
| 813 | } |
| 814 | |
| 815 | static void mpic_mask_tm(struct irq_data *d) |
| 816 | { |
| 817 | struct mpic *mpic = mpic_from_irq_data(d); |
| 818 | unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; |
| 819 | |
| 820 | mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK); |
| 821 | mpic_tm_read(src); |
| 822 | } |
| 823 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 824 | int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
| 825 | bool force) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 826 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 827 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 828 | unsigned int src = irqd_to_hwirq(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 829 | |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 830 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
Yang Li | 38e1313 | 2009-12-16 20:18:11 +0000 | [diff] [blame] | 831 | int cpuid = irq_choose_cpu(cpumask); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 832 | |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 833 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
| 834 | } else { |
Milton Miller | 2a116f3 | 2011-05-10 19:29:02 +0000 | [diff] [blame] | 835 | u32 mask = cpumask_bits(cpumask)[0]; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 836 | |
Milton Miller | 2a116f3 | 2011-05-10 19:29:02 +0000 | [diff] [blame] | 837 | mask &= cpumask_bits(cpu_online_mask)[0]; |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 838 | |
| 839 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), |
Milton Miller | 2a116f3 | 2011-05-10 19:29:02 +0000 | [diff] [blame] | 840 | mpic_physmask(mask)); |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 841 | } |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 842 | |
| 843 | return 0; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 844 | } |
| 845 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 846 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 847 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 848 | /* Now convert sense value */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 849 | switch(type & IRQ_TYPE_SENSE_MASK) { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 850 | case IRQ_TYPE_EDGE_RISING: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 851 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
| 852 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 853 | case IRQ_TYPE_EDGE_FALLING: |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 854 | case IRQ_TYPE_EDGE_BOTH: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 855 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
| 856 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 857 | case IRQ_TYPE_LEVEL_HIGH: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 858 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
| 859 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 860 | case IRQ_TYPE_LEVEL_LOW: |
| 861 | default: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 862 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
| 863 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 864 | } |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 865 | } |
| 866 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 867 | int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 868 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 869 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 870 | unsigned int src = irqd_to_hwirq(d); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 871 | unsigned int vecpri, vold, vnew; |
| 872 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 873 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 874 | mpic, d->irq, src, flow_type); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 875 | |
Kyle Moffett | 5019609 | 2011-12-22 10:19:12 +0000 | [diff] [blame] | 876 | if (src >= mpic->num_sources) |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 877 | return -EINVAL; |
| 878 | |
| 879 | if (flow_type == IRQ_TYPE_NONE) |
| 880 | if (mpic->senses && src < mpic->senses_count) |
| 881 | flow_type = mpic->senses[src]; |
| 882 | if (flow_type == IRQ_TYPE_NONE) |
| 883 | flow_type = IRQ_TYPE_LEVEL_LOW; |
| 884 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 885 | irqd_set_trigger_type(d, flow_type); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 886 | |
| 887 | if (mpic_is_ht_interrupt(mpic, src)) |
| 888 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | |
| 889 | MPIC_VECPRI_SENSE_EDGE; |
| 890 | else |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 891 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 892 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 893 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
| 894 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | |
| 895 | MPIC_INFO(VECPRI_SENSE_MASK)); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 896 | vnew |= vecpri; |
| 897 | if (vold != vnew) |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 898 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 899 | |
Justin P. Mattock | e075cd7 | 2011-11-21 06:43:26 +0000 | [diff] [blame] | 900 | return IRQ_SET_MASK_OK_NOCOPY; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 901 | } |
| 902 | |
Olof Johansson | 38958dd | 2007-12-12 17:44:46 +1100 | [diff] [blame] | 903 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
| 904 | { |
| 905 | struct mpic *mpic = mpic_from_irq(virq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 906 | unsigned int src = virq_to_hw(virq); |
Olof Johansson | 38958dd | 2007-12-12 17:44:46 +1100 | [diff] [blame] | 907 | unsigned int vecpri; |
| 908 | |
| 909 | DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", |
| 910 | mpic, virq, src, vector); |
| 911 | |
Kyle Moffett | 5019609 | 2011-12-22 10:19:12 +0000 | [diff] [blame] | 912 | if (src >= mpic->num_sources) |
Olof Johansson | 38958dd | 2007-12-12 17:44:46 +1100 | [diff] [blame] | 913 | return; |
| 914 | |
| 915 | vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
| 916 | vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); |
| 917 | vecpri |= vector; |
| 918 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
| 919 | } |
| 920 | |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 921 | void mpic_set_destination(unsigned int virq, unsigned int cpuid) |
| 922 | { |
| 923 | struct mpic *mpic = mpic_from_irq(virq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 924 | unsigned int src = virq_to_hw(virq); |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 925 | |
| 926 | DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", |
| 927 | mpic, virq, src, cpuid); |
| 928 | |
Kyle Moffett | 5019609 | 2011-12-22 10:19:12 +0000 | [diff] [blame] | 929 | if (src >= mpic->num_sources) |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 930 | return; |
| 931 | |
| 932 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
| 933 | } |
| 934 | |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 935 | static struct irq_chip mpic_irq_chip = { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 936 | .irq_mask = mpic_mask_irq, |
| 937 | .irq_unmask = mpic_unmask_irq, |
| 938 | .irq_eoi = mpic_end_irq, |
| 939 | .irq_set_type = mpic_set_irq_type, |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 940 | }; |
| 941 | |
| 942 | #ifdef CONFIG_SMP |
| 943 | static struct irq_chip mpic_ipi_chip = { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 944 | .irq_mask = mpic_mask_ipi, |
| 945 | .irq_unmask = mpic_unmask_ipi, |
| 946 | .irq_eoi = mpic_end_ipi, |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 947 | }; |
| 948 | #endif /* CONFIG_SMP */ |
| 949 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 950 | static struct irq_chip mpic_tm_chip = { |
| 951 | .irq_mask = mpic_mask_tm, |
| 952 | .irq_unmask = mpic_unmask_tm, |
| 953 | .irq_eoi = mpic_end_irq, |
| 954 | }; |
| 955 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 956 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 957 | static struct irq_chip mpic_irq_ht_chip = { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 958 | .irq_startup = mpic_startup_ht_irq, |
| 959 | .irq_shutdown = mpic_shutdown_ht_irq, |
| 960 | .irq_mask = mpic_mask_irq, |
| 961 | .irq_unmask = mpic_unmask_ht_irq, |
| 962 | .irq_eoi = mpic_end_ht_irq, |
| 963 | .irq_set_type = mpic_set_irq_type, |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 964 | }; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 965 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 966 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 967 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 968 | static int mpic_host_match(struct irq_domain *h, struct device_node *node) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 969 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 970 | /* Exact match, unless mpic node is NULL */ |
Michael Ellerman | 52964f8 | 2007-08-28 18:47:54 +1000 | [diff] [blame] | 971 | return h->of_node == NULL || h->of_node == node; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 972 | } |
| 973 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 974 | static int mpic_host_map(struct irq_domain *h, unsigned int virq, |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 975 | irq_hw_number_t hw) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 976 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 977 | struct mpic *mpic = h->host_data; |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 978 | struct irq_chip *chip; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 979 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 980 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 981 | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 982 | if (hw == mpic->spurious_vec) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 983 | return -EINVAL; |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 984 | if (mpic->protected && test_bit(hw, mpic->protected)) |
| 985 | return -EINVAL; |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 986 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 987 | #ifdef CONFIG_SMP |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 988 | else if (hw >= mpic->ipi_vecs[0]) { |
Kyle Moffett | be8bec5 | 2011-12-02 06:28:03 +0000 | [diff] [blame] | 989 | WARN_ON(mpic->flags & MPIC_SECONDARY); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 990 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 991 | DBG("mpic: mapping as IPI\n"); |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 992 | irq_set_chip_data(virq, mpic); |
| 993 | irq_set_chip_and_handler(virq, &mpic->hc_ipi, |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 994 | handle_percpu_irq); |
| 995 | return 0; |
| 996 | } |
| 997 | #endif /* CONFIG_SMP */ |
| 998 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 999 | if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { |
Kyle Moffett | be8bec5 | 2011-12-02 06:28:03 +0000 | [diff] [blame] | 1000 | WARN_ON(mpic->flags & MPIC_SECONDARY); |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1001 | |
| 1002 | DBG("mpic: mapping as timer\n"); |
| 1003 | irq_set_chip_data(virq, mpic); |
| 1004 | irq_set_chip_and_handler(virq, &mpic->hc_tm, |
| 1005 | handle_fasteoi_irq); |
| 1006 | return 0; |
| 1007 | } |
| 1008 | |
Kyle Moffett | 5019609 | 2011-12-22 10:19:12 +0000 | [diff] [blame] | 1009 | if (hw >= mpic->num_sources) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1010 | return -EINVAL; |
| 1011 | |
Michael Ellerman | a7de7c7 | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 1012 | mpic_msi_reserve_hwirq(mpic, hw); |
| 1013 | |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 1014 | /* Default chip */ |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1015 | chip = &mpic->hc_irq; |
| 1016 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 1017 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1018 | /* Check for HT interrupts, override vecpri */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 1019 | if (mpic_is_ht_interrupt(mpic, hw)) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1020 | chip = &mpic->hc_ht_irq; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 1021 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1022 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1023 | DBG("mpic: mapping to irq chip @%p\n", chip); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1024 | |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 1025 | irq_set_chip_data(virq, mpic); |
| 1026 | irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 1027 | |
| 1028 | /* Set default irq type */ |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 1029 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 1030 | |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1031 | /* If the MPIC was reset, then all vectors have already been |
| 1032 | * initialized. Otherwise, a per source lazy initialization |
| 1033 | * is done here. |
| 1034 | */ |
| 1035 | if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1036 | mpic_set_vector(virq, hw); |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 1037 | mpic_set_destination(virq, mpic_processor_id(mpic)); |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1038 | mpic_irq_set_priority(virq, 8); |
| 1039 | } |
| 1040 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1041 | return 0; |
| 1042 | } |
| 1043 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 1044 | static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct, |
Roman Fietze | 40d50cf | 2009-12-08 02:39:50 +0000 | [diff] [blame] | 1045 | const u32 *intspec, unsigned int intsize, |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1046 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
| 1047 | |
| 1048 | { |
Scott Wood | 22d168c | 2011-03-24 16:43:54 -0500 | [diff] [blame] | 1049 | struct mpic *mpic = h->host_data; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1050 | static unsigned char map_mpic_senses[4] = { |
| 1051 | IRQ_TYPE_EDGE_RISING, |
| 1052 | IRQ_TYPE_LEVEL_LOW, |
| 1053 | IRQ_TYPE_LEVEL_HIGH, |
| 1054 | IRQ_TYPE_EDGE_FALLING, |
| 1055 | }; |
| 1056 | |
| 1057 | *out_hwirq = intspec[0]; |
Scott Wood | 22d168c | 2011-03-24 16:43:54 -0500 | [diff] [blame] | 1058 | if (intsize >= 4 && (mpic->flags & MPIC_FSL)) { |
| 1059 | /* |
| 1060 | * Freescale MPIC with extended intspec: |
| 1061 | * First two cells are as usual. Third specifies |
| 1062 | * an "interrupt type". Fourth is type-specific data. |
| 1063 | * |
| 1064 | * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt |
| 1065 | */ |
| 1066 | switch (intspec[2]) { |
| 1067 | case 0: |
| 1068 | case 1: /* no EISR/EIMR support for now, treat as shared IRQ */ |
| 1069 | break; |
| 1070 | case 2: |
| 1071 | if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) |
| 1072 | return -EINVAL; |
| 1073 | |
| 1074 | *out_hwirq = mpic->ipi_vecs[intspec[0]]; |
| 1075 | break; |
| 1076 | case 3: |
| 1077 | if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs)) |
| 1078 | return -EINVAL; |
| 1079 | |
| 1080 | *out_hwirq = mpic->timer_vecs[intspec[0]]; |
| 1081 | break; |
| 1082 | default: |
| 1083 | pr_debug("%s: unknown irq type %u\n", |
| 1084 | __func__, intspec[2]); |
| 1085 | return -EINVAL; |
| 1086 | } |
| 1087 | |
| 1088 | *out_flags = map_mpic_senses[intspec[1] & 3]; |
| 1089 | } else if (intsize > 1) { |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1090 | u32 mask = 0x3; |
| 1091 | |
| 1092 | /* Apple invented a new race of encoding on machines with |
| 1093 | * an HT APIC. They encode, among others, the index within |
| 1094 | * the HT APIC. We don't care about it here since thankfully, |
| 1095 | * it appears that they have the APIC already properly |
| 1096 | * configured, and thus our current fixup code that reads the |
| 1097 | * APIC config works fine. However, we still need to mask out |
| 1098 | * bits in the specifier to make sure we only get bit 0 which |
| 1099 | * is the level/edge bit (the only sense bit exposed by Apple), |
| 1100 | * as their bit 1 means something else. |
| 1101 | */ |
| 1102 | if (machine_is(powermac)) |
| 1103 | mask = 0x1; |
| 1104 | *out_flags = map_mpic_senses[intspec[1] & mask]; |
| 1105 | } else |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1106 | *out_flags = IRQ_TYPE_NONE; |
| 1107 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1108 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
| 1109 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); |
| 1110 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1111 | return 0; |
| 1112 | } |
| 1113 | |
Kyle Moffett | 09dc34a | 2011-12-02 06:28:07 +0000 | [diff] [blame] | 1114 | /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */ |
| 1115 | static void mpic_cascade(unsigned int irq, struct irq_desc *desc) |
| 1116 | { |
| 1117 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 1118 | struct mpic *mpic = irq_desc_get_handler_data(desc); |
| 1119 | unsigned int virq; |
| 1120 | |
| 1121 | BUG_ON(!(mpic->flags & MPIC_SECONDARY)); |
| 1122 | |
| 1123 | virq = mpic_get_one_irq(mpic); |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 1124 | if (virq) |
Kyle Moffett | 09dc34a | 2011-12-02 06:28:07 +0000 | [diff] [blame] | 1125 | generic_handle_irq(virq); |
| 1126 | |
| 1127 | chip->irq_eoi(&desc->irq_data); |
| 1128 | } |
| 1129 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 1130 | static struct irq_domain_ops mpic_host_ops = { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1131 | .match = mpic_host_match, |
| 1132 | .map = mpic_host_map, |
| 1133 | .xlate = mpic_host_xlate, |
| 1134 | }; |
| 1135 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1136 | /* |
| 1137 | * Exported functions |
| 1138 | */ |
| 1139 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1140 | struct mpic * __init mpic_alloc(struct device_node *node, |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1141 | phys_addr_t phys_addr, |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1142 | unsigned int flags, |
| 1143 | unsigned int isu_size, |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1144 | unsigned int irq_count, |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1145 | const char *name) |
| 1146 | { |
Kyle Moffett | 5bdb6f2 | 2011-12-02 06:28:00 +0000 | [diff] [blame] | 1147 | int i, psize, intvec_top; |
| 1148 | struct mpic *mpic; |
| 1149 | u32 greg_feature; |
| 1150 | const char *vers; |
| 1151 | const u32 *psrc; |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1152 | u32 last_irq; |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1153 | |
Kyle Moffett | 996983b | 2011-12-02 06:28:02 +0000 | [diff] [blame] | 1154 | /* Default MPIC search parameters */ |
| 1155 | static const struct of_device_id __initconst mpic_device_id[] = { |
| 1156 | { .type = "open-pic", }, |
| 1157 | { .compatible = "open-pic", }, |
| 1158 | {}, |
| 1159 | }; |
| 1160 | |
| 1161 | /* |
| 1162 | * If we were not passed a device-tree node, then perform the default |
| 1163 | * search for standardized a standardized OpenPIC. |
| 1164 | */ |
| 1165 | if (node) { |
| 1166 | node = of_node_get(node); |
| 1167 | } else { |
| 1168 | node = of_find_matching_node(NULL, mpic_device_id); |
| 1169 | if (!node) |
| 1170 | return NULL; |
| 1171 | } |
Kyle Moffett | 5bdb6f2 | 2011-12-02 06:28:00 +0000 | [diff] [blame] | 1172 | |
| 1173 | /* Pick the physical address from the device tree if unspecified */ |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1174 | if (!phys_addr) { |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1175 | /* Check if it is DCR-based */ |
| 1176 | if (of_get_property(node, "dcr-reg", NULL)) { |
| 1177 | flags |= MPIC_USES_DCR; |
| 1178 | } else { |
| 1179 | struct resource r; |
| 1180 | if (of_address_to_resource(node, 0, &r)) |
Kyle Moffett | 996983b | 2011-12-02 06:28:02 +0000 | [diff] [blame] | 1181 | goto err_of_node_put; |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1182 | phys_addr = r.start; |
| 1183 | } |
| 1184 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1185 | |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1186 | /* Read extra device-tree properties into the flags variable */ |
| 1187 | if (of_get_property(node, "big-endian", NULL)) |
| 1188 | flags |= MPIC_BIG_ENDIAN; |
| 1189 | if (of_get_property(node, "pic-no-reset", NULL)) |
| 1190 | flags |= MPIC_NO_RESET; |
Kyle Moffett | 9ca163c | 2011-12-22 10:19:11 +0000 | [diff] [blame] | 1191 | if (of_get_property(node, "single-cpu-affinity", NULL)) |
| 1192 | flags |= MPIC_SINGLE_DEST_CPU; |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1193 | if (of_device_is_compatible(node, "fsl,mpic")) |
| 1194 | flags |= MPIC_FSL; |
| 1195 | |
Kumar Gala | 85355bb | 2009-06-18 22:01:20 +0000 | [diff] [blame] | 1196 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1197 | if (mpic == NULL) |
Kyle Moffett | 996983b | 2011-12-02 06:28:02 +0000 | [diff] [blame] | 1198 | goto err_of_node_put; |
Kumar Gala | 85355bb | 2009-06-18 22:01:20 +0000 | [diff] [blame] | 1199 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1200 | mpic->name = name; |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1201 | mpic->node = node; |
Kyle Moffett | e7a9867 | 2011-12-02 06:28:01 +0000 | [diff] [blame] | 1202 | mpic->paddr = phys_addr; |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1203 | mpic->flags = flags; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1204 | |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 1205 | mpic->hc_irq = mpic_irq_chip; |
Thomas Gleixner | b27df67 | 2009-11-18 23:44:21 +0000 | [diff] [blame] | 1206 | mpic->hc_irq.name = name; |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1207 | if (!(mpic->flags & MPIC_SECONDARY)) |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 1208 | mpic->hc_irq.irq_set_affinity = mpic_set_affinity; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 1209 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 1210 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
Thomas Gleixner | b27df67 | 2009-11-18 23:44:21 +0000 | [diff] [blame] | 1211 | mpic->hc_ht_irq.name = name; |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1212 | if (!(mpic->flags & MPIC_SECONDARY)) |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 1213 | mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 1214 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1215 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1216 | #ifdef CONFIG_SMP |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 1217 | mpic->hc_ipi = mpic_ipi_chip; |
Thomas Gleixner | b27df67 | 2009-11-18 23:44:21 +0000 | [diff] [blame] | 1218 | mpic->hc_ipi.name = name; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1219 | #endif /* CONFIG_SMP */ |
| 1220 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1221 | mpic->hc_tm = mpic_tm_chip; |
| 1222 | mpic->hc_tm.name = name; |
| 1223 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1224 | mpic->num_sources = 0; /* so far */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1225 | |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1226 | if (mpic->flags & MPIC_LARGE_VECTORS) |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1227 | intvec_top = 2047; |
| 1228 | else |
| 1229 | intvec_top = 255; |
| 1230 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1231 | mpic->timer_vecs[0] = intvec_top - 12; |
| 1232 | mpic->timer_vecs[1] = intvec_top - 11; |
| 1233 | mpic->timer_vecs[2] = intvec_top - 10; |
| 1234 | mpic->timer_vecs[3] = intvec_top - 9; |
| 1235 | mpic->timer_vecs[4] = intvec_top - 8; |
| 1236 | mpic->timer_vecs[5] = intvec_top - 7; |
| 1237 | mpic->timer_vecs[6] = intvec_top - 6; |
| 1238 | mpic->timer_vecs[7] = intvec_top - 5; |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1239 | mpic->ipi_vecs[0] = intvec_top - 4; |
| 1240 | mpic->ipi_vecs[1] = intvec_top - 3; |
| 1241 | mpic->ipi_vecs[2] = intvec_top - 2; |
| 1242 | mpic->ipi_vecs[3] = intvec_top - 1; |
| 1243 | mpic->spurious_vec = intvec_top; |
| 1244 | |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1245 | /* Look for protected sources */ |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1246 | psrc = of_get_property(mpic->node, "protected-sources", &psize); |
Kyle Moffett | 5bdb6f2 | 2011-12-02 06:28:00 +0000 | [diff] [blame] | 1247 | if (psrc) { |
| 1248 | /* Allocate a bitmap with one bit per interrupt */ |
| 1249 | unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1); |
| 1250 | mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL); |
| 1251 | BUG_ON(mpic->protected == NULL); |
| 1252 | for (i = 0; i < psize/sizeof(u32); i++) { |
| 1253 | if (psrc[i] > intvec_top) |
| 1254 | continue; |
| 1255 | __set_bit(psrc[i], mpic->protected); |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1256 | } |
| 1257 | } |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1258 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1259 | #ifdef CONFIG_MPIC_WEIRD |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1260 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)]; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1261 | #endif |
| 1262 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1263 | /* default register type */ |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1264 | if (mpic->flags & MPIC_BIG_ENDIAN) |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1265 | mpic->reg_type = mpic_access_mmio_be; |
| 1266 | else |
| 1267 | mpic->reg_type = mpic_access_mmio_le; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1268 | |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1269 | /* |
| 1270 | * An MPIC with a "dcr-reg" property must be accessed that way, but |
| 1271 | * only if the kernel includes DCR support. |
| 1272 | */ |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1273 | #ifdef CONFIG_PPC_DCR |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1274 | if (mpic->flags & MPIC_USES_DCR) |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1275 | mpic->reg_type = mpic_access_dcr; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1276 | #else |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1277 | BUG_ON(mpic->flags & MPIC_USES_DCR); |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1278 | #endif |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1279 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1280 | /* Map the global registers */ |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1281 | mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
| 1282 | mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1283 | |
| 1284 | /* Reset */ |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1285 | |
| 1286 | /* When using a device-node, reset requests are only honored if the MPIC |
| 1287 | * is allowed to reset. |
| 1288 | */ |
Kyle Moffett | e55d7f7 | 2011-12-22 10:19:14 +0000 | [diff] [blame] | 1289 | if (!(mpic->flags & MPIC_NO_RESET)) { |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1290 | printk(KERN_DEBUG "mpic: Resetting\n"); |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1291 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1292 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1293 | | MPIC_GREG_GCONF_RESET); |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1294 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1295 | & MPIC_GREG_GCONF_RESET) |
| 1296 | mb(); |
| 1297 | } |
| 1298 | |
Kumar Gala | d91e4ea | 2009-01-07 15:53:29 -0600 | [diff] [blame] | 1299 | /* CoreInt */ |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1300 | if (mpic->flags & MPIC_ENABLE_COREINT) |
Kumar Gala | d91e4ea | 2009-01-07 15:53:29 -0600 | [diff] [blame] | 1301 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1302 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1303 | | MPIC_GREG_GCONF_COREINT); |
| 1304 | |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1305 | if (mpic->flags & MPIC_ENABLE_MCK) |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1306 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1307 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1308 | | MPIC_GREG_GCONF_MCK); |
| 1309 | |
Timur Tabi | 14b9247 | 2011-07-08 11:12:42 +0000 | [diff] [blame] | 1310 | /* |
Timur Tabi | 14b9247 | 2011-07-08 11:12:42 +0000 | [diff] [blame] | 1311 | * The MPIC driver will crash if there are more cores than we |
| 1312 | * can initialize, so we may as well catch that problem here. |
| 1313 | */ |
| 1314 | BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS); |
| 1315 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1316 | /* Map the per-CPU registers */ |
Timur Tabi | 14b9247 | 2011-07-08 11:12:42 +0000 | [diff] [blame] | 1317 | for_each_possible_cpu(i) { |
| 1318 | unsigned int cpu = get_hard_smp_processor_id(i); |
| 1319 | |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1320 | mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu], |
Timur Tabi | 14b9247 | 2011-07-08 11:12:42 +0000 | [diff] [blame] | 1321 | MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE), |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1322 | 0x1000); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1323 | } |
| 1324 | |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1325 | /* |
| 1326 | * Read feature register. For non-ISU MPICs, num sources as well. On |
| 1327 | * ISU MPICs, sources are counted as ISUs are added |
| 1328 | */ |
| 1329 | greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); |
| 1330 | |
| 1331 | /* |
| 1332 | * By default, the last source number comes from the MPIC, but the |
| 1333 | * device-tree and board support code can override it on buggy hw. |
Benjamin Herrenschmidt | fe83364 | 2012-02-22 13:50:13 +0000 | [diff] [blame] | 1334 | * If we get passed an isu_size (multi-isu MPIC) then we use that |
| 1335 | * as a default instead of the value read from the HW. |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1336 | */ |
| 1337 | last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) |
Benjamin Herrenschmidt | fe83364 | 2012-02-22 13:50:13 +0000 | [diff] [blame] | 1338 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT; |
| 1339 | if (isu_size) |
| 1340 | last_irq = isu_size * MPIC_MAX_ISU - 1; |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1341 | of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq); |
| 1342 | if (irq_count) |
| 1343 | last_irq = irq_count - 1; |
| 1344 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1345 | /* Initialize main ISU if none provided */ |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1346 | if (!isu_size) { |
| 1347 | isu_size = last_irq + 1; |
| 1348 | mpic->num_sources = isu_size; |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1349 | mpic_map(mpic, mpic->paddr, &mpic->isus[0], |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1350 | MPIC_INFO(IRQ_BASE), |
| 1351 | MPIC_INFO(IRQ_STRIDE) * isu_size); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1352 | } |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1353 | |
| 1354 | mpic->isu_size = isu_size; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1355 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); |
| 1356 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; |
| 1357 | |
Grant Likely | a8db8cf | 2012-02-14 14:06:54 -0700 | [diff] [blame] | 1358 | mpic->irqhost = irq_domain_add_linear(mpic->node, |
Linus Torvalds | 5375871 | 2012-03-21 18:55:10 -0700 | [diff] [blame] | 1359 | last_irq + 1, |
Grant Likely | a8db8cf | 2012-02-14 14:06:54 -0700 | [diff] [blame] | 1360 | &mpic_host_ops, mpic); |
Kyle Moffett | 996983b | 2011-12-02 06:28:02 +0000 | [diff] [blame] | 1361 | |
| 1362 | /* |
| 1363 | * FIXME: The code leaks the MPIC object and mappings here; this |
| 1364 | * is very unlikely to fail but it ought to be fixed anyways. |
| 1365 | */ |
Kumar Gala | 31207da | 2009-05-08 12:08:20 +0000 | [diff] [blame] | 1366 | if (mpic->irqhost == NULL) |
| 1367 | return NULL; |
| 1368 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1369 | /* Display version */ |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 1370 | switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1371 | case 1: |
| 1372 | vers = "1.0"; |
| 1373 | break; |
| 1374 | case 2: |
| 1375 | vers = "1.2"; |
| 1376 | break; |
| 1377 | case 3: |
| 1378 | vers = "1.3"; |
| 1379 | break; |
| 1380 | default: |
| 1381 | vers = "<unknown>"; |
| 1382 | break; |
| 1383 | } |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1384 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
| 1385 | " max %d CPUs\n", |
Kyle Moffett | e7a9867 | 2011-12-02 06:28:01 +0000 | [diff] [blame] | 1386 | name, vers, (unsigned long long)mpic->paddr, num_possible_cpus()); |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1387 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", |
| 1388 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1389 | |
| 1390 | mpic->next = mpics; |
| 1391 | mpics = mpic; |
| 1392 | |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1393 | if (!(mpic->flags & MPIC_SECONDARY)) { |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1394 | mpic_primary = mpic; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1395 | irq_set_default_host(mpic->irqhost); |
| 1396 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1397 | |
| 1398 | return mpic; |
Kyle Moffett | 996983b | 2011-12-02 06:28:02 +0000 | [diff] [blame] | 1399 | |
| 1400 | err_of_node_put: |
| 1401 | of_node_put(node); |
| 1402 | return NULL; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1403 | } |
| 1404 | |
| 1405 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1406 | phys_addr_t paddr) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1407 | { |
| 1408 | unsigned int isu_first = isu_num * mpic->isu_size; |
| 1409 | |
| 1410 | BUG_ON(isu_num >= MPIC_MAX_ISU); |
| 1411 | |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1412 | mpic_map(mpic, |
Benjamin Herrenschmidt | 5a2642f | 2009-06-22 16:47:59 +0000 | [diff] [blame] | 1413 | paddr, &mpic->isus[isu_num], 0, |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1414 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
Benjamin Herrenschmidt | 5a2642f | 2009-06-22 16:47:59 +0000 | [diff] [blame] | 1415 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1416 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
| 1417 | mpic->num_sources = isu_first + mpic->isu_size; |
| 1418 | } |
| 1419 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1420 | void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) |
| 1421 | { |
| 1422 | mpic->senses = senses; |
| 1423 | mpic->senses_count = count; |
| 1424 | } |
| 1425 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1426 | void __init mpic_init(struct mpic *mpic) |
| 1427 | { |
Kyle Moffett | 09dc34a | 2011-12-02 06:28:07 +0000 | [diff] [blame] | 1428 | int i, cpu; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1429 | |
| 1430 | BUG_ON(mpic->num_sources == 0); |
| 1431 | |
| 1432 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); |
| 1433 | |
| 1434 | /* Set current processor priority to max */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1435 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1436 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1437 | /* Initialize timers to our reserved vectors and mask them for now */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1438 | for (i = 0; i < 4; i++) { |
| 1439 | mpic_write(mpic->tmregs, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1440 | i * MPIC_INFO(TIMER_STRIDE) + |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1441 | MPIC_INFO(TIMER_DESTINATION), |
| 1442 | 1 << hard_smp_processor_id()); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1443 | mpic_write(mpic->tmregs, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1444 | i * MPIC_INFO(TIMER_STRIDE) + |
| 1445 | MPIC_INFO(TIMER_VECTOR_PRI), |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1446 | MPIC_VECPRI_MASK | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1447 | (9 << MPIC_VECPRI_PRIORITY_SHIFT) | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1448 | (mpic->timer_vecs[0] + i)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1449 | } |
| 1450 | |
| 1451 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ |
| 1452 | mpic_test_broken_ipi(mpic); |
| 1453 | for (i = 0; i < 4; i++) { |
| 1454 | mpic_ipi_write(i, |
| 1455 | MPIC_VECPRI_MASK | |
| 1456 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1457 | (mpic->ipi_vecs[0] + i)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1458 | } |
| 1459 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1460 | /* Do the HT PIC fixups on U3 broken mpic */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1461 | DBG("MPIC flags: %x\n", mpic->flags); |
Kyle Moffett | be8bec5 | 2011-12-02 06:28:03 +0000 | [diff] [blame] | 1462 | if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1463 | mpic_scan_ht_pics(mpic); |
Michael Ellerman | 05af7bd | 2007-05-08 12:58:37 +1000 | [diff] [blame] | 1464 | mpic_u3msi_init(mpic); |
| 1465 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1466 | |
Olof Johansson | 38958dd | 2007-12-12 17:44:46 +1100 | [diff] [blame] | 1467 | mpic_pasemi_msi_init(mpic); |
| 1468 | |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 1469 | cpu = mpic_processor_id(mpic); |
Arnd Bergmann | cc353c3 | 2008-11-28 09:51:23 +0000 | [diff] [blame] | 1470 | |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1471 | if (!(mpic->flags & MPIC_NO_RESET)) { |
| 1472 | for (i = 0; i < mpic->num_sources; i++) { |
| 1473 | /* start with vector = source number, and masked */ |
| 1474 | u32 vecpri = MPIC_VECPRI_MASK | i | |
| 1475 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1476 | |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1477 | /* check if protected */ |
| 1478 | if (mpic->protected && test_bit(i, mpic->protected)) |
| 1479 | continue; |
| 1480 | /* init hw */ |
| 1481 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
| 1482 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); |
| 1483 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1484 | } |
| 1485 | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1486 | /* Init spurious vector */ |
| 1487 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1488 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1489 | /* Disable 8259 passthrough, if supported */ |
| 1490 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) |
| 1491 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1492 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1493 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1494 | |
Olof Johansson | d87bf3b | 2007-12-27 22:16:29 -0600 | [diff] [blame] | 1495 | if (mpic->flags & MPIC_NO_BIAS) |
| 1496 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1497 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1498 | | MPIC_GREG_GCONF_NO_BIAS); |
| 1499 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1500 | /* Set current processor priority to 0 */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1501 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1502 | |
| 1503 | #ifdef CONFIG_PM |
| 1504 | /* allocate memory to save mpic state */ |
Anton Vorontsov | ea96025 | 2009-07-01 10:59:57 +0000 | [diff] [blame] | 1505 | mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), |
| 1506 | GFP_KERNEL); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1507 | BUG_ON(mpic->save_data == NULL); |
| 1508 | #endif |
Kyle Moffett | 09dc34a | 2011-12-02 06:28:07 +0000 | [diff] [blame] | 1509 | |
| 1510 | /* Check if this MPIC is chained from a parent interrupt controller */ |
| 1511 | if (mpic->flags & MPIC_SECONDARY) { |
| 1512 | int virq = irq_of_parse_and_map(mpic->node, 0); |
| 1513 | if (virq != NO_IRQ) { |
| 1514 | printk(KERN_INFO "%s: hooking up to IRQ %d\n", |
| 1515 | mpic->node->full_name, virq); |
| 1516 | irq_set_handler_data(virq, mpic); |
| 1517 | irq_set_chained_handler(virq, &mpic_cascade); |
| 1518 | } |
| 1519 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1520 | } |
| 1521 | |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1522 | void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) |
| 1523 | { |
| 1524 | u32 v; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1525 | |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1526 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
| 1527 | v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; |
| 1528 | v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); |
| 1529 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); |
| 1530 | } |
| 1531 | |
| 1532 | void __init mpic_set_serial_int(struct mpic *mpic, int enable) |
| 1533 | { |
Benjamin Herrenschmidt | ba1826e | 2006-07-05 15:36:15 +1000 | [diff] [blame] | 1534 | unsigned long flags; |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1535 | u32 v; |
| 1536 | |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1537 | raw_spin_lock_irqsave(&mpic_lock, flags); |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1538 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
| 1539 | if (enable) |
| 1540 | v |= MPIC_GREG_GLOBAL_CONF_1_SIE; |
| 1541 | else |
| 1542 | v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; |
| 1543 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1544 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1545 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1546 | |
| 1547 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) |
| 1548 | { |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 1549 | struct mpic *mpic = mpic_find(irq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 1550 | unsigned int src = virq_to_hw(irq); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1551 | unsigned long flags; |
| 1552 | u32 reg; |
| 1553 | |
Stephen Rothwell | 06a901c | 2008-05-21 16:24:31 +1000 | [diff] [blame] | 1554 | if (!mpic) |
| 1555 | return; |
| 1556 | |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1557 | raw_spin_lock_irqsave(&mpic_lock, flags); |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 1558 | if (mpic_is_ipi(mpic, irq)) { |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1559 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 1560 | ~MPIC_VECPRI_PRIORITY_MASK; |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1561 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1562 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1563 | } else if (mpic_is_tm(mpic, irq)) { |
| 1564 | reg = mpic_tm_read(src - mpic->timer_vecs[0]) & |
| 1565 | ~MPIC_VECPRI_PRIORITY_MASK; |
| 1566 | mpic_tm_write(src - mpic->timer_vecs[0], |
| 1567 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1568 | } else { |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1569 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 1570 | & ~MPIC_VECPRI_PRIORITY_MASK; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1571 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1572 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
| 1573 | } |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1574 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1575 | } |
| 1576 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1577 | void mpic_setup_this_cpu(void) |
| 1578 | { |
| 1579 | #ifdef CONFIG_SMP |
| 1580 | struct mpic *mpic = mpic_primary; |
| 1581 | unsigned long flags; |
| 1582 | u32 msk = 1 << hard_smp_processor_id(); |
| 1583 | unsigned int i; |
| 1584 | |
| 1585 | BUG_ON(mpic == NULL); |
| 1586 | |
| 1587 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); |
| 1588 | |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1589 | raw_spin_lock_irqsave(&mpic_lock, flags); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1590 | |
| 1591 | /* let the mpic know we want intrs. default affinity is 0xffffffff |
| 1592 | * until changed via /proc. That's how it's done on x86. If we want |
| 1593 | * it differently, then we should make sure we also change the default |
Ingo Molnar | a53da52 | 2006-06-29 02:24:38 -0700 | [diff] [blame] | 1594 | * values of irq_desc[].affinity in irq.c. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1595 | */ |
| 1596 | if (distribute_irqs) { |
| 1597 | for (i = 0; i < mpic->num_sources ; i++) |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1598 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
| 1599 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1600 | } |
| 1601 | |
| 1602 | /* Set current processor priority to 0 */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1603 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1604 | |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1605 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1606 | #endif /* CONFIG_SMP */ |
| 1607 | } |
| 1608 | |
| 1609 | int mpic_cpu_get_priority(void) |
| 1610 | { |
| 1611 | struct mpic *mpic = mpic_primary; |
| 1612 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1613 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1614 | } |
| 1615 | |
| 1616 | void mpic_cpu_set_priority(int prio) |
| 1617 | { |
| 1618 | struct mpic *mpic = mpic_primary; |
| 1619 | |
| 1620 | prio &= MPIC_CPU_TASKPRI_MASK; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1621 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1622 | } |
| 1623 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1624 | void mpic_teardown_this_cpu(int secondary) |
| 1625 | { |
| 1626 | struct mpic *mpic = mpic_primary; |
| 1627 | unsigned long flags; |
| 1628 | u32 msk = 1 << hard_smp_processor_id(); |
| 1629 | unsigned int i; |
| 1630 | |
| 1631 | BUG_ON(mpic == NULL); |
| 1632 | |
| 1633 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1634 | raw_spin_lock_irqsave(&mpic_lock, flags); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1635 | |
| 1636 | /* let the mpic know we don't want intrs. */ |
| 1637 | for (i = 0; i < mpic->num_sources ; i++) |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1638 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
| 1639 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1640 | |
| 1641 | /* Set current processor priority to max */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1642 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
Valentine Barshak | 7132799 | 2008-04-03 23:09:43 +0400 | [diff] [blame] | 1643 | /* We need to EOI the IPI since not all platforms reset the MPIC |
| 1644 | * on boot and new interrupts wouldn't get delivered otherwise. |
| 1645 | */ |
| 1646 | mpic_eoi(mpic); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1647 | |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1648 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1649 | } |
| 1650 | |
| 1651 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1652 | static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1653 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1654 | u32 src; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1655 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1656 | src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1657 | #ifdef DEBUG_LOW |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1658 | DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1659 | #endif |
Josh Boyer | 5cddd2e | 2007-05-01 06:38:11 +1000 | [diff] [blame] | 1660 | if (unlikely(src == mpic->spurious_vec)) { |
| 1661 | if (mpic->flags & MPIC_SPV_EOI) |
| 1662 | mpic_eoi(mpic); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1663 | return NO_IRQ; |
Josh Boyer | 5cddd2e | 2007-05-01 06:38:11 +1000 | [diff] [blame] | 1664 | } |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1665 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
Christian Dietrich | 7646223 | 2011-06-04 05:36:54 +0000 | [diff] [blame] | 1666 | printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", |
| 1667 | mpic->name, (int)src); |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1668 | mpic_eoi(mpic); |
| 1669 | return NO_IRQ; |
| 1670 | } |
| 1671 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1672 | return irq_linear_revmap(mpic->irqhost, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1673 | } |
| 1674 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1675 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
| 1676 | { |
| 1677 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); |
| 1678 | } |
| 1679 | |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 1680 | unsigned int mpic_get_irq(void) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1681 | { |
| 1682 | struct mpic *mpic = mpic_primary; |
| 1683 | |
| 1684 | BUG_ON(mpic == NULL); |
| 1685 | |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 1686 | return mpic_get_one_irq(mpic); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1687 | } |
| 1688 | |
Kumar Gala | d91e4ea | 2009-01-07 15:53:29 -0600 | [diff] [blame] | 1689 | unsigned int mpic_get_coreint_irq(void) |
| 1690 | { |
| 1691 | #ifdef CONFIG_BOOKE |
| 1692 | struct mpic *mpic = mpic_primary; |
| 1693 | u32 src; |
| 1694 | |
| 1695 | BUG_ON(mpic == NULL); |
| 1696 | |
| 1697 | src = mfspr(SPRN_EPR); |
| 1698 | |
| 1699 | if (unlikely(src == mpic->spurious_vec)) { |
| 1700 | if (mpic->flags & MPIC_SPV_EOI) |
| 1701 | mpic_eoi(mpic); |
| 1702 | return NO_IRQ; |
| 1703 | } |
| 1704 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
Christian Dietrich | 7646223 | 2011-06-04 05:36:54 +0000 | [diff] [blame] | 1705 | printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", |
| 1706 | mpic->name, (int)src); |
Kumar Gala | d91e4ea | 2009-01-07 15:53:29 -0600 | [diff] [blame] | 1707 | return NO_IRQ; |
| 1708 | } |
| 1709 | |
| 1710 | return irq_linear_revmap(mpic->irqhost, src); |
| 1711 | #else |
| 1712 | return NO_IRQ; |
| 1713 | #endif |
| 1714 | } |
| 1715 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1716 | unsigned int mpic_get_mcirq(void) |
| 1717 | { |
| 1718 | struct mpic *mpic = mpic_primary; |
| 1719 | |
| 1720 | BUG_ON(mpic == NULL); |
| 1721 | |
| 1722 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); |
| 1723 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1724 | |
| 1725 | #ifdef CONFIG_SMP |
| 1726 | void mpic_request_ipis(void) |
| 1727 | { |
| 1728 | struct mpic *mpic = mpic_primary; |
Milton Miller | 78608dd | 2008-10-10 01:56:50 +0000 | [diff] [blame] | 1729 | int i; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1730 | BUG_ON(mpic == NULL); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1731 | |
Frans Pop | 8354be9 | 2010-02-06 07:47:20 +0000 | [diff] [blame] | 1732 | printk(KERN_INFO "mpic: requesting IPIs...\n"); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1733 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1734 | for (i = 0; i < 4; i++) { |
| 1735 | unsigned int vipi = irq_create_mapping(mpic->irqhost, |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1736 | mpic->ipi_vecs[0] + i); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1737 | if (vipi == NO_IRQ) { |
Milton Miller | 78608dd | 2008-10-10 01:56:50 +0000 | [diff] [blame] | 1738 | printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); |
| 1739 | continue; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1740 | } |
Milton Miller | 78608dd | 2008-10-10 01:56:50 +0000 | [diff] [blame] | 1741 | smp_request_message_ipi(vipi, i); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1742 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1743 | } |
Paul Mackerras | a9c5926 | 2005-10-20 17:09:51 +1000 | [diff] [blame] | 1744 | |
Milton Miller | 3caba98 | 2011-05-10 19:29:17 +0000 | [diff] [blame] | 1745 | void smp_mpic_message_pass(int cpu, int msg) |
Benjamin Herrenschmidt | 2ef613cb | 2010-05-06 18:01:46 +1000 | [diff] [blame] | 1746 | { |
| 1747 | struct mpic *mpic = mpic_primary; |
Milton Miller | 3caba98 | 2011-05-10 19:29:17 +0000 | [diff] [blame] | 1748 | u32 physmask; |
Benjamin Herrenschmidt | 2ef613cb | 2010-05-06 18:01:46 +1000 | [diff] [blame] | 1749 | |
| 1750 | BUG_ON(mpic == NULL); |
| 1751 | |
Paul Mackerras | a9c5926 | 2005-10-20 17:09:51 +1000 | [diff] [blame] | 1752 | /* make sure we're sending something that translates to an IPI */ |
| 1753 | if ((unsigned int)msg > 3) { |
| 1754 | printk("SMP %d: smp_message_pass: unknown msg %d\n", |
| 1755 | smp_processor_id(), msg); |
| 1756 | return; |
| 1757 | } |
Milton Miller | 3caba98 | 2011-05-10 19:29:17 +0000 | [diff] [blame] | 1758 | |
| 1759 | #ifdef DEBUG_IPI |
| 1760 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg); |
| 1761 | #endif |
| 1762 | |
| 1763 | physmask = 1 << get_hard_smp_processor_id(cpu); |
| 1764 | |
| 1765 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + |
| 1766 | msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask); |
Paul Mackerras | a9c5926 | 2005-10-20 17:09:51 +1000 | [diff] [blame] | 1767 | } |
Michael Ellerman | 775aeff | 2007-02-08 18:34:04 +1100 | [diff] [blame] | 1768 | |
| 1769 | int __init smp_mpic_probe(void) |
| 1770 | { |
| 1771 | int nr_cpus; |
| 1772 | |
| 1773 | DBG("smp_mpic_probe()...\n"); |
| 1774 | |
Benjamin Herrenschmidt | 2ef613cb | 2010-05-06 18:01:46 +1000 | [diff] [blame] | 1775 | nr_cpus = cpumask_weight(cpu_possible_mask); |
Michael Ellerman | 775aeff | 2007-02-08 18:34:04 +1100 | [diff] [blame] | 1776 | |
| 1777 | DBG("nr_cpus: %d\n", nr_cpus); |
| 1778 | |
| 1779 | if (nr_cpus > 1) |
| 1780 | mpic_request_ipis(); |
| 1781 | |
| 1782 | return nr_cpus; |
| 1783 | } |
| 1784 | |
| 1785 | void __devinit smp_mpic_setup_cpu(int cpu) |
| 1786 | { |
| 1787 | mpic_setup_this_cpu(); |
| 1788 | } |
Matthew McClintock | 66953eb | 2010-06-29 09:42:26 +0000 | [diff] [blame] | 1789 | |
| 1790 | void mpic_reset_core(int cpu) |
| 1791 | { |
| 1792 | struct mpic *mpic = mpic_primary; |
| 1793 | u32 pir; |
| 1794 | int cpuid = get_hard_smp_processor_id(cpu); |
Matthew McClintock | 44f16fc | 2011-10-26 13:46:57 -0500 | [diff] [blame] | 1795 | int i; |
Matthew McClintock | 66953eb | 2010-06-29 09:42:26 +0000 | [diff] [blame] | 1796 | |
| 1797 | /* Set target bit for core reset */ |
| 1798 | pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); |
| 1799 | pir |= (1 << cpuid); |
| 1800 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); |
| 1801 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); |
| 1802 | |
| 1803 | /* Restore target bit after reset complete */ |
| 1804 | pir &= ~(1 << cpuid); |
| 1805 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); |
| 1806 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); |
Matthew McClintock | 44f16fc | 2011-10-26 13:46:57 -0500 | [diff] [blame] | 1807 | |
| 1808 | /* Perform 15 EOI on each reset core to clear pending interrupts. |
| 1809 | * This is required for FSL CoreNet based devices */ |
| 1810 | if (mpic->flags & MPIC_FSL) { |
| 1811 | for (i = 0; i < 15; i++) { |
| 1812 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], |
| 1813 | MPIC_CPU_EOI, 0); |
| 1814 | } |
| 1815 | } |
Matthew McClintock | 66953eb | 2010-06-29 09:42:26 +0000 | [diff] [blame] | 1816 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1817 | #endif /* CONFIG_SMP */ |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1818 | |
| 1819 | #ifdef CONFIG_PM |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1820 | static void mpic_suspend_one(struct mpic *mpic) |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1821 | { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1822 | int i; |
| 1823 | |
| 1824 | for (i = 0; i < mpic->num_sources; i++) { |
| 1825 | mpic->save_data[i].vecprio = |
| 1826 | mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); |
| 1827 | mpic->save_data[i].dest = |
| 1828 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); |
| 1829 | } |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1830 | } |
| 1831 | |
| 1832 | static int mpic_suspend(void) |
| 1833 | { |
| 1834 | struct mpic *mpic = mpics; |
| 1835 | |
| 1836 | while (mpic) { |
| 1837 | mpic_suspend_one(mpic); |
| 1838 | mpic = mpic->next; |
| 1839 | } |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1840 | |
| 1841 | return 0; |
| 1842 | } |
| 1843 | |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1844 | static void mpic_resume_one(struct mpic *mpic) |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1845 | { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1846 | int i; |
| 1847 | |
| 1848 | for (i = 0; i < mpic->num_sources; i++) { |
| 1849 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), |
| 1850 | mpic->save_data[i].vecprio); |
| 1851 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
| 1852 | mpic->save_data[i].dest); |
| 1853 | |
| 1854 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Alastair Bridgewater | 7c9d936 | 2010-06-12 15:36:48 +0000 | [diff] [blame] | 1855 | if (mpic->fixups) { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1856 | struct mpic_irq_fixup *fixup = &mpic->fixups[i]; |
| 1857 | |
| 1858 | if (fixup->base) { |
| 1859 | /* we use the lowest bit in an inverted meaning */ |
| 1860 | if ((mpic->save_data[i].fixup_data & 1) == 0) |
| 1861 | continue; |
| 1862 | |
| 1863 | /* Enable and configure */ |
| 1864 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
| 1865 | |
| 1866 | writel(mpic->save_data[i].fixup_data & ~1, |
| 1867 | fixup->base + 4); |
| 1868 | } |
| 1869 | } |
| 1870 | #endif |
| 1871 | } /* end for loop */ |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1872 | } |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1873 | |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1874 | static void mpic_resume(void) |
| 1875 | { |
| 1876 | struct mpic *mpic = mpics; |
| 1877 | |
| 1878 | while (mpic) { |
| 1879 | mpic_resume_one(mpic); |
| 1880 | mpic = mpic->next; |
| 1881 | } |
| 1882 | } |
| 1883 | |
| 1884 | static struct syscore_ops mpic_syscore_ops = { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1885 | .resume = mpic_resume, |
| 1886 | .suspend = mpic_suspend, |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1887 | }; |
| 1888 | |
| 1889 | static int mpic_init_sys(void) |
| 1890 | { |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1891 | register_syscore_ops(&mpic_syscore_ops); |
| 1892 | return 0; |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1893 | } |
| 1894 | |
| 1895 | device_initcall(mpic_init_sys); |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1896 | #endif |