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Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +08001/*
2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9263 family SoC";
13 compatible = "atmel,at91sam9263";
14 interrupt-parent = <&aic>;
15
16 aliases {
17 serial0 = &dbgu;
18 serial1 = &usart0;
19 serial2 = &usart1;
20 serial3 = &usart2;
21 gpio0 = &pioA;
22 gpio1 = &pioB;
23 gpio2 = &pioC;
24 gpio3 = &pioD;
25 gpio4 = &pioE;
26 tcb0 = &tcb0;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020027 i2c0 = &i2c0;
Bo Shen099343c2012-11-07 11:41:41 +080028 ssc0 = &ssc0;
29 ssc1 = &ssc1;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080030 };
31 cpus {
32 cpu@0 {
33 compatible = "arm,arm926ejs";
34 };
35 };
36
37 memory {
38 reg = <0x20000000 0x08000000>;
39 };
40
41 ahb {
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges;
46
47 apb {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52
53 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020054 #interrupt-cells = <3>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080055 compatible = "atmel,at91rm9200-aic";
56 interrupt-controller;
57 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080058 atmel,external-irqs = <30 31>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080059 };
60
61 pmc: pmc@fffffc00 {
62 compatible = "atmel,at91rm9200-pmc";
63 reg = <0xfffffc00 0x100>;
64 };
65
66 ramc: ramc@ffffe200 {
67 compatible = "atmel,at91sam9260-sdramc";
68 reg = <0xffffe200 0x200
69 0xffffe800 0x200>;
70 };
71
72 pit: timer@fffffd30 {
73 compatible = "atmel,at91sam9260-pit";
74 reg = <0xfffffd30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020075 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080076 };
77
78 tcb0: timer@fff7c000 {
79 compatible = "atmel,at91rm9200-tcb";
80 reg = <0xfff7c000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020081 interrupts = <19 4 0>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080082 };
83
84 rstc@fffffd00 {
85 compatible = "atmel,at91sam9260-rstc";
86 reg = <0xfffffd00 0x10>;
87 };
88
89 shdwc@fffffd10 {
90 compatible = "atmel,at91sam9260-shdwc";
91 reg = <0xfffffd10 0x10>;
92 };
93
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +080094 pinctrl@fffff200 {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
98 ranges = <0xfffff200 0xfffff200 0xa00>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080099
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800100 atmel,mux-mask = <
101 /* A B */
102 0xfffffffb 0xffffe07f /* pioA */
103 0x0007ffff 0x39072fff /* pioB */
104 0xffffffff 0x3ffffff8 /* pioC */
105 0xfffffbff 0xffffffff /* pioD */
106 0xffe00fff 0xfbfcff00 /* pioE */
107 >;
108
109 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800110 dbgu {
111 pinctrl_dbgu: dbgu-0 {
112 atmel,pins =
113 <2 30 0x1 0x0 /* PC30 periph A */
114 2 31 0x1 0x1>; /* PC31 periph with pullup */
115 };
116 };
117
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800118 usart0 {
119 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800120 atmel,pins =
121 <0 26 0x1 0x1 /* PA26 periph A with pullup */
122 0 27 0x1 0x0>; /* PA27 periph A */
123 };
124
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800125 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800126 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800127 <0 28 0x1 0x0>; /* PA28 periph A */
128 };
129
130 pinctrl_usart0_cts: usart0_cts-0 {
131 atmel,pins =
132 <0 29 0x1 0x0>; /* PA29 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800133 };
134 };
135
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800136 usart1 {
137 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800138 atmel,pins =
139 <3 0 0x1 0x1 /* PD0 periph A with pullup */
140 3 1 0x1 0x0>; /* PD1 periph A */
141 };
142
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800143 pinctrl_usart1_rts: usart1_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800144 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800145 <3 7 0x2 0x0>; /* PD7 periph B */
146 };
147
148 pinctrl_usart1_cts: usart1_cts-0 {
149 atmel,pins =
150 <3 8 0x2 0x0>; /* PD8 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800151 };
152 };
153
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800154 usart2 {
155 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800156 atmel,pins =
157 <3 2 0x1 0x1 /* PD2 periph A with pullup */
158 3 3 0x1 0x0>; /* PD3 periph A */
159 };
160
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800161 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800162 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800163 <3 5 0x2 0x0>; /* PD5 periph B */
164 };
165
166 pinctrl_usart2_cts: usart2_cts-0 {
167 atmel,pins =
168 <4 6 0x2 0x0>; /* PD6 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800169 };
170 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800171
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800172 nand {
173 pinctrl_nand: nand-0 {
174 atmel,pins =
175 <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
176 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
177 };
178 };
179
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800180 macb {
181 pinctrl_macb_rmii: macb_rmii-0 {
182 atmel,pins =
183 <2 25 0x2 0x0 /* PC25 periph B */
184 4 21 0x1 0x0 /* PE21 periph A */
185 4 23 0x1 0x0 /* PE23 periph A */
186 4 24 0x1 0x0 /* PE24 periph A */
187 4 25 0x1 0x0 /* PE25 periph A */
188 4 26 0x1 0x0 /* PE26 periph A */
189 4 27 0x1 0x0 /* PE27 periph A */
190 4 28 0x1 0x0 /* PE28 periph A */
191 4 29 0x1 0x0 /* PE29 periph A */
192 4 30 0x1 0x0>; /* PE30 periph A */
193 };
194
195 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
196 atmel,pins =
197 <2 20 0x2 0x0 /* PC20 periph B */
198 2 21 0x2 0x0 /* PC21 periph B */
199 2 22 0x2 0x0 /* PC22 periph B */
200 2 23 0x2 0x0 /* PC23 periph B */
201 2 24 0x2 0x0 /* PC24 periph B */
202 2 25 0x2 0x0 /* PC25 periph B */
203 2 27 0x2 0x0 /* PC27 periph B */
204 4 22 0x2 0x0>; /* PE22 periph B */
205 };
206 };
207
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800208 mmc0 {
209 pinctrl_mmc0_clk: mmc0_clk-0 {
210 atmel,pins =
211 <0 12 0x1 0x0>; /* PA12 periph A */
212 };
213
214 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
215 atmel,pins =
216 <0 1 0x1 0x1 /* PA1 periph A with pullup */
217 0 0 0x1 0x1>; /* PA0 periph A with pullup */
218 };
219
220 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
221 atmel,pins =
222 <0 3 0x1 0x1 /* PA3 periph A with pullup */
223 0 4 0x1 0x1 /* PA4 periph A with pullup */
224 0 5 0x1 0x1>; /* PA5 periph A with pullup */
225 };
226
227 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
228 atmel,pins =
229 <0 16 0x1 0x1 /* PA16 periph A with pullup */
230 0 17 0x1 0x1>; /* PA17 periph A with pullup */
231 };
232
233 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
234 atmel,pins =
235 <0 18 0x1 0x1 /* PA18 periph A with pullup */
236 0 19 0x1 0x1 /* PA19 periph A with pullup */
237 0 20 0x1 0x1>; /* PA20 periph A with pullup */
238 };
239 };
240
241 mmc1 {
242 pinctrl_mmc1_clk: mmc1_clk-0 {
243 atmel,pins =
244 <0 6 0x1 0x0>; /* PA6 periph A */
245 };
246
247 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
248 atmel,pins =
249 <0 7 0x1 0x1 /* PA7 periph A with pullup */
250 0 8 0x1 0x1>; /* PA8 periph A with pullup */
251 };
252
253 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
254 atmel,pins =
255 <0 9 0x1 0x1 /* PA9 periph A with pullup */
256 0 10 0x1 0x1 /* PA10 periph A with pullup */
257 0 11 0x1 0x1>; /* PA11 periph A with pullup */
258 };
259
260 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
261 atmel,pins =
262 <0 21 0x1 0x1 /* PA21 periph A with pullup */
263 0 22 0x1 0x1>; /* PA22 periph A with pullup */
264 };
265
266 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
267 atmel,pins =
268 <0 23 0x1 0x1 /* PA23 periph A with pullup */
269 0 24 0x1 0x1 /* PA24 periph A with pullup */
270 0 25 0x1 0x1>; /* PA25 periph A with pullup */
271 };
272 };
273
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800274 pioA: gpio@fffff200 {
275 compatible = "atmel,at91rm9200-gpio";
276 reg = <0xfffff200 0x200>;
277 interrupts = <2 4 1>;
278 #gpio-cells = <2>;
279 gpio-controller;
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800283
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800284 pioB: gpio@fffff400 {
285 compatible = "atmel,at91rm9200-gpio";
286 reg = <0xfffff400 0x200>;
287 interrupts = <3 4 1>;
288 #gpio-cells = <2>;
289 gpio-controller;
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800293
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800294 pioC: gpio@fffff600 {
295 compatible = "atmel,at91rm9200-gpio";
296 reg = <0xfffff600 0x200>;
297 interrupts = <4 4 1>;
298 #gpio-cells = <2>;
299 gpio-controller;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800303
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800304 pioD: gpio@fffff800 {
305 compatible = "atmel,at91rm9200-gpio";
306 reg = <0xfffff800 0x200>;
307 interrupts = <4 4 1>;
308 #gpio-cells = <2>;
309 gpio-controller;
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 };
313
314 pioE: gpio@fffffa00 {
315 compatible = "atmel,at91rm9200-gpio";
316 reg = <0xfffffa00 0x200>;
317 interrupts = <4 4 1>;
318 #gpio-cells = <2>;
319 gpio-controller;
320 interrupt-controller;
321 #interrupt-cells = <2>;
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800322 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800323 };
324
325 dbgu: serial@ffffee00 {
326 compatible = "atmel,at91sam9260-usart";
327 reg = <0xffffee00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200328 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_dbgu>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800331 status = "disabled";
332 };
333
334 usart0: serial@fff8c000 {
335 compatible = "atmel,at91sam9260-usart";
336 reg = <0xfff8c000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200337 interrupts = <7 4 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800338 atmel,use-dma-rx;
339 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800340 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800341 pinctrl-0 = <&pinctrl_usart0>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800342 status = "disabled";
343 };
344
345 usart1: serial@fff90000 {
346 compatible = "atmel,at91sam9260-usart";
347 reg = <0xfff90000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200348 interrupts = <8 4 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800349 atmel,use-dma-rx;
350 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800351 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800352 pinctrl-0 = <&pinctrl_usart1>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800353 status = "disabled";
354 };
355
356 usart2: serial@fff94000 {
357 compatible = "atmel,at91sam9260-usart";
358 reg = <0xfff94000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200359 interrupts = <9 4 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800360 atmel,use-dma-rx;
361 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800362 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800363 pinctrl-0 = <&pinctrl_usart2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800364 status = "disabled";
365 };
366
Bo Shen099343c2012-11-07 11:41:41 +0800367 ssc0: ssc@fff98000 {
368 compatible = "atmel,at91rm9200-ssc";
369 reg = <0xfff98000 0x4000>;
370 interrupts = <16 4 5>;
Bo Shen315656b2012-12-13 10:05:07 +0800371 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800372 };
373
374 ssc1: ssc@fff9c000 {
375 compatible = "atmel,at91rm9200-ssc";
376 reg = <0xfff9c000 0x4000>;
377 interrupts = <17 4 5>;
Bo Shen315656b2012-12-13 10:05:07 +0800378 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800379 };
380
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800381 macb0: ethernet@fffbc000 {
382 compatible = "cdns,at32ap7000-macb", "cdns,macb";
383 reg = <0xfffbc000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200384 interrupts = <21 4 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_macb_rmii>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800387 status = "disabled";
388 };
389
390 usb1: gadget@fff78000 {
391 compatible = "atmel,at91rm9200-udc";
392 reg = <0xfff78000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200393 interrupts = <24 4 2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800394 status = "disabled";
395 };
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200396
397 i2c0: i2c@fff88000 {
398 compatible = "atmel,at91sam9263-i2c";
399 reg = <0xfff88000 0x100>;
400 interrupts = <13 4 6>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403 status = "disabled";
404 };
Ludovic Desroches98731372012-11-19 12:23:36 +0100405
406 mmc0: mmc@fff80000 {
407 compatible = "atmel,hsmci";
408 reg = <0xfff80000 0x600>;
409 interrupts = <10 4 0>;
410 #address-cells = <1>;
411 #size-cells = <0>;
412 status = "disabled";
413 };
414
415 mmc1: mmc@fff84000 {
416 compatible = "atmel,hsmci";
417 reg = <0xfff84000 0x600>;
418 interrupts = <11 4 0>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 status = "disabled";
422 };
Linus Torvaldsdb5b0ae2012-12-13 10:39:26 -0800423
Fabio Porcedda7492e7c2012-11-12 09:37:26 +0100424 watchdog@fffffd40 {
425 compatible = "atmel,at91sam9260-wdt";
426 reg = <0xfffffd40 0x10>;
427 status = "disabled";
428 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800429 };
430
431 nand0: nand@40000000 {
432 compatible = "atmel,at91rm9200-nand";
433 #address-cells = <1>;
434 #size-cells = <1>;
435 reg = <0x40000000 0x10000000
436 0xffffe000 0x200
437 >;
438 atmel,nand-addr-offset = <21>;
439 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800442 gpios = <&pioA 22 0
443 &pioD 15 0
444 0
445 >;
446 status = "disabled";
447 };
448
449 usb0: ohci@00a00000 {
450 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
451 reg = <0x00a00000 0x100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200452 interrupts = <29 4 2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800453 status = "disabled";
454 };
455 };
456
457 i2c@0 {
458 compatible = "i2c-gpio";
459 gpios = <&pioB 4 0 /* sda */
460 &pioB 5 0 /* scl */
461 >;
462 i2c-gpio,sda-open-drain;
463 i2c-gpio,scl-open-drain;
464 i2c-gpio,delay-us = <2>; /* ~100 kHz */
465 #address-cells = <1>;
466 #size-cells = <0>;
467 status = "disabled";
468 };
469};