Andy Gospodarek | 1a348cc | 2007-09-17 18:50:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Tehuti Networks(R) Network Driver |
| 3 | * ethtool interface implementation |
| 4 | * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * RX HW/SW interaction overview |
| 14 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 15 | * There are 2 types of RX communication channels betwean driver and NIC. |
| 16 | * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming |
| 17 | * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds |
| 18 | * info about buffer's location, size and ID. An ID field is used to identify a |
| 19 | * buffer when it's returned with data via RXD Fifo (see below) |
| 20 | * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is |
| 21 | * filled by HW and is readen by SW. Each descriptor holds status and ID. |
| 22 | * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data, |
| 23 | * via dma moves it into host memory, builds new RXD descriptor with same ID, |
| 24 | * pushes it into RXD Fifo and raises interrupt to indicate new RX data. |
| 25 | * |
| 26 | * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos. |
| 27 | * One holds 1.5K packets and another - 26K packets. Depending on incoming |
| 28 | * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is |
| 29 | * filled with data, HW builds new RXD descriptor for it and push it into single |
| 30 | * RXD Fifo. |
| 31 | * |
| 32 | * RX SW Data Structures |
| 33 | * ~~~~~~~~~~~~~~~~~~~~~ |
| 34 | * skb db - used to keep track of all skbs owned by SW and their dma addresses. |
| 35 | * For RX case, ownership lasts from allocating new empty skb for RXF until |
| 36 | * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own |
| 37 | * skb db. Implemented as array with bitmask. |
| 38 | * fifo - keeps info about fifo's size and location, relevant HW registers, |
| 39 | * usage and skb db. Each RXD and RXF Fifo has its own fifo structure. |
| 40 | * Implemented as simple struct. |
| 41 | * |
| 42 | * RX SW Execution Flow |
| 43 | * ~~~~~~~~~~~~~~~~~~~~ |
| 44 | * Upon initialization (ifconfig up) driver creates RX fifos and initializes |
| 45 | * relevant registers. At the end of init phase, driver enables interrupts. |
| 46 | * NIC sees that there is no RXF buffers and raises |
| 47 | * RD_INTR interrupt, isr fills skbs and Rx begins. |
| 48 | * Driver has two receive operation modes: |
| 49 | * NAPI - interrupt-driven mixed with polling |
| 50 | * interrupt-driven only |
| 51 | * |
| 52 | * Interrupt-driven only flow is following. When buffer is ready, HW raises |
| 53 | * interrupt and isr is called. isr collects all available packets |
| 54 | * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit. |
| 55 | |
| 56 | * Rx buffer allocation note |
| 57 | * ~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 58 | * Driver cares to feed such amount of RxF descriptors that respective amount of |
| 59 | * RxD descriptors can not fill entire RxD fifo. The main reason is lack of |
| 60 | * overflow check in Bordeaux for RxD fifo free/used size. |
| 61 | * FIXME: this is NOT fully implemented, more work should be done |
| 62 | * |
| 63 | */ |
| 64 | |
| 65 | #include "tehuti.h" |
| 66 | #include "tehuti_fw.h" |
| 67 | |
| 68 | static struct pci_device_id __devinitdata bdx_pci_tbl[] = { |
| 69 | {0x1FC9, 0x3009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
| 70 | {0x1FC9, 0x3010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
| 71 | {0x1FC9, 0x3014, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
| 72 | {0} |
| 73 | }; |
| 74 | |
| 75 | MODULE_DEVICE_TABLE(pci, bdx_pci_tbl); |
| 76 | |
| 77 | /* Definitions needed by ISR or NAPI functions */ |
| 78 | static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f); |
| 79 | static void bdx_tx_cleanup(struct bdx_priv *priv); |
| 80 | static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget); |
| 81 | |
| 82 | /* Definitions needed by FW loading */ |
| 83 | static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size); |
| 84 | |
| 85 | /* Definitions needed by hw_start */ |
| 86 | static int bdx_tx_init(struct bdx_priv *priv); |
| 87 | static int bdx_rx_init(struct bdx_priv *priv); |
| 88 | |
| 89 | /* Definitions needed by bdx_close */ |
| 90 | static void bdx_rx_free(struct bdx_priv *priv); |
| 91 | static void bdx_tx_free(struct bdx_priv *priv); |
| 92 | |
| 93 | /* Definitions needed by bdx_probe */ |
| 94 | static void bdx_ethtool_ops(struct net_device *netdev); |
| 95 | |
| 96 | /************************************************************************* |
| 97 | * Print Info * |
| 98 | *************************************************************************/ |
| 99 | |
| 100 | static void print_hw_id(struct pci_dev *pdev) |
| 101 | { |
| 102 | struct pci_nic *nic = pci_get_drvdata(pdev); |
| 103 | u16 pci_link_status = 0; |
| 104 | u16 pci_ctrl = 0; |
| 105 | |
| 106 | pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status); |
| 107 | pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl); |
| 108 | |
| 109 | printk(KERN_INFO "tehuti: %s%s\n", BDX_NIC_NAME, |
| 110 | nic->port_num == 1 ? "" : ", 2-Port"); |
| 111 | printk(KERN_INFO |
| 112 | "tehuti: srom 0x%x fpga %d build %u lane# %d" |
| 113 | " max_pl 0x%x mrrs 0x%x\n", |
| 114 | readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF, |
| 115 | readl(nic->regs + FPGA_SEED), |
| 116 | GET_LINK_STATUS_LANES(pci_link_status), |
| 117 | GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl)); |
| 118 | } |
| 119 | |
| 120 | static void print_fw_id(struct pci_nic *nic) |
| 121 | { |
| 122 | printk(KERN_INFO "tehuti: fw 0x%x\n", readl(nic->regs + FW_VER)); |
| 123 | } |
| 124 | |
| 125 | static void print_eth_id(struct net_device *ndev) |
| 126 | { |
| 127 | printk(KERN_INFO "%s: %s, Port %c\n", ndev->name, BDX_NIC_NAME, |
| 128 | (ndev->if_port == 0) ? 'A' : 'B'); |
| 129 | |
| 130 | } |
| 131 | |
| 132 | /************************************************************************* |
| 133 | * Code * |
| 134 | *************************************************************************/ |
| 135 | |
| 136 | #define bdx_enable_interrupts(priv) \ |
| 137 | do { WRITE_REG(priv, regIMR, IR_RUN); } while (0) |
| 138 | #define bdx_disable_interrupts(priv) \ |
| 139 | do { WRITE_REG(priv, regIMR, 0); } while (0) |
| 140 | |
| 141 | /* bdx_fifo_init |
| 142 | * create TX/RX descriptor fifo for host-NIC communication. |
| 143 | * 1K extra space is allocated at the end of the fifo to simplify |
| 144 | * processing of descriptors that wraps around fifo's end |
| 145 | * @priv - NIC private structure |
| 146 | * @f - fifo to initialize |
| 147 | * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB |
| 148 | * @reg_XXX - offsets of registers relative to base address |
| 149 | * |
| 150 | * Returns 0 on success, negative value on failure |
| 151 | * |
| 152 | */ |
| 153 | static int |
| 154 | bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type, |
| 155 | u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR) |
| 156 | { |
| 157 | u16 memsz = FIFO_SIZE * (1 << fsz_type); |
| 158 | |
| 159 | memset(f, 0, sizeof(struct fifo)); |
| 160 | /* pci_alloc_consistent gives us 4k-aligned memory */ |
| 161 | f->va = pci_alloc_consistent(priv->pdev, |
| 162 | memsz + FIFO_EXTRA_SPACE, &f->da); |
| 163 | if (!f->va) { |
| 164 | ERR("pci_alloc_consistent failed\n"); |
| 165 | RET(-ENOMEM); |
| 166 | } |
| 167 | f->reg_CFG0 = reg_CFG0; |
| 168 | f->reg_CFG1 = reg_CFG1; |
| 169 | f->reg_RPTR = reg_RPTR; |
| 170 | f->reg_WPTR = reg_WPTR; |
| 171 | f->rptr = 0; |
| 172 | f->wptr = 0; |
| 173 | f->memsz = memsz; |
| 174 | f->size_mask = memsz - 1; |
| 175 | WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type)); |
| 176 | WRITE_REG(priv, reg_CFG1, H32_64(f->da)); |
| 177 | |
| 178 | RET(0); |
| 179 | } |
| 180 | |
| 181 | /* bdx_fifo_free - free all resources used by fifo |
| 182 | * @priv - NIC private structure |
| 183 | * @f - fifo to release |
| 184 | */ |
| 185 | static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f) |
| 186 | { |
| 187 | ENTER; |
| 188 | if (f->va) { |
| 189 | pci_free_consistent(priv->pdev, |
| 190 | f->memsz + FIFO_EXTRA_SPACE, f->va, f->da); |
| 191 | f->va = NULL; |
| 192 | } |
| 193 | RET(); |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * bdx_link_changed - notifies OS about hw link state. |
| 198 | * @bdx_priv - hw adapter structure |
| 199 | */ |
| 200 | static void bdx_link_changed(struct bdx_priv *priv) |
| 201 | { |
| 202 | u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT; |
| 203 | |
| 204 | if (!link) { |
| 205 | if (netif_carrier_ok(priv->ndev)) { |
| 206 | netif_stop_queue(priv->ndev); |
| 207 | netif_carrier_off(priv->ndev); |
| 208 | ERR("%s: Link Down\n", priv->ndev->name); |
| 209 | } |
| 210 | } else { |
| 211 | if (!netif_carrier_ok(priv->ndev)) { |
| 212 | netif_wake_queue(priv->ndev); |
| 213 | netif_carrier_on(priv->ndev); |
| 214 | ERR("%s: Link Up\n", priv->ndev->name); |
| 215 | } |
| 216 | } |
| 217 | } |
| 218 | |
| 219 | static void bdx_isr_extra(struct bdx_priv *priv, u32 isr) |
| 220 | { |
| 221 | if (isr & IR_RX_FREE_0) { |
| 222 | bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); |
| 223 | DBG("RX_FREE_0\n"); |
| 224 | } |
| 225 | |
| 226 | if (isr & IR_LNKCHG0) |
| 227 | bdx_link_changed(priv); |
| 228 | |
| 229 | if (isr & IR_PCIE_LINK) |
| 230 | ERR("%s: PCI-E Link Fault\n", priv->ndev->name); |
| 231 | |
| 232 | if (isr & IR_PCIE_TOUT) |
| 233 | ERR("%s: PCI-E Time Out\n", priv->ndev->name); |
| 234 | |
| 235 | } |
| 236 | |
| 237 | /* bdx_isr - Interrupt Service Routine for Bordeaux NIC |
| 238 | * @irq - interrupt number |
| 239 | * @ndev - network device |
| 240 | * @regs - CPU registers |
| 241 | * |
| 242 | * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise |
| 243 | * |
| 244 | * It reads ISR register to know interrupt reasons, and proceed them one by one. |
| 245 | * Reasons of interest are: |
| 246 | * RX_DESC - new packet has arrived and RXD fifo holds its descriptor |
| 247 | * RX_FREE - number of free Rx buffers in RXF fifo gets low |
| 248 | * TX_FREE - packet was transmited and RXF fifo holds its descriptor |
| 249 | */ |
| 250 | |
| 251 | static irqreturn_t bdx_isr_napi(int irq, void *dev) |
| 252 | { |
| 253 | struct net_device *ndev = dev; |
| 254 | struct bdx_priv *priv = ndev->priv; |
| 255 | u32 isr; |
| 256 | |
| 257 | ENTER; |
| 258 | isr = (READ_REG(priv, regISR) & IR_RUN); |
| 259 | if (unlikely(!isr)) { |
| 260 | bdx_enable_interrupts(priv); |
| 261 | return IRQ_NONE; /* Not our interrupt */ |
| 262 | } |
| 263 | |
| 264 | if (isr & IR_EXTRA) |
| 265 | bdx_isr_extra(priv, isr); |
| 266 | |
| 267 | if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) { |
| 268 | if (likely(netif_rx_schedule_prep(ndev, &priv->napi))) { |
| 269 | __netif_rx_schedule(ndev, &priv->napi); |
| 270 | RET(IRQ_HANDLED); |
| 271 | } else { |
| 272 | /* NOTE: we get here if intr has slipped into window |
| 273 | * between these lines in bdx_poll: |
| 274 | * bdx_enable_interrupts(priv); |
| 275 | * return 0; |
| 276 | * currently intrs are disabled (since we read ISR), |
| 277 | * and we have failed to register next poll. |
| 278 | * so we read the regs to trigger chip |
| 279 | * and allow further interupts. */ |
| 280 | READ_REG(priv, regTXF_WPTR_0); |
| 281 | READ_REG(priv, regRXD_WPTR_0); |
| 282 | } |
| 283 | } |
| 284 | |
| 285 | bdx_enable_interrupts(priv); |
| 286 | RET(IRQ_HANDLED); |
| 287 | } |
| 288 | |
| 289 | static int bdx_poll(struct napi_struct *napi, int budget) |
| 290 | { |
| 291 | struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi); |
| 292 | struct net_device *dev = priv->ndev; |
| 293 | int work_done; |
| 294 | |
| 295 | ENTER; |
| 296 | bdx_tx_cleanup(priv); |
| 297 | work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget); |
| 298 | if ((work_done < budget) || |
| 299 | (priv->napi_stop++ >= 30)) { |
| 300 | DBG("rx poll is done. backing to isr-driven\n"); |
| 301 | |
| 302 | /* from time to time we exit to let NAPI layer release |
| 303 | * device lock and allow waiting tasks (eg rmmod) to advance) */ |
| 304 | priv->napi_stop = 0; |
| 305 | |
| 306 | netif_rx_complete(dev, napi); |
| 307 | bdx_enable_interrupts(priv); |
| 308 | } |
| 309 | return work_done; |
| 310 | } |
| 311 | |
| 312 | /* bdx_fw_load - loads firmware to NIC |
| 313 | * @priv - NIC private structure |
| 314 | * Firmware is loaded via TXD fifo, so it must be initialized first. |
| 315 | * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC |
| 316 | * can have few of them). So all drivers use semaphore register to choose one |
| 317 | * that will actually load FW to NIC. |
| 318 | */ |
| 319 | |
| 320 | static int bdx_fw_load(struct bdx_priv *priv) |
| 321 | { |
| 322 | int master, i; |
| 323 | |
| 324 | ENTER; |
| 325 | master = READ_REG(priv, regINIT_SEMAPHORE); |
| 326 | if (!READ_REG(priv, regINIT_STATUS) && master) { |
| 327 | bdx_tx_push_desc_safe(priv, s_firmLoad, sizeof(s_firmLoad)); |
| 328 | mdelay(100); |
| 329 | } |
| 330 | for (i = 0; i < 200; i++) { |
| 331 | if (READ_REG(priv, regINIT_STATUS)) |
| 332 | break; |
| 333 | mdelay(2); |
| 334 | } |
| 335 | if (master) |
| 336 | WRITE_REG(priv, regINIT_SEMAPHORE, 1); |
| 337 | |
| 338 | if (i == 200) { |
| 339 | ERR("%s: firmware loading failed\n", priv->ndev->name); |
| 340 | DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n", |
| 341 | READ_REG(priv, regVPC), |
| 342 | READ_REG(priv, regVIC), READ_REG(priv, regINIT_STATUS), i); |
| 343 | RET(-EIO); |
| 344 | } else { |
| 345 | DBG("%s: firmware loading success\n", priv->ndev->name); |
| 346 | RET(0); |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv) |
| 351 | { |
| 352 | u32 val; |
| 353 | |
| 354 | ENTER; |
| 355 | DBG("mac0=%x mac1=%x mac2=%x\n", |
| 356 | READ_REG(priv, regUNC_MAC0_A), |
| 357 | READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A)); |
| 358 | |
| 359 | val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]); |
| 360 | WRITE_REG(priv, regUNC_MAC2_A, val); |
| 361 | val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]); |
| 362 | WRITE_REG(priv, regUNC_MAC1_A, val); |
| 363 | val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]); |
| 364 | WRITE_REG(priv, regUNC_MAC0_A, val); |
| 365 | |
| 366 | DBG("mac0=%x mac1=%x mac2=%x\n", |
| 367 | READ_REG(priv, regUNC_MAC0_A), |
| 368 | READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A)); |
| 369 | RET(); |
| 370 | } |
| 371 | |
| 372 | /* bdx_hw_start - inits registers and starts HW's Rx and Tx engines |
| 373 | * @priv - NIC private structure |
| 374 | */ |
| 375 | static int bdx_hw_start(struct bdx_priv *priv) |
| 376 | { |
| 377 | int rc = -EIO; |
| 378 | struct net_device *ndev = priv->ndev; |
| 379 | |
| 380 | ENTER; |
| 381 | bdx_link_changed(priv); |
| 382 | |
| 383 | /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */ |
| 384 | WRITE_REG(priv, regFRM_LENGTH, 0X3FE0); |
| 385 | WRITE_REG(priv, regPAUSE_QUANT, 0x96); |
| 386 | WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010); |
| 387 | WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010); |
| 388 | WRITE_REG(priv, regRX_FULLNESS, 0); |
| 389 | WRITE_REG(priv, regTX_FULLNESS, 0); |
| 390 | WRITE_REG(priv, regCTRLST, |
| 391 | regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA); |
| 392 | |
| 393 | WRITE_REG(priv, regVGLB, 0); |
| 394 | WRITE_REG(priv, regMAX_FRAME_A, |
| 395 | priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL); |
| 396 | |
| 397 | DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */ |
| 398 | WRITE_REG(priv, regRDINTCM0, priv->rdintcm); |
| 399 | WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */ |
| 400 | |
| 401 | DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */ |
| 402 | WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */ |
| 403 | |
| 404 | /* Enable timer interrupt once in 2 secs. */ |
| 405 | /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */ |
| 406 | bdx_restore_mac(priv->ndev, priv); |
| 407 | |
| 408 | WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN | |
| 409 | GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB); |
| 410 | |
| 411 | #define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI)?0:IRQF_SHARED) |
| 412 | if ((rc = request_irq(priv->pdev->irq, &bdx_isr_napi, BDX_IRQ_TYPE, |
| 413 | ndev->name, ndev))) |
| 414 | goto err_irq; |
| 415 | bdx_enable_interrupts(priv); |
| 416 | |
| 417 | RET(0); |
| 418 | |
| 419 | err_irq: |
| 420 | RET(rc); |
| 421 | } |
| 422 | |
| 423 | static void bdx_hw_stop(struct bdx_priv *priv) |
| 424 | { |
| 425 | ENTER; |
| 426 | bdx_disable_interrupts(priv); |
| 427 | free_irq(priv->pdev->irq, priv->ndev); |
| 428 | |
| 429 | netif_carrier_off(priv->ndev); |
| 430 | netif_stop_queue(priv->ndev); |
| 431 | |
| 432 | RET(); |
| 433 | } |
| 434 | |
| 435 | static int bdx_hw_reset_direct(void __iomem *regs) |
| 436 | { |
| 437 | u32 val, i; |
| 438 | ENTER; |
| 439 | |
| 440 | /* reset sequences: read, write 1, read, write 0 */ |
| 441 | val = readl(regs + regCLKPLL); |
| 442 | writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL); |
| 443 | udelay(50); |
| 444 | val = readl(regs + regCLKPLL); |
| 445 | writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL); |
| 446 | |
| 447 | /* check that the PLLs are locked and reset ended */ |
| 448 | for (i = 0; i < 70; i++, mdelay(10)) |
| 449 | if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) { |
| 450 | /* do any PCI-E read transaction */ |
| 451 | readl(regs + regRXD_CFG0_0); |
| 452 | return 0; |
| 453 | } |
| 454 | ERR("tehuti: HW reset failed\n"); |
| 455 | return 1; /* failure */ |
| 456 | } |
| 457 | |
| 458 | static int bdx_hw_reset(struct bdx_priv *priv) |
| 459 | { |
| 460 | u32 val, i; |
| 461 | ENTER; |
| 462 | |
| 463 | if (priv->port == 0) { |
| 464 | /* reset sequences: read, write 1, read, write 0 */ |
| 465 | val = READ_REG(priv, regCLKPLL); |
| 466 | WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8); |
| 467 | udelay(50); |
| 468 | val = READ_REG(priv, regCLKPLL); |
| 469 | WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST); |
| 470 | } |
| 471 | /* check that the PLLs are locked and reset ended */ |
| 472 | for (i = 0; i < 70; i++, mdelay(10)) |
| 473 | if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) { |
| 474 | /* do any PCI-E read transaction */ |
| 475 | READ_REG(priv, regRXD_CFG0_0); |
| 476 | return 0; |
| 477 | } |
| 478 | ERR("tehuti: HW reset failed\n"); |
| 479 | return 1; /* failure */ |
| 480 | } |
| 481 | |
| 482 | static int bdx_sw_reset(struct bdx_priv *priv) |
| 483 | { |
| 484 | int i; |
| 485 | |
| 486 | ENTER; |
| 487 | /* 1. load MAC (obsolete) */ |
| 488 | /* 2. disable Rx (and Tx) */ |
| 489 | WRITE_REG(priv, regGMAC_RXF_A, 0); |
| 490 | mdelay(100); |
| 491 | /* 3. disable port */ |
| 492 | WRITE_REG(priv, regDIS_PORT, 1); |
| 493 | /* 4. disable queue */ |
| 494 | WRITE_REG(priv, regDIS_QU, 1); |
| 495 | /* 5. wait until hw is disabled */ |
| 496 | for (i = 0; i < 50; i++) { |
| 497 | if (READ_REG(priv, regRST_PORT) & 1) |
| 498 | break; |
| 499 | mdelay(10); |
| 500 | } |
| 501 | if (i == 50) |
| 502 | ERR("%s: SW reset timeout. continuing anyway\n", |
| 503 | priv->ndev->name); |
| 504 | |
| 505 | /* 6. disable intrs */ |
| 506 | WRITE_REG(priv, regRDINTCM0, 0); |
| 507 | WRITE_REG(priv, regTDINTCM0, 0); |
| 508 | WRITE_REG(priv, regIMR, 0); |
| 509 | READ_REG(priv, regISR); |
| 510 | |
| 511 | /* 7. reset queue */ |
| 512 | WRITE_REG(priv, regRST_QU, 1); |
| 513 | /* 8. reset port */ |
| 514 | WRITE_REG(priv, regRST_PORT, 1); |
| 515 | /* 9. zero all read and write pointers */ |
| 516 | for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) |
| 517 | DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR); |
| 518 | for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) |
| 519 | WRITE_REG(priv, i, 0); |
| 520 | /* 10. unseet port disable */ |
| 521 | WRITE_REG(priv, regDIS_PORT, 0); |
| 522 | /* 11. unset queue disable */ |
| 523 | WRITE_REG(priv, regDIS_QU, 0); |
| 524 | /* 12. unset queue reset */ |
| 525 | WRITE_REG(priv, regRST_QU, 0); |
| 526 | /* 13. unset port reset */ |
| 527 | WRITE_REG(priv, regRST_PORT, 0); |
| 528 | /* 14. enable Rx */ |
| 529 | /* skiped. will be done later */ |
| 530 | /* 15. save MAC (obsolete) */ |
| 531 | for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) |
| 532 | DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR); |
| 533 | |
| 534 | RET(0); |
| 535 | } |
| 536 | |
| 537 | /* bdx_reset - performs right type of reset depending on hw type */ |
| 538 | static int bdx_reset(struct bdx_priv *priv) |
| 539 | { |
| 540 | ENTER; |
| 541 | RET((priv->pdev->device == 0x3009) |
| 542 | ? bdx_hw_reset(priv) |
| 543 | : bdx_sw_reset(priv)); |
| 544 | } |
| 545 | |
| 546 | /** |
| 547 | * bdx_close - Disables a network interface |
| 548 | * @netdev: network interface device structure |
| 549 | * |
| 550 | * Returns 0, this is not allowed to fail |
| 551 | * |
| 552 | * The close entry point is called when an interface is de-activated |
| 553 | * by the OS. The hardware is still under the drivers control, but |
| 554 | * needs to be disabled. A global MAC reset is issued to stop the |
| 555 | * hardware, and all transmit and receive resources are freed. |
| 556 | **/ |
| 557 | static int bdx_close(struct net_device *ndev) |
| 558 | { |
| 559 | struct bdx_priv *priv = NULL; |
| 560 | |
| 561 | ENTER; |
| 562 | priv = ndev->priv; |
| 563 | |
| 564 | napi_disable(&priv->napi); |
| 565 | |
| 566 | bdx_reset(priv); |
| 567 | bdx_hw_stop(priv); |
| 568 | bdx_rx_free(priv); |
| 569 | bdx_tx_free(priv); |
| 570 | RET(0); |
| 571 | } |
| 572 | |
| 573 | /** |
| 574 | * bdx_open - Called when a network interface is made active |
| 575 | * @netdev: network interface device structure |
| 576 | * |
| 577 | * Returns 0 on success, negative value on failure |
| 578 | * |
| 579 | * The open entry point is called when a network interface is made |
| 580 | * active by the system (IFF_UP). At this point all resources needed |
| 581 | * for transmit and receive operations are allocated, the interrupt |
| 582 | * handler is registered with the OS, the watchdog timer is started, |
| 583 | * and the stack is notified that the interface is ready. |
| 584 | **/ |
| 585 | static int bdx_open(struct net_device *ndev) |
| 586 | { |
| 587 | struct bdx_priv *priv; |
| 588 | int rc; |
| 589 | |
| 590 | ENTER; |
| 591 | priv = ndev->priv; |
| 592 | bdx_reset(priv); |
| 593 | if (netif_running(ndev)) |
| 594 | netif_stop_queue(priv->ndev); |
| 595 | |
| 596 | if ((rc = bdx_tx_init(priv))) |
| 597 | goto err; |
| 598 | |
| 599 | if ((rc = bdx_rx_init(priv))) |
| 600 | goto err; |
| 601 | |
| 602 | if ((rc = bdx_fw_load(priv))) |
| 603 | goto err; |
| 604 | |
| 605 | bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); |
| 606 | |
| 607 | if ((rc = bdx_hw_start(priv))) |
| 608 | goto err; |
| 609 | |
| 610 | napi_enable(&priv->napi); |
| 611 | |
| 612 | print_fw_id(priv->nic); |
| 613 | |
| 614 | RET(0); |
| 615 | |
| 616 | err: |
| 617 | bdx_close(ndev); |
| 618 | RET(rc); |
| 619 | } |
| 620 | |
| 621 | static void __init bdx_firmware_endianess(void) |
| 622 | { |
| 623 | int i; |
| 624 | for (i = 0; i < sizeof(s_firmLoad) / sizeof(u32); i++) |
| 625 | s_firmLoad[i] = CPU_CHIP_SWAP32(s_firmLoad[i]); |
| 626 | } |
| 627 | |
| 628 | static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd) |
| 629 | { |
| 630 | struct bdx_priv *priv = ndev->priv; |
| 631 | u32 data[3]; |
| 632 | int error; |
| 633 | |
| 634 | ENTER; |
| 635 | |
| 636 | DBG("jiffies=%ld cmd=%d\n", jiffies, cmd); |
| 637 | if (cmd != SIOCDEVPRIVATE) { |
| 638 | error = copy_from_user(data, ifr->ifr_data, sizeof(data)); |
| 639 | if (error) { |
| 640 | ERR("cant copy from user\n"); |
| 641 | RET(error); |
| 642 | } |
| 643 | DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]); |
| 644 | } |
| 645 | |
| 646 | switch (data[0]) { |
| 647 | |
| 648 | case BDX_OP_READ: |
| 649 | data[2] = READ_REG(priv, data[1]); |
| 650 | DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2], |
| 651 | data[2]); |
| 652 | error = copy_to_user(ifr->ifr_data, data, sizeof(data)); |
| 653 | if (error) |
| 654 | RET(error); |
| 655 | break; |
| 656 | |
| 657 | case BDX_OP_WRITE: |
| 658 | WRITE_REG(priv, data[1], data[2]); |
| 659 | DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]); |
| 660 | break; |
| 661 | |
| 662 | default: |
| 663 | RET(-EOPNOTSUPP); |
| 664 | } |
| 665 | return 0; |
| 666 | } |
| 667 | |
| 668 | static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) |
| 669 | { |
| 670 | ENTER; |
| 671 | if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15)) |
| 672 | RET(bdx_ioctl_priv(ndev, ifr, cmd)); |
| 673 | else |
| 674 | RET(-EOPNOTSUPP); |
| 675 | } |
| 676 | |
| 677 | /* |
| 678 | * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid |
| 679 | * by passing VLAN filter table to hardware |
| 680 | * @ndev network device |
| 681 | * @vid VLAN vid |
| 682 | * @op add or kill operation |
| 683 | */ |
| 684 | static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable) |
| 685 | { |
| 686 | struct bdx_priv *priv = ndev->priv; |
| 687 | u32 reg, bit, val; |
| 688 | |
| 689 | ENTER; |
| 690 | DBG2("vid=%d value=%d\n", (int)vid, enable); |
| 691 | if (unlikely(vid >= 4096)) { |
| 692 | ERR("tehuti: invalid VID: %u (> 4096)\n", vid); |
| 693 | RET(); |
| 694 | } |
| 695 | reg = regVLAN_0 + (vid / 32) * 4; |
| 696 | bit = 1 << vid % 32; |
| 697 | val = READ_REG(priv, reg); |
| 698 | DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit); |
| 699 | if (enable) |
| 700 | val |= bit; |
| 701 | else |
| 702 | val &= ~bit; |
| 703 | DBG2("new val %x\n", val); |
| 704 | WRITE_REG(priv, reg, val); |
| 705 | RET(); |
| 706 | } |
| 707 | |
| 708 | /* |
| 709 | * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table |
| 710 | * @ndev network device |
| 711 | * @vid VLAN vid to add |
| 712 | */ |
| 713 | static void bdx_vlan_rx_add_vid(struct net_device *ndev, uint16_t vid) |
| 714 | { |
| 715 | __bdx_vlan_rx_vid(ndev, vid, 1); |
| 716 | } |
| 717 | |
| 718 | /* |
| 719 | * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table |
| 720 | * @ndev network device |
| 721 | * @vid VLAN vid to kill |
| 722 | */ |
| 723 | static void bdx_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid) |
| 724 | { |
| 725 | __bdx_vlan_rx_vid(ndev, vid, 0); |
| 726 | } |
| 727 | |
| 728 | /* |
| 729 | * bdx_vlan_rx_register - kernel hook for adding VLAN group |
| 730 | * @ndev network device |
| 731 | * @grp VLAN group |
| 732 | */ |
| 733 | static void |
| 734 | bdx_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp) |
| 735 | { |
| 736 | struct bdx_priv *priv = ndev->priv; |
| 737 | |
| 738 | ENTER; |
| 739 | DBG("device='%s', group='%p'\n", ndev->name, grp); |
| 740 | priv->vlgrp = grp; |
| 741 | RET(); |
| 742 | } |
| 743 | |
| 744 | /** |
| 745 | * bdx_change_mtu - Change the Maximum Transfer Unit |
| 746 | * @netdev: network interface device structure |
| 747 | * @new_mtu: new value for maximum frame size |
| 748 | * |
| 749 | * Returns 0 on success, negative on failure |
| 750 | */ |
| 751 | static int bdx_change_mtu(struct net_device *ndev, int new_mtu) |
| 752 | { |
| 753 | BDX_ASSERT(ndev == 0); |
| 754 | ENTER; |
| 755 | |
| 756 | if (new_mtu == ndev->mtu) |
| 757 | RET(0); |
| 758 | |
| 759 | /* enforce minimum frame size */ |
| 760 | if (new_mtu < ETH_ZLEN) { |
| 761 | ERR("%s: %s mtu %d is less then minimal %d\n", |
| 762 | BDX_DRV_NAME, ndev->name, new_mtu, ETH_ZLEN); |
| 763 | RET(-EINVAL); |
| 764 | } |
| 765 | |
| 766 | ndev->mtu = new_mtu; |
| 767 | if (netif_running(ndev)) { |
| 768 | bdx_close(ndev); |
| 769 | bdx_open(ndev); |
| 770 | } |
| 771 | RET(0); |
| 772 | } |
| 773 | |
| 774 | static void bdx_setmulti(struct net_device *ndev) |
| 775 | { |
| 776 | struct bdx_priv *priv = ndev->priv; |
| 777 | |
| 778 | u32 rxf_val = |
| 779 | GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN; |
| 780 | int i; |
| 781 | |
| 782 | ENTER; |
| 783 | /* IMF - imperfect (hash) rx multicat filter */ |
| 784 | /* PMF - perfect rx multicat filter */ |
| 785 | |
| 786 | /* FIXME: RXE(OFF) */ |
| 787 | if (ndev->flags & IFF_PROMISC) { |
| 788 | rxf_val |= GMAC_RX_FILTER_PRM; |
| 789 | } else if (ndev->flags & IFF_ALLMULTI) { |
| 790 | /* set IMF to accept all multicast frmaes */ |
| 791 | for (i = 0; i < MAC_MCST_HASH_NUM; i++) |
| 792 | WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0); |
| 793 | } else if (ndev->mc_count) { |
| 794 | u8 hash; |
| 795 | struct dev_mc_list *mclist; |
| 796 | u32 reg, val; |
| 797 | |
| 798 | /* set IMF to deny all multicast frames */ |
| 799 | for (i = 0; i < MAC_MCST_HASH_NUM; i++) |
| 800 | WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0); |
| 801 | /* set PMF to deny all multicast frames */ |
| 802 | for (i = 0; i < MAC_MCST_NUM; i++) { |
| 803 | WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0); |
| 804 | WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0); |
| 805 | } |
| 806 | |
| 807 | /* use PMF to accept first MAC_MCST_NUM (15) addresses */ |
| 808 | /* TBD: sort addreses and write them in ascending order |
| 809 | * into RX_MAC_MCST regs. we skip this phase now and accept ALL |
| 810 | * multicast frames throu IMF */ |
| 811 | mclist = ndev->mc_list; |
| 812 | |
| 813 | /* accept the rest of addresses throu IMF */ |
| 814 | for (; mclist; mclist = mclist->next) { |
| 815 | hash = 0; |
| 816 | for (i = 0; i < ETH_ALEN; i++) |
| 817 | hash ^= mclist->dmi_addr[i]; |
| 818 | reg = regRX_MCST_HASH0 + ((hash >> 5) << 2); |
| 819 | val = READ_REG(priv, reg); |
| 820 | val |= (1 << (hash % 32)); |
| 821 | WRITE_REG(priv, reg, val); |
| 822 | } |
| 823 | |
| 824 | } else { |
| 825 | DBG("only own mac %d\n", ndev->mc_count); |
| 826 | rxf_val |= GMAC_RX_FILTER_AB; |
| 827 | } |
| 828 | WRITE_REG(priv, regGMAC_RXF_A, rxf_val); |
| 829 | /* enable RX */ |
| 830 | /* FIXME: RXE(ON) */ |
| 831 | RET(); |
| 832 | } |
| 833 | |
| 834 | static int bdx_set_mac(struct net_device *ndev, void *p) |
| 835 | { |
| 836 | struct bdx_priv *priv = ndev->priv; |
| 837 | struct sockaddr *addr = p; |
| 838 | |
| 839 | ENTER; |
| 840 | /* |
| 841 | if (netif_running(dev)) |
| 842 | return -EBUSY |
| 843 | */ |
| 844 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
| 845 | bdx_restore_mac(ndev, priv); |
| 846 | RET(0); |
| 847 | } |
| 848 | |
| 849 | static int bdx_read_mac(struct bdx_priv *priv) |
| 850 | { |
| 851 | u16 macAddress[3], i; |
| 852 | ENTER; |
| 853 | |
| 854 | macAddress[2] = READ_REG(priv, regUNC_MAC0_A); |
| 855 | macAddress[2] = READ_REG(priv, regUNC_MAC0_A); |
| 856 | macAddress[1] = READ_REG(priv, regUNC_MAC1_A); |
| 857 | macAddress[1] = READ_REG(priv, regUNC_MAC1_A); |
| 858 | macAddress[0] = READ_REG(priv, regUNC_MAC2_A); |
| 859 | macAddress[0] = READ_REG(priv, regUNC_MAC2_A); |
| 860 | for (i = 0; i < 3; i++) { |
| 861 | priv->ndev->dev_addr[i * 2 + 1] = macAddress[i]; |
| 862 | priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8; |
| 863 | } |
| 864 | RET(0); |
| 865 | } |
| 866 | |
| 867 | static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg) |
| 868 | { |
| 869 | u64 val; |
| 870 | |
| 871 | val = READ_REG(priv, reg); |
| 872 | val |= ((u64) READ_REG(priv, reg + 8)) << 32; |
| 873 | return val; |
| 874 | } |
| 875 | |
| 876 | /*Do the statistics-update work*/ |
| 877 | static void bdx_update_stats(struct bdx_priv *priv) |
| 878 | { |
| 879 | struct bdx_stats *stats = &priv->hw_stats; |
| 880 | u64 *stats_vector = (u64 *) stats; |
| 881 | int i; |
| 882 | int addr; |
| 883 | |
| 884 | /*Fill HW structure */ |
| 885 | addr = 0x7200; |
| 886 | /*First 12 statistics - 0x7200 - 0x72B0 */ |
| 887 | for (i = 0; i < 12; i++) { |
| 888 | stats_vector[i] = bdx_read_l2stat(priv, addr); |
| 889 | addr += 0x10; |
| 890 | } |
| 891 | BDX_ASSERT(addr != 0x72C0); |
| 892 | /* 0x72C0-0x72E0 RSRV */ |
| 893 | addr = 0x72F0; |
| 894 | for (; i < 16; i++) { |
| 895 | stats_vector[i] = bdx_read_l2stat(priv, addr); |
| 896 | addr += 0x10; |
| 897 | } |
| 898 | BDX_ASSERT(addr != 0x7330); |
| 899 | /* 0x7330-0x7360 RSRV */ |
| 900 | addr = 0x7370; |
| 901 | for (; i < 19; i++) { |
| 902 | stats_vector[i] = bdx_read_l2stat(priv, addr); |
| 903 | addr += 0x10; |
| 904 | } |
| 905 | BDX_ASSERT(addr != 0x73A0); |
| 906 | /* 0x73A0-0x73B0 RSRV */ |
| 907 | addr = 0x73C0; |
| 908 | for (; i < 23; i++) { |
| 909 | stats_vector[i] = bdx_read_l2stat(priv, addr); |
| 910 | addr += 0x10; |
| 911 | } |
| 912 | BDX_ASSERT(addr != 0x7400); |
| 913 | BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i); |
| 914 | } |
| 915 | |
| 916 | static struct net_device_stats *bdx_get_stats(struct net_device *ndev) |
| 917 | { |
| 918 | struct bdx_priv *priv = ndev->priv; |
| 919 | struct net_device_stats *net_stat = &priv->net_stats; |
| 920 | return net_stat; |
| 921 | } |
| 922 | |
| 923 | static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len, |
| 924 | u16 rxd_vlan); |
| 925 | static void print_rxfd(struct rxf_desc *rxfd); |
| 926 | |
| 927 | /************************************************************************* |
| 928 | * Rx DB * |
| 929 | *************************************************************************/ |
| 930 | |
| 931 | static void bdx_rxdb_destroy(struct rxdb *db) |
| 932 | { |
| 933 | if (db) |
| 934 | vfree(db); |
| 935 | } |
| 936 | |
| 937 | static struct rxdb *bdx_rxdb_create(int nelem) |
| 938 | { |
| 939 | struct rxdb *db; |
| 940 | int i; |
| 941 | |
| 942 | db = vmalloc(sizeof(struct rxdb) |
| 943 | + (nelem * sizeof(int)) |
| 944 | + (nelem * sizeof(struct rx_map))); |
| 945 | if (likely(db != NULL)) { |
| 946 | db->stack = (int *)(db + 1); |
| 947 | db->elems = (void *)(db->stack + nelem); |
| 948 | db->nelem = nelem; |
| 949 | db->top = nelem; |
| 950 | for (i = 0; i < nelem; i++) |
| 951 | db->stack[i] = nelem - i - 1; /* to make first allocs |
| 952 | close to db struct*/ |
| 953 | } |
| 954 | |
| 955 | return db; |
| 956 | } |
| 957 | |
| 958 | static inline int bdx_rxdb_alloc_elem(struct rxdb *db) |
| 959 | { |
| 960 | BDX_ASSERT(db->top <= 0); |
| 961 | return db->stack[--(db->top)]; |
| 962 | } |
| 963 | |
| 964 | static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n) |
| 965 | { |
| 966 | BDX_ASSERT((n < 0) || (n >= db->nelem)); |
| 967 | return db->elems + n; |
| 968 | } |
| 969 | |
| 970 | static inline int bdx_rxdb_available(struct rxdb *db) |
| 971 | { |
| 972 | return db->top; |
| 973 | } |
| 974 | |
| 975 | static inline void bdx_rxdb_free_elem(struct rxdb *db, int n) |
| 976 | { |
| 977 | BDX_ASSERT((n >= db->nelem) || (n < 0)); |
| 978 | db->stack[(db->top)++] = n; |
| 979 | } |
| 980 | |
| 981 | /************************************************************************* |
| 982 | * Rx Init * |
| 983 | *************************************************************************/ |
| 984 | |
| 985 | /* bdx_rx_init - initialize RX all related HW and SW resources |
| 986 | * @priv - NIC private structure |
| 987 | * |
| 988 | * Returns 0 on success, negative value on failure |
| 989 | * |
| 990 | * It creates rxf and rxd fifos, update relevant HW registers, preallocate |
| 991 | * skb for rx. It assumes that Rx is desabled in HW |
| 992 | * funcs are grouped for better cache usage |
| 993 | * |
| 994 | * RxD fifo is smaller then RxF fifo by design. Upon high load, RxD will be |
| 995 | * filled and packets will be dropped by nic without getting into host or |
| 996 | * cousing interrupt. Anyway, in that condition, host has no chance to proccess |
| 997 | * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles |
| 998 | */ |
| 999 | |
| 1000 | /* TBD: ensure proper packet size */ |
| 1001 | |
| 1002 | static int bdx_rx_init(struct bdx_priv *priv) |
| 1003 | { |
| 1004 | ENTER; |
| 1005 | BDX_ASSERT(priv == 0); |
| 1006 | if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size, |
| 1007 | regRXD_CFG0_0, regRXD_CFG1_0, |
| 1008 | regRXD_RPTR_0, regRXD_WPTR_0)) |
| 1009 | goto err_mem; |
| 1010 | if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size, |
| 1011 | regRXF_CFG0_0, regRXF_CFG1_0, |
| 1012 | regRXF_RPTR_0, regRXF_WPTR_0)) |
| 1013 | goto err_mem; |
| 1014 | if (! |
| 1015 | (priv->rxdb = |
| 1016 | bdx_rxdb_create(priv->rxf_fifo0.m.memsz / |
| 1017 | sizeof(struct rxf_desc)))) |
| 1018 | goto err_mem; |
| 1019 | |
| 1020 | priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN; |
| 1021 | return 0; |
| 1022 | |
| 1023 | err_mem: |
| 1024 | ERR("%s: %s: Rx init failed\n", BDX_DRV_NAME, priv->ndev->name); |
| 1025 | return -ENOMEM; |
| 1026 | } |
| 1027 | |
| 1028 | /* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo |
| 1029 | * @priv - NIC private structure |
| 1030 | * @f - RXF fifo |
| 1031 | */ |
| 1032 | static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f) |
| 1033 | { |
| 1034 | struct rx_map *dm; |
| 1035 | struct rxdb *db = priv->rxdb; |
| 1036 | u16 i; |
| 1037 | |
| 1038 | ENTER; |
| 1039 | DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db), |
| 1040 | db->nelem - bdx_rxdb_available(db)); |
| 1041 | while (bdx_rxdb_available(db) > 0) { |
| 1042 | i = bdx_rxdb_alloc_elem(db); |
| 1043 | dm = bdx_rxdb_addr_elem(db, i); |
| 1044 | dm->dma = 0; |
| 1045 | } |
| 1046 | for (i = 0; i < db->nelem; i++) { |
| 1047 | dm = bdx_rxdb_addr_elem(db, i); |
| 1048 | if (dm->dma) { |
| 1049 | pci_unmap_single(priv->pdev, |
| 1050 | dm->dma, f->m.pktsz, |
| 1051 | PCI_DMA_FROMDEVICE); |
| 1052 | dev_kfree_skb(dm->skb); |
| 1053 | } |
| 1054 | } |
| 1055 | } |
| 1056 | |
| 1057 | /* bdx_rx_free - release all Rx resources |
| 1058 | * @priv - NIC private structure |
| 1059 | * It assumes that Rx is desabled in HW |
| 1060 | */ |
| 1061 | static void bdx_rx_free(struct bdx_priv *priv) |
| 1062 | { |
| 1063 | ENTER; |
| 1064 | if (priv->rxdb) { |
| 1065 | bdx_rx_free_skbs(priv, &priv->rxf_fifo0); |
| 1066 | bdx_rxdb_destroy(priv->rxdb); |
| 1067 | priv->rxdb = NULL; |
| 1068 | } |
| 1069 | bdx_fifo_free(priv, &priv->rxf_fifo0.m); |
| 1070 | bdx_fifo_free(priv, &priv->rxd_fifo0.m); |
| 1071 | |
| 1072 | RET(); |
| 1073 | } |
| 1074 | |
| 1075 | /************************************************************************* |
| 1076 | * Rx Engine * |
| 1077 | *************************************************************************/ |
| 1078 | |
| 1079 | /* bdx_rx_alloc_skbs - fill rxf fifo with new skbs |
| 1080 | * @priv - nic's private structure |
| 1081 | * @f - RXF fifo that needs skbs |
| 1082 | * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo. |
| 1083 | * skb's virtual and physical addresses are stored in skb db. |
| 1084 | * To calculate free space, func uses cached values of RPTR and WPTR |
| 1085 | * When needed, it also updates RPTR and WPTR. |
| 1086 | */ |
| 1087 | |
| 1088 | /* TBD: do not update WPTR if no desc were written */ |
| 1089 | |
| 1090 | static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f) |
| 1091 | { |
| 1092 | struct sk_buff *skb; |
| 1093 | struct rxf_desc *rxfd; |
| 1094 | struct rx_map *dm; |
| 1095 | int dno, delta, idx; |
| 1096 | struct rxdb *db = priv->rxdb; |
| 1097 | |
| 1098 | ENTER; |
| 1099 | dno = bdx_rxdb_available(db) - 1; |
| 1100 | while (dno > 0) { |
| 1101 | if (!(skb = dev_alloc_skb(f->m.pktsz + NET_IP_ALIGN))) { |
| 1102 | ERR("NO MEM: dev_alloc_skb failed\n"); |
| 1103 | break; |
| 1104 | } |
| 1105 | skb->dev = priv->ndev; |
| 1106 | skb_reserve(skb, NET_IP_ALIGN); |
| 1107 | |
| 1108 | idx = bdx_rxdb_alloc_elem(db); |
| 1109 | dm = bdx_rxdb_addr_elem(db, idx); |
| 1110 | dm->dma = pci_map_single(priv->pdev, |
| 1111 | skb->data, f->m.pktsz, |
| 1112 | PCI_DMA_FROMDEVICE); |
| 1113 | dm->skb = skb; |
| 1114 | rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); |
| 1115 | rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */ |
| 1116 | rxfd->va_lo = idx; |
| 1117 | rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma)); |
| 1118 | rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma)); |
| 1119 | rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz); |
| 1120 | print_rxfd(rxfd); |
| 1121 | |
| 1122 | f->m.wptr += sizeof(struct rxf_desc); |
| 1123 | delta = f->m.wptr - f->m.memsz; |
| 1124 | if (unlikely(delta >= 0)) { |
| 1125 | f->m.wptr = delta; |
| 1126 | if (delta > 0) { |
| 1127 | memcpy(f->m.va, f->m.va + f->m.memsz, delta); |
| 1128 | DBG("wrapped descriptor\n"); |
| 1129 | } |
| 1130 | } |
| 1131 | dno--; |
| 1132 | } |
| 1133 | /*TBD: to do - delayed rxf wptr like in txd */ |
| 1134 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); |
| 1135 | RET(); |
| 1136 | } |
| 1137 | |
| 1138 | static inline void |
| 1139 | NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan, |
| 1140 | struct sk_buff *skb) |
| 1141 | { |
| 1142 | ENTER; |
| 1143 | DBG("rxdd->flags.bits.vtag=%d vlgrp=%p\n", GET_RXD_VTAG(rxd_val1), |
| 1144 | priv->vlgrp); |
| 1145 | if (priv->vlgrp && GET_RXD_VTAG(rxd_val1)) { |
| 1146 | DBG("%s: vlan rcv vlan '%x' vtag '%x', device name '%s'\n", |
| 1147 | priv->ndev->name, |
| 1148 | GET_RXD_VLAN_ID(rxd_vlan), |
| 1149 | GET_RXD_VTAG(rxd_val1), |
| 1150 | vlan_group_get_device(priv->vlgrp, |
| 1151 | GET_RXD_VLAN_ID(rxd_vlan))->name); |
| 1152 | /* NAPI variant of receive functions */ |
| 1153 | vlan_hwaccel_receive_skb(skb, priv->vlgrp, |
| 1154 | GET_RXD_VLAN_ID(rxd_vlan)); |
| 1155 | } else { |
| 1156 | netif_receive_skb(skb); |
| 1157 | } |
| 1158 | } |
| 1159 | |
| 1160 | static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd) |
| 1161 | { |
| 1162 | struct rxf_desc *rxfd; |
| 1163 | struct rx_map *dm; |
| 1164 | struct rxf_fifo *f; |
| 1165 | struct rxdb *db; |
| 1166 | struct sk_buff *skb; |
| 1167 | int delta; |
| 1168 | |
| 1169 | ENTER; |
| 1170 | DBG("priv=%p rxdd=%p\n", priv, rxdd); |
| 1171 | f = &priv->rxf_fifo0; |
| 1172 | db = priv->rxdb; |
| 1173 | DBG("db=%p f=%p\n", db, f); |
| 1174 | dm = bdx_rxdb_addr_elem(db, rxdd->va_lo); |
| 1175 | DBG("dm=%p\n", dm); |
| 1176 | skb = dm->skb; |
| 1177 | rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); |
| 1178 | rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */ |
| 1179 | rxfd->va_lo = rxdd->va_lo; |
| 1180 | rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma)); |
| 1181 | rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma)); |
| 1182 | rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz); |
| 1183 | print_rxfd(rxfd); |
| 1184 | |
| 1185 | f->m.wptr += sizeof(struct rxf_desc); |
| 1186 | delta = f->m.wptr - f->m.memsz; |
| 1187 | if (unlikely(delta >= 0)) { |
| 1188 | f->m.wptr = delta; |
| 1189 | if (delta > 0) { |
| 1190 | memcpy(f->m.va, f->m.va + f->m.memsz, delta); |
| 1191 | DBG("wrapped descriptor\n"); |
| 1192 | } |
| 1193 | } |
| 1194 | RET(); |
| 1195 | } |
| 1196 | |
| 1197 | /* bdx_rx_receive - recieves full packets from RXD fifo and pass them to OS |
| 1198 | * NOTE: a special treatment is given to non-continous descriptors |
| 1199 | * that start near the end, wraps around and continue at the beginning. a second |
| 1200 | * part is copied right after the first, and then descriptor is interpreted as |
| 1201 | * normal. fifo has an extra space to allow such operations |
| 1202 | * @priv - nic's private structure |
| 1203 | * @f - RXF fifo that needs skbs |
| 1204 | */ |
| 1205 | |
| 1206 | /* TBD: replace memcpy func call by explicite inline asm */ |
| 1207 | |
| 1208 | static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget) |
| 1209 | { |
| 1210 | struct sk_buff *skb, *skb2; |
| 1211 | struct rxd_desc *rxdd; |
| 1212 | struct rx_map *dm; |
| 1213 | struct rxf_fifo *rxf_fifo; |
| 1214 | int tmp_len, size; |
| 1215 | int done = 0; |
| 1216 | int max_done = BDX_MAX_RX_DONE; |
| 1217 | struct rxdb *db = NULL; |
| 1218 | /* Unmarshalled descriptor - copy of descriptor in host order */ |
| 1219 | u32 rxd_val1; |
| 1220 | u16 len; |
| 1221 | u16 rxd_vlan; |
| 1222 | |
| 1223 | ENTER; |
| 1224 | max_done = budget; |
| 1225 | |
| 1226 | priv->ndev->last_rx = jiffies; |
| 1227 | f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR; |
| 1228 | |
| 1229 | size = f->m.wptr - f->m.rptr; |
| 1230 | if (size < 0) |
| 1231 | size = f->m.memsz + size; /* size is negative :-) */ |
| 1232 | |
| 1233 | while (size > 0) { |
| 1234 | |
| 1235 | rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr); |
| 1236 | rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1); |
| 1237 | |
| 1238 | len = CPU_CHIP_SWAP16(rxdd->len); |
| 1239 | |
| 1240 | rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan); |
| 1241 | |
| 1242 | print_rxdd(rxdd, rxd_val1, len, rxd_vlan); |
| 1243 | |
| 1244 | tmp_len = GET_RXD_BC(rxd_val1) << 3; |
| 1245 | BDX_ASSERT(tmp_len <= 0); |
| 1246 | size -= tmp_len; |
| 1247 | if (size < 0) /* test for partially arrived descriptor */ |
| 1248 | break; |
| 1249 | |
| 1250 | f->m.rptr += tmp_len; |
| 1251 | |
| 1252 | tmp_len = f->m.rptr - f->m.memsz; |
| 1253 | if (unlikely(tmp_len >= 0)) { |
| 1254 | f->m.rptr = tmp_len; |
| 1255 | if (tmp_len > 0) { |
| 1256 | DBG("wrapped desc rptr=%d tmp_len=%d\n", |
| 1257 | f->m.rptr, tmp_len); |
| 1258 | memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len); |
| 1259 | } |
| 1260 | } |
| 1261 | |
| 1262 | if (unlikely(GET_RXD_ERR(rxd_val1))) { |
| 1263 | DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1)); |
| 1264 | priv->net_stats.rx_errors++; |
| 1265 | bdx_recycle_skb(priv, rxdd); |
| 1266 | continue; |
| 1267 | } |
| 1268 | |
| 1269 | rxf_fifo = &priv->rxf_fifo0; |
| 1270 | db = priv->rxdb; |
| 1271 | dm = bdx_rxdb_addr_elem(db, rxdd->va_lo); |
| 1272 | skb = dm->skb; |
| 1273 | |
| 1274 | if (len < BDX_COPYBREAK && |
| 1275 | (skb2 = dev_alloc_skb(len + NET_IP_ALIGN))) { |
| 1276 | skb_reserve(skb2, NET_IP_ALIGN); |
| 1277 | /*skb_put(skb2, len); */ |
| 1278 | pci_dma_sync_single_for_cpu(priv->pdev, |
| 1279 | dm->dma, rxf_fifo->m.pktsz, |
| 1280 | PCI_DMA_FROMDEVICE); |
| 1281 | memcpy(skb2->data, skb->data, len); |
| 1282 | bdx_recycle_skb(priv, rxdd); |
| 1283 | skb = skb2; |
| 1284 | } else { |
| 1285 | pci_unmap_single(priv->pdev, |
| 1286 | dm->dma, rxf_fifo->m.pktsz, |
| 1287 | PCI_DMA_FROMDEVICE); |
| 1288 | bdx_rxdb_free_elem(db, rxdd->va_lo); |
| 1289 | } |
| 1290 | |
| 1291 | priv->net_stats.rx_bytes += len; |
| 1292 | |
| 1293 | skb_put(skb, len); |
| 1294 | skb->dev = priv->ndev; |
| 1295 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 1296 | skb->protocol = eth_type_trans(skb, priv->ndev); |
| 1297 | |
| 1298 | /* Non-IP packets aren't checksum-offloaded */ |
| 1299 | if (GET_RXD_PKT_ID(rxd_val1) == 0) |
| 1300 | skb->ip_summed = CHECKSUM_NONE; |
| 1301 | |
| 1302 | NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb); |
| 1303 | |
| 1304 | if (++done >= max_done) |
| 1305 | break; |
| 1306 | } |
| 1307 | |
| 1308 | priv->net_stats.rx_packets += done; |
| 1309 | |
| 1310 | /* FIXME: do smth to minimize pci accesses */ |
| 1311 | WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); |
| 1312 | |
| 1313 | bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); |
| 1314 | |
| 1315 | RET(done); |
| 1316 | } |
| 1317 | |
| 1318 | /************************************************************************* |
| 1319 | * Debug / Temprorary Code * |
| 1320 | *************************************************************************/ |
| 1321 | static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len, |
| 1322 | u16 rxd_vlan) |
| 1323 | { |
| 1324 | DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d " |
| 1325 | "pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d " |
| 1326 | "va_lo %d va_hi %d\n", |
| 1327 | GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1), |
| 1328 | GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1), |
| 1329 | GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1), |
| 1330 | GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan), |
| 1331 | GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo, |
| 1332 | rxdd->va_hi); |
| 1333 | } |
| 1334 | |
| 1335 | static void print_rxfd(struct rxf_desc *rxfd) |
| 1336 | { |
| 1337 | DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n" |
| 1338 | "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n", |
| 1339 | rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len); |
| 1340 | } |
| 1341 | |
| 1342 | /* |
| 1343 | * TX HW/SW interaction overview |
| 1344 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1345 | * There are 2 types of TX communication channels betwean driver and NIC. |
| 1346 | * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets |
| 1347 | * 2) TX Data Fifo - TXD - holds descriptors of full buffers. |
| 1348 | * |
| 1349 | * Currently NIC supports TSO, checksuming and gather DMA |
| 1350 | * UFO and IP fragmentation is on the way |
| 1351 | * |
| 1352 | * RX SW Data Structures |
| 1353 | * ~~~~~~~~~~~~~~~~~~~~~ |
| 1354 | * txdb - used to keep track of all skbs owned by SW and their dma addresses. |
| 1355 | * For TX case, ownership lasts from geting packet via hard_xmit and until HW |
| 1356 | * acknowledges sent by TXF descriptors. |
| 1357 | * Implemented as cyclic buffer. |
| 1358 | * fifo - keeps info about fifo's size and location, relevant HW registers, |
| 1359 | * usage and skb db. Each RXD and RXF Fifo has its own fifo structure. |
| 1360 | * Implemented as simple struct. |
| 1361 | * |
| 1362 | * TX SW Execution Flow |
| 1363 | * ~~~~~~~~~~~~~~~~~~~~ |
| 1364 | * OS calls driver's hard_xmit method with packet to sent. |
| 1365 | * Driver creates DMA mappings, builds TXD descriptors and kicks HW |
| 1366 | * by updating TXD WPTR. |
| 1367 | * When packet is sent, HW write us TXF descriptor and SW frees original skb. |
| 1368 | * To prevent TXD fifo overflow without reading HW registers every time, |
| 1369 | * SW deploys "tx level" technique. |
| 1370 | * Upon strart up, tx level is initialized to TXD fifo length. |
| 1371 | * For every sent packet, SW gets its TXD descriptor sizei |
| 1372 | * (from precalculated array) and substructs it from tx level. |
| 1373 | * The size is also stored in txdb. When TXF ack arrives, SW fetch size of |
| 1374 | * original TXD descriptor from txdb and adds it to tx level. |
| 1375 | * When Tx level drops under some predefined treshhold, the driver |
| 1376 | * stops the TX queue. When TX level rises above that level, |
| 1377 | * the tx queue is enabled again. |
| 1378 | * |
| 1379 | * This technique avoids eccessive reading of RPTR and WPTR registers. |
| 1380 | * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput. |
| 1381 | */ |
| 1382 | |
| 1383 | /************************************************************************* |
| 1384 | * Tx DB * |
| 1385 | *************************************************************************/ |
| 1386 | static inline int bdx_tx_db_size(struct txdb *db) |
| 1387 | { |
| 1388 | int taken = db->wptr - db->rptr; |
| 1389 | if (taken < 0) |
| 1390 | taken = db->size + 1 + taken; /* (size + 1) equals memsz */ |
| 1391 | |
| 1392 | return db->size - taken; |
| 1393 | } |
| 1394 | |
| 1395 | /* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap |
| 1396 | * @d - tx data base |
| 1397 | * @ptr - read or write pointer |
| 1398 | */ |
| 1399 | static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr) |
| 1400 | { |
| 1401 | BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */ |
| 1402 | |
| 1403 | BDX_ASSERT(*pptr != db->rptr && /* expect either read */ |
| 1404 | *pptr != db->wptr); /* or write pointer */ |
| 1405 | |
| 1406 | BDX_ASSERT(*pptr < db->start || /* pointer has to be */ |
| 1407 | *pptr >= db->end); /* in range */ |
| 1408 | |
| 1409 | ++*pptr; |
| 1410 | if (unlikely(*pptr == db->end)) |
| 1411 | *pptr = db->start; |
| 1412 | } |
| 1413 | |
| 1414 | /* bdx_tx_db_inc_rptr - increment read pointer |
| 1415 | * @d - tx data base |
| 1416 | */ |
| 1417 | static inline void bdx_tx_db_inc_rptr(struct txdb *db) |
| 1418 | { |
| 1419 | BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */ |
| 1420 | __bdx_tx_db_ptr_next(db, &db->rptr); |
| 1421 | } |
| 1422 | |
| 1423 | /* bdx_tx_db_inc_rptr - increment write pointer |
| 1424 | * @d - tx data base |
| 1425 | */ |
| 1426 | static inline void bdx_tx_db_inc_wptr(struct txdb *db) |
| 1427 | { |
| 1428 | __bdx_tx_db_ptr_next(db, &db->wptr); |
| 1429 | BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as |
| 1430 | a result of write */ |
| 1431 | } |
| 1432 | |
| 1433 | /* bdx_tx_db_init - creates and initializes tx db |
| 1434 | * @d - tx data base |
| 1435 | * @sz_type - size of tx fifo |
| 1436 | * Returns 0 on success, error code otherwise |
| 1437 | */ |
| 1438 | static int bdx_tx_db_init(struct txdb *d, int sz_type) |
| 1439 | { |
| 1440 | int memsz = FIFO_SIZE * (1 << (sz_type + 1)); |
| 1441 | |
| 1442 | d->start = vmalloc(memsz); |
| 1443 | if (!d->start) |
| 1444 | return -ENOMEM; |
| 1445 | |
| 1446 | /* |
| 1447 | * In order to differentiate between db is empty and db is full |
| 1448 | * states at least one element should always be empty in order to |
| 1449 | * avoid rptr == wptr which means db is empty |
| 1450 | */ |
| 1451 | d->size = memsz / sizeof(struct tx_map) - 1; |
| 1452 | d->end = d->start + d->size + 1; /* just after last element */ |
| 1453 | |
| 1454 | /* all dbs are created equally empty */ |
| 1455 | d->rptr = d->start; |
| 1456 | d->wptr = d->start; |
| 1457 | |
| 1458 | return 0; |
| 1459 | } |
| 1460 | |
| 1461 | /* bdx_tx_db_close - closes tx db and frees all memory |
| 1462 | * @d - tx data base |
| 1463 | */ |
| 1464 | static void bdx_tx_db_close(struct txdb *d) |
| 1465 | { |
| 1466 | BDX_ASSERT(d == NULL); |
| 1467 | |
| 1468 | if (d->start) { |
| 1469 | vfree(d->start); |
| 1470 | d->start = NULL; |
| 1471 | } |
| 1472 | } |
| 1473 | |
| 1474 | /************************************************************************* |
| 1475 | * Tx Engine * |
| 1476 | *************************************************************************/ |
| 1477 | |
| 1478 | /* sizes of tx desc (including padding if needed) as function |
| 1479 | * of skb's frag number */ |
| 1480 | static struct { |
| 1481 | u16 bytes; |
| 1482 | u16 qwords; /* qword = 64 bit */ |
| 1483 | } txd_sizes[MAX_SKB_FRAGS + 1]; |
| 1484 | |
| 1485 | /* txdb_map_skb - creates and stores dma mappings for skb's data blocks |
| 1486 | * @priv - NIC private structure |
| 1487 | * @skb - socket buffer to map |
| 1488 | * |
| 1489 | * It makes dma mappings for skb's data blocks and writes them to PBL of |
| 1490 | * new tx descriptor. It also stores them in the tx db, so they could be |
| 1491 | * unmaped after data was sent. It is reponsibility of a caller to make |
| 1492 | * sure that there is enough space in the tx db. Last element holds pointer |
| 1493 | * to skb itself and marked with zero length |
| 1494 | */ |
| 1495 | static inline void |
| 1496 | bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb, |
| 1497 | struct txd_desc *txdd) |
| 1498 | { |
| 1499 | struct txdb *db = &priv->txdb; |
| 1500 | struct pbl *pbl = &txdd->pbl[0]; |
| 1501 | int nr_frags = skb_shinfo(skb)->nr_frags; |
| 1502 | int i; |
| 1503 | |
| 1504 | db->wptr->len = skb->len - skb->data_len; |
| 1505 | db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data, |
| 1506 | db->wptr->len, PCI_DMA_TODEVICE); |
| 1507 | pbl->len = CPU_CHIP_SWAP32(db->wptr->len); |
| 1508 | pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); |
| 1509 | pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); |
| 1510 | DBG("=== pbl len: 0x%x ================\n", pbl->len); |
| 1511 | DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo); |
| 1512 | DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi); |
| 1513 | bdx_tx_db_inc_wptr(db); |
| 1514 | |
| 1515 | for (i = 0; i < nr_frags; i++) { |
| 1516 | struct skb_frag_struct *frag; |
| 1517 | |
| 1518 | frag = &skb_shinfo(skb)->frags[i]; |
| 1519 | db->wptr->len = frag->size; |
| 1520 | db->wptr->addr.dma = |
| 1521 | pci_map_page(priv->pdev, frag->page, frag->page_offset, |
| 1522 | frag->size, PCI_DMA_TODEVICE); |
| 1523 | |
| 1524 | pbl++; |
| 1525 | pbl->len = CPU_CHIP_SWAP32(db->wptr->len); |
| 1526 | pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); |
| 1527 | pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); |
| 1528 | bdx_tx_db_inc_wptr(db); |
| 1529 | } |
| 1530 | |
| 1531 | /* add skb clean up info. */ |
| 1532 | db->wptr->len = -txd_sizes[nr_frags].bytes; |
| 1533 | db->wptr->addr.skb = skb; |
| 1534 | bdx_tx_db_inc_wptr(db); |
| 1535 | } |
| 1536 | |
| 1537 | /* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags |
| 1538 | * number of frags is used as index to fetch correct descriptors size, |
| 1539 | * instead of calculating it each time */ |
| 1540 | static void __init init_txd_sizes(void) |
| 1541 | { |
| 1542 | int i, lwords; |
| 1543 | |
| 1544 | /* 7 - is number of lwords in txd with one phys buffer |
| 1545 | * 3 - is number of lwords used for every additional phys buffer */ |
| 1546 | for (i = 0; i < MAX_SKB_FRAGS + 1; i++) { |
| 1547 | lwords = 7 + (i * 3); |
| 1548 | if (lwords & 1) |
| 1549 | lwords++; /* pad it with 1 lword */ |
| 1550 | txd_sizes[i].qwords = lwords >> 1; |
| 1551 | txd_sizes[i].bytes = lwords << 2; |
| 1552 | } |
| 1553 | } |
| 1554 | |
| 1555 | /* bdx_tx_init - initialize all Tx related stuff. |
| 1556 | * Namely, TXD and TXF fifos, database etc */ |
| 1557 | static int bdx_tx_init(struct bdx_priv *priv) |
| 1558 | { |
| 1559 | if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size, |
| 1560 | regTXD_CFG0_0, |
| 1561 | regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0)) |
| 1562 | goto err_mem; |
| 1563 | if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size, |
| 1564 | regTXF_CFG0_0, |
| 1565 | regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0)) |
| 1566 | goto err_mem; |
| 1567 | |
| 1568 | /* The TX db has to keep mappings for all packets sent (on TxD) |
| 1569 | * and not yet reclaimed (on TxF) */ |
| 1570 | if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size))) |
| 1571 | goto err_mem; |
| 1572 | |
| 1573 | priv->tx_level = BDX_MAX_TX_LEVEL; |
| 1574 | #ifdef BDX_DELAY_WPTR |
| 1575 | priv->tx_update_mark = priv->tx_level - 1024; |
| 1576 | #endif |
| 1577 | return 0; |
| 1578 | |
| 1579 | err_mem: |
| 1580 | ERR("tehuti: %s: Tx init failed\n", priv->ndev->name); |
| 1581 | return -ENOMEM; |
| 1582 | } |
| 1583 | |
| 1584 | /* |
| 1585 | * bdx_tx_space - calculates avalable space in TX fifo |
| 1586 | * @priv - NIC private structure |
| 1587 | * Returns avaliable space in TX fifo in bytes |
| 1588 | */ |
| 1589 | static inline int bdx_tx_space(struct bdx_priv *priv) |
| 1590 | { |
| 1591 | struct txd_fifo *f = &priv->txd_fifo0; |
| 1592 | int fsize; |
| 1593 | |
| 1594 | f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR; |
| 1595 | fsize = f->m.rptr - f->m.wptr; |
| 1596 | if (fsize <= 0) |
| 1597 | fsize = f->m.memsz + fsize; |
| 1598 | return (fsize); |
| 1599 | } |
| 1600 | |
| 1601 | /* bdx_tx_transmit - send packet to NIC |
| 1602 | * @skb - packet to send |
| 1603 | * ndev - network device assigned to NIC |
| 1604 | * Return codes: |
| 1605 | * o NETDEV_TX_OK everything ok. |
| 1606 | * o NETDEV_TX_BUSY Cannot transmit packet, try later |
| 1607 | * Usually a bug, means queue start/stop flow control is broken in |
| 1608 | * the driver. Note: the driver must NOT put the skb in its DMA ring. |
| 1609 | * o NETDEV_TX_LOCKED Locking failed, please retry quickly. |
| 1610 | */ |
| 1611 | static int bdx_tx_transmit(struct sk_buff *skb, struct net_device *ndev) |
| 1612 | { |
| 1613 | struct bdx_priv *priv = ndev->priv; |
| 1614 | struct txd_fifo *f = &priv->txd_fifo0; |
| 1615 | int txd_checksum = 7; /* full checksum */ |
| 1616 | int txd_lgsnd = 0; |
| 1617 | int txd_vlan_id = 0; |
| 1618 | int txd_vtag = 0; |
| 1619 | int txd_mss = 0; |
| 1620 | |
| 1621 | int nr_frags = skb_shinfo(skb)->nr_frags; |
| 1622 | struct txd_desc *txdd; |
| 1623 | int len; |
| 1624 | unsigned long flags; |
| 1625 | |
| 1626 | ENTER; |
| 1627 | local_irq_save(flags); |
| 1628 | if (!spin_trylock(&priv->tx_lock)) { |
| 1629 | local_irq_restore(flags); |
| 1630 | DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n", |
| 1631 | BDX_DRV_NAME, ndev->name); |
| 1632 | return NETDEV_TX_LOCKED; |
| 1633 | } |
| 1634 | |
| 1635 | /* build tx descriptor */ |
| 1636 | BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */ |
| 1637 | txdd = (struct txd_desc *)(f->m.va + f->m.wptr); |
| 1638 | if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) |
| 1639 | txd_checksum = 0; |
| 1640 | |
| 1641 | if (skb_shinfo(skb)->gso_size) { |
| 1642 | txd_mss = skb_shinfo(skb)->gso_size; |
| 1643 | txd_lgsnd = 1; |
| 1644 | DBG("skb %p skb len %d gso size = %d\n", skb, skb->len, |
| 1645 | txd_mss); |
| 1646 | } |
| 1647 | |
| 1648 | if (vlan_tx_tag_present(skb)) { |
| 1649 | /*Cut VLAN ID to 12 bits */ |
| 1650 | txd_vlan_id = vlan_tx_tag_get(skb) & BITS_MASK(12); |
| 1651 | txd_vtag = 1; |
| 1652 | } |
| 1653 | |
| 1654 | txdd->length = CPU_CHIP_SWAP16(skb->len); |
| 1655 | txdd->mss = CPU_CHIP_SWAP16(txd_mss); |
| 1656 | txdd->txd_val1 = |
| 1657 | CPU_CHIP_SWAP32(TXD_W1_VAL |
| 1658 | (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag, |
| 1659 | txd_lgsnd, txd_vlan_id)); |
| 1660 | DBG("=== TxD desc =====================\n"); |
| 1661 | DBG("=== w1: 0x%x ================\n", txdd->txd_val1); |
| 1662 | DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length); |
| 1663 | |
| 1664 | bdx_tx_map_skb(priv, skb, txdd); |
| 1665 | |
| 1666 | /* increment TXD write pointer. In case of |
| 1667 | fifo wrapping copy reminder of the descriptor |
| 1668 | to the beginning */ |
| 1669 | f->m.wptr += txd_sizes[nr_frags].bytes; |
| 1670 | len = f->m.wptr - f->m.memsz; |
| 1671 | if (unlikely(len >= 0)) { |
| 1672 | f->m.wptr = len; |
| 1673 | if (len > 0) { |
| 1674 | BDX_ASSERT(len > f->m.memsz); |
| 1675 | memcpy(f->m.va, f->m.va + f->m.memsz, len); |
| 1676 | } |
| 1677 | } |
| 1678 | BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */ |
| 1679 | |
| 1680 | priv->tx_level -= txd_sizes[nr_frags].bytes; |
| 1681 | BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL); |
| 1682 | #ifdef BDX_DELAY_WPTR |
| 1683 | if (priv->tx_level > priv->tx_update_mark) { |
| 1684 | /* Force memory writes to complete before letting h/w |
| 1685 | know there are new descriptors to fetch. |
| 1686 | (might be needed on platforms like IA64) |
| 1687 | wmb(); */ |
| 1688 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); |
| 1689 | } else { |
| 1690 | if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) { |
| 1691 | priv->tx_noupd = 0; |
| 1692 | WRITE_REG(priv, f->m.reg_WPTR, |
| 1693 | f->m.wptr & TXF_WPTR_WR_PTR); |
| 1694 | } |
| 1695 | } |
| 1696 | #else |
| 1697 | /* Force memory writes to complete before letting h/w |
| 1698 | know there are new descriptors to fetch. |
| 1699 | (might be needed on platforms like IA64) |
| 1700 | wmb(); */ |
| 1701 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); |
| 1702 | |
| 1703 | #endif |
| 1704 | ndev->trans_start = jiffies; |
| 1705 | |
| 1706 | priv->net_stats.tx_packets++; |
| 1707 | priv->net_stats.tx_bytes += skb->len; |
| 1708 | |
| 1709 | if (priv->tx_level < BDX_MIN_TX_LEVEL) { |
| 1710 | DBG("%s: %s: TX Q STOP level %d\n", |
| 1711 | BDX_DRV_NAME, ndev->name, priv->tx_level); |
| 1712 | netif_stop_queue(ndev); |
| 1713 | } |
| 1714 | |
| 1715 | spin_unlock_irqrestore(&priv->tx_lock, flags); |
| 1716 | return NETDEV_TX_OK; |
| 1717 | } |
| 1718 | |
| 1719 | /* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ. |
| 1720 | * @priv - bdx adapter |
| 1721 | * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS |
| 1722 | * that those packets were sent |
| 1723 | */ |
| 1724 | static void bdx_tx_cleanup(struct bdx_priv *priv) |
| 1725 | { |
| 1726 | struct txf_fifo *f = &priv->txf_fifo0; |
| 1727 | struct txdb *db = &priv->txdb; |
| 1728 | int tx_level = 0; |
| 1729 | |
| 1730 | ENTER; |
| 1731 | f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK; |
| 1732 | BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */ |
| 1733 | |
| 1734 | while (f->m.wptr != f->m.rptr) { |
| 1735 | f->m.rptr += BDX_TXF_DESC_SZ; |
| 1736 | f->m.rptr &= f->m.size_mask; |
| 1737 | |
| 1738 | /* unmap all the fragments */ |
| 1739 | /* first has to come tx_maps containing dma */ |
| 1740 | BDX_ASSERT(db->rptr->len == 0); |
| 1741 | do { |
| 1742 | BDX_ASSERT(db->rptr->addr.dma == 0); |
| 1743 | pci_unmap_page(priv->pdev, db->rptr->addr.dma, |
| 1744 | db->rptr->len, PCI_DMA_TODEVICE); |
| 1745 | bdx_tx_db_inc_rptr(db); |
| 1746 | } while (db->rptr->len > 0); |
| 1747 | tx_level -= db->rptr->len; /* '-' koz len is negative */ |
| 1748 | |
| 1749 | /* now should come skb pointer - free it */ |
| 1750 | BDX_ASSERT(db->rptr->addr.skb == 0); |
| 1751 | dev_kfree_skb_irq(db->rptr->addr.skb); |
| 1752 | bdx_tx_db_inc_rptr(db); |
| 1753 | } |
| 1754 | |
| 1755 | /* let h/w know which TXF descriptors were cleaned */ |
| 1756 | BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz); |
| 1757 | WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); |
| 1758 | |
| 1759 | /* We reclaimed resources, so in case the Q is stopped by xmit callback, |
| 1760 | * we resume the transmition and use tx_lock to synchronize with xmit.*/ |
| 1761 | spin_lock(&priv->tx_lock); |
| 1762 | priv->tx_level += tx_level; |
| 1763 | BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL); |
| 1764 | #ifdef BDX_DELAY_WPTR |
| 1765 | if (priv->tx_noupd) { |
| 1766 | priv->tx_noupd = 0; |
| 1767 | WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR, |
| 1768 | priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR); |
| 1769 | } |
| 1770 | #endif |
| 1771 | |
| 1772 | if (unlikely(netif_queue_stopped(priv->ndev) |
| 1773 | && netif_carrier_ok(priv->ndev) |
| 1774 | && (priv->tx_level >= BDX_MIN_TX_LEVEL))) { |
| 1775 | DBG("%s: %s: TX Q WAKE level %d\n", |
| 1776 | BDX_DRV_NAME, priv->ndev->name, priv->tx_level); |
| 1777 | netif_wake_queue(priv->ndev); |
| 1778 | } |
| 1779 | spin_unlock(&priv->tx_lock); |
| 1780 | } |
| 1781 | |
| 1782 | /* bdx_tx_free_skbs - frees all skbs from TXD fifo. |
| 1783 | * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod |
| 1784 | */ |
| 1785 | static void bdx_tx_free_skbs(struct bdx_priv *priv) |
| 1786 | { |
| 1787 | struct txdb *db = &priv->txdb; |
| 1788 | |
| 1789 | ENTER; |
| 1790 | while (db->rptr != db->wptr) { |
| 1791 | if (likely(db->rptr->len)) |
| 1792 | pci_unmap_page(priv->pdev, db->rptr->addr.dma, |
| 1793 | db->rptr->len, PCI_DMA_TODEVICE); |
| 1794 | else |
| 1795 | dev_kfree_skb(db->rptr->addr.skb); |
| 1796 | bdx_tx_db_inc_rptr(db); |
| 1797 | } |
| 1798 | RET(); |
| 1799 | } |
| 1800 | |
| 1801 | /* bdx_tx_free - frees all Tx resources */ |
| 1802 | static void bdx_tx_free(struct bdx_priv *priv) |
| 1803 | { |
| 1804 | ENTER; |
| 1805 | bdx_tx_free_skbs(priv); |
| 1806 | bdx_fifo_free(priv, &priv->txd_fifo0.m); |
| 1807 | bdx_fifo_free(priv, &priv->txf_fifo0.m); |
| 1808 | bdx_tx_db_close(&priv->txdb); |
| 1809 | } |
| 1810 | |
| 1811 | /* bdx_tx_push_desc - push descriptor to TxD fifo |
| 1812 | * @priv - NIC private structure |
| 1813 | * @data - desc's data |
| 1814 | * @size - desc's size |
| 1815 | * |
| 1816 | * Pushes desc to TxD fifo and overlaps it if needed. |
| 1817 | * NOTE: this func does not check for available space. this is responsibility |
| 1818 | * of the caller. Neither does it check that data size is smaller then |
| 1819 | * fifo size. |
| 1820 | */ |
| 1821 | static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size) |
| 1822 | { |
| 1823 | struct txd_fifo *f = &priv->txd_fifo0; |
| 1824 | int i = f->m.memsz - f->m.wptr; |
| 1825 | |
| 1826 | if (size == 0) |
| 1827 | return; |
| 1828 | |
| 1829 | if (i > size) { |
| 1830 | memcpy(f->m.va + f->m.wptr, data, size); |
| 1831 | f->m.wptr += size; |
| 1832 | } else { |
| 1833 | memcpy(f->m.va + f->m.wptr, data, i); |
| 1834 | f->m.wptr = size - i; |
| 1835 | memcpy(f->m.va, data + i, f->m.wptr); |
| 1836 | } |
| 1837 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); |
| 1838 | } |
| 1839 | |
| 1840 | /* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way |
| 1841 | * @priv - NIC private structure |
| 1842 | * @data - desc's data |
| 1843 | * @size - desc's size |
| 1844 | * |
| 1845 | * NOTE: this func does check for available space and, if neccessary, waits for |
| 1846 | * NIC to read existing data before writing new one. |
| 1847 | */ |
| 1848 | static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size) |
| 1849 | { |
| 1850 | int timer = 0; |
| 1851 | ENTER; |
| 1852 | |
| 1853 | while (size > 0) { |
| 1854 | /* we substruct 8 because when fifo is full rptr == wptr |
| 1855 | which also means that fifo is empty, we can understand |
| 1856 | the difference, but could hw do the same ??? :) */ |
| 1857 | int avail = bdx_tx_space(priv) - 8; |
| 1858 | if (avail <= 0) { |
| 1859 | if (timer++ > 300) { /* prevent endless loop */ |
| 1860 | DBG("timeout while writing desc to TxD fifo\n"); |
| 1861 | break; |
| 1862 | } |
| 1863 | udelay(50); /* give hw a chance to clean fifo */ |
| 1864 | continue; |
| 1865 | } |
| 1866 | avail = MIN(avail, size); |
| 1867 | DBG("about to push %d bytes starting %p size %d\n", avail, |
| 1868 | data, size); |
| 1869 | bdx_tx_push_desc(priv, data, avail); |
| 1870 | size -= avail; |
| 1871 | data += avail; |
| 1872 | } |
| 1873 | RET(); |
| 1874 | } |
| 1875 | |
| 1876 | /** |
| 1877 | * bdx_probe - Device Initialization Routine |
| 1878 | * @pdev: PCI device information struct |
| 1879 | * @ent: entry in bdx_pci_tbl |
| 1880 | * |
| 1881 | * Returns 0 on success, negative on failure |
| 1882 | * |
| 1883 | * bdx_probe initializes an adapter identified by a pci_dev structure. |
| 1884 | * The OS initialization, configuring of the adapter private structure, |
| 1885 | * and a hardware reset occur. |
| 1886 | * |
| 1887 | * functions and their order used as explained in |
| 1888 | * /usr/src/linux/Documentation/DMA-{API,mapping}.txt |
| 1889 | * |
| 1890 | */ |
| 1891 | |
| 1892 | /* TBD: netif_msg should be checked and implemented. I disable it for now */ |
| 1893 | static int __devinit |
| 1894 | bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 1895 | { |
| 1896 | struct net_device *ndev; |
| 1897 | struct bdx_priv *priv; |
| 1898 | int err, pci_using_dac, port; |
| 1899 | unsigned long pciaddr; |
| 1900 | u32 regionSize; |
| 1901 | struct pci_nic *nic; |
| 1902 | |
| 1903 | ENTER; |
| 1904 | |
| 1905 | nic = vmalloc(sizeof(*nic)); |
| 1906 | if (!nic) |
| 1907 | RET(-ENOMEM); |
| 1908 | |
| 1909 | /************** pci *****************/ |
| 1910 | if ((err = pci_enable_device(pdev))) /* it trigers interrupt, dunno why. */ |
| 1911 | RET(err); /* it's not a problem though */ |
| 1912 | |
| 1913 | if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) && |
| 1914 | !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) { |
| 1915 | pci_using_dac = 1; |
| 1916 | } else { |
| 1917 | if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) || |
| 1918 | (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) { |
| 1919 | printk(KERN_ERR "tehuti: No usable DMA configuration" |
| 1920 | ", aborting\n"); |
| 1921 | goto err_dma; |
| 1922 | } |
| 1923 | pci_using_dac = 0; |
| 1924 | } |
| 1925 | |
| 1926 | if ((err = pci_request_regions(pdev, BDX_DRV_NAME))) |
| 1927 | goto err_dma; |
| 1928 | |
| 1929 | pci_set_master(pdev); |
| 1930 | |
| 1931 | pciaddr = pci_resource_start(pdev, 0); |
| 1932 | if (!pciaddr) { |
| 1933 | err = -EIO; |
| 1934 | ERR("tehuti: no MMIO resource\n"); |
| 1935 | goto err_out_res; |
| 1936 | } |
| 1937 | if ((regionSize = pci_resource_len(pdev, 0)) < BDX_REGS_SIZE) { |
| 1938 | err = -EIO; |
| 1939 | ERR("tehuti: MMIO resource (%x) too small\n", regionSize); |
| 1940 | goto err_out_res; |
| 1941 | } |
| 1942 | |
| 1943 | nic->regs = ioremap(pciaddr, regionSize); |
| 1944 | if (!nic->regs) { |
| 1945 | err = -EIO; |
| 1946 | ERR("tehuti: ioremap failed\n"); |
| 1947 | goto err_out_res; |
| 1948 | } |
| 1949 | |
| 1950 | if (pdev->irq < 2) { |
| 1951 | err = -EIO; |
| 1952 | ERR("tehuti: invalid irq (%d)\n", pdev->irq); |
| 1953 | goto err_out_iomap; |
| 1954 | } |
| 1955 | pci_set_drvdata(pdev, nic); |
| 1956 | |
| 1957 | if (pdev->device == 0x3014) |
| 1958 | nic->port_num = 2; |
| 1959 | else |
| 1960 | nic->port_num = 1; |
| 1961 | |
| 1962 | print_hw_id(pdev); |
| 1963 | |
| 1964 | bdx_hw_reset_direct(nic->regs); |
| 1965 | |
| 1966 | nic->irq_type = IRQ_INTX; |
| 1967 | #ifdef BDX_MSI |
| 1968 | if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) { |
| 1969 | if ((err = pci_enable_msi(pdev))) |
| 1970 | ERR("Tehuti: Can't eneble msi. error is %d\n", err); |
| 1971 | else |
| 1972 | nic->irq_type = IRQ_MSI; |
| 1973 | } else |
| 1974 | DBG("HW does not support MSI\n"); |
| 1975 | #endif |
| 1976 | |
| 1977 | /************** netdev **************/ |
| 1978 | for (port = 0; port < nic->port_num; port++) { |
| 1979 | if (!(ndev = alloc_etherdev(sizeof(struct bdx_priv)))) { |
| 1980 | err = -ENOMEM; |
| 1981 | printk(KERN_ERR "tehuti: alloc_etherdev failed\n"); |
| 1982 | goto err_out_iomap; |
| 1983 | } |
| 1984 | |
| 1985 | ndev->open = bdx_open; |
| 1986 | ndev->stop = bdx_close; |
| 1987 | ndev->hard_start_xmit = bdx_tx_transmit; |
| 1988 | ndev->do_ioctl = bdx_ioctl; |
| 1989 | ndev->set_multicast_list = bdx_setmulti; |
| 1990 | ndev->get_stats = bdx_get_stats; |
| 1991 | ndev->change_mtu = bdx_change_mtu; |
| 1992 | ndev->set_mac_address = bdx_set_mac; |
| 1993 | ndev->tx_queue_len = BDX_NDEV_TXQ_LEN; |
| 1994 | ndev->vlan_rx_register = bdx_vlan_rx_register; |
| 1995 | ndev->vlan_rx_add_vid = bdx_vlan_rx_add_vid; |
| 1996 | ndev->vlan_rx_kill_vid = bdx_vlan_rx_kill_vid; |
| 1997 | |
| 1998 | bdx_ethtool_ops(ndev); /* ethtool interface */ |
| 1999 | |
| 2000 | /* these fields are used for info purposes only |
| 2001 | * so we can have them same for all ports of the board */ |
| 2002 | ndev->if_port = port; |
| 2003 | ndev->base_addr = pciaddr; |
| 2004 | ndev->mem_start = pciaddr; |
| 2005 | ndev->mem_end = pciaddr + regionSize; |
| 2006 | ndev->irq = pdev->irq; |
| 2007 | ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO |
| 2008 | | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX | |
| 2009 | NETIF_F_HW_VLAN_FILTER |
| 2010 | /*| NETIF_F_FRAGLIST */ |
| 2011 | ; |
| 2012 | |
| 2013 | if (pci_using_dac) |
| 2014 | ndev->features |= NETIF_F_HIGHDMA; |
| 2015 | |
| 2016 | /************** priv ****************/ |
| 2017 | priv = nic->priv[port] = ndev->priv; |
| 2018 | |
| 2019 | memset(priv, 0, sizeof(struct bdx_priv)); |
| 2020 | priv->pBdxRegs = nic->regs + port * 0x8000; |
| 2021 | priv->port = port; |
| 2022 | priv->pdev = pdev; |
| 2023 | priv->ndev = ndev; |
| 2024 | priv->nic = nic; |
| 2025 | priv->msg_enable = BDX_DEF_MSG_ENABLE; |
| 2026 | |
| 2027 | netif_napi_add(ndev, &priv->napi, bdx_poll, 64); |
| 2028 | |
| 2029 | if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) { |
| 2030 | DBG("HW statistics not supported\n"); |
| 2031 | priv->stats_flag = 0; |
| 2032 | } else { |
| 2033 | priv->stats_flag = 1; |
| 2034 | } |
| 2035 | |
| 2036 | /* Initialize fifo sizes. */ |
| 2037 | priv->txd_size = 2; |
| 2038 | priv->txf_size = 2; |
| 2039 | priv->rxd_size = 2; |
| 2040 | priv->rxf_size = 3; |
| 2041 | |
| 2042 | /* Initialize the initial coalescing registers. */ |
| 2043 | priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12); |
| 2044 | priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12); |
| 2045 | |
| 2046 | /* ndev->xmit_lock spinlock is not used. |
| 2047 | * Private priv->tx_lock is used for synchronization |
| 2048 | * between transmit and TX irq cleanup. In addition |
| 2049 | * set multicast list callback has to use priv->tx_lock. |
| 2050 | */ |
| 2051 | #ifdef BDX_LLTX |
| 2052 | ndev->features |= NETIF_F_LLTX; |
| 2053 | #endif |
| 2054 | spin_lock_init(&priv->tx_lock); |
| 2055 | |
| 2056 | /*bdx_hw_reset(priv); */ |
| 2057 | if (bdx_read_mac(priv)) { |
| 2058 | printk(KERN_ERR "tehuti: load MAC address failed\n"); |
| 2059 | goto err_out_iomap; |
| 2060 | } |
| 2061 | SET_NETDEV_DEV(ndev, &pdev->dev); |
| 2062 | if ((err = register_netdev(ndev))) { |
| 2063 | printk(KERN_ERR "tehuti: register_netdev failed\n"); |
| 2064 | goto err_out_free; |
| 2065 | } |
| 2066 | netif_carrier_off(ndev); |
| 2067 | netif_stop_queue(ndev); |
| 2068 | |
| 2069 | print_eth_id(ndev); |
| 2070 | } |
| 2071 | RET(0); |
| 2072 | |
| 2073 | err_out_free: |
| 2074 | free_netdev(ndev); |
| 2075 | err_out_iomap: |
| 2076 | iounmap(nic->regs); |
| 2077 | err_out_res: |
| 2078 | pci_release_regions(pdev); |
| 2079 | err_dma: |
| 2080 | pci_disable_device(pdev); |
| 2081 | vfree(nic); |
| 2082 | |
| 2083 | RET(err); |
| 2084 | } |
| 2085 | |
| 2086 | /****************** Ethtool interface *********************/ |
| 2087 | /* get strings for tests */ |
| 2088 | static const char |
| 2089 | bdx_test_names[][ETH_GSTRING_LEN] = { |
| 2090 | "No tests defined" |
| 2091 | }; |
| 2092 | |
| 2093 | /* get strings for statistics counters */ |
| 2094 | static const char |
| 2095 | bdx_stat_names[][ETH_GSTRING_LEN] = { |
| 2096 | "InUCast", /* 0x7200 */ |
| 2097 | "InMCast", /* 0x7210 */ |
| 2098 | "InBCast", /* 0x7220 */ |
| 2099 | "InPkts", /* 0x7230 */ |
| 2100 | "InErrors", /* 0x7240 */ |
| 2101 | "InDropped", /* 0x7250 */ |
| 2102 | "FrameTooLong", /* 0x7260 */ |
| 2103 | "FrameSequenceErrors", /* 0x7270 */ |
| 2104 | "InVLAN", /* 0x7280 */ |
| 2105 | "InDroppedDFE", /* 0x7290 */ |
| 2106 | "InDroppedIntFull", /* 0x72A0 */ |
| 2107 | "InFrameAlignErrors", /* 0x72B0 */ |
| 2108 | |
| 2109 | /* 0x72C0-0x72E0 RSRV */ |
| 2110 | |
| 2111 | "OutUCast", /* 0x72F0 */ |
| 2112 | "OutMCast", /* 0x7300 */ |
| 2113 | "OutBCast", /* 0x7310 */ |
| 2114 | "OutPkts", /* 0x7320 */ |
| 2115 | |
| 2116 | /* 0x7330-0x7360 RSRV */ |
| 2117 | |
| 2118 | "OutVLAN", /* 0x7370 */ |
| 2119 | "InUCastOctects", /* 0x7380 */ |
| 2120 | "OutUCastOctects", /* 0x7390 */ |
| 2121 | |
| 2122 | /* 0x73A0-0x73B0 RSRV */ |
| 2123 | |
| 2124 | "InBCastOctects", /* 0x73C0 */ |
| 2125 | "OutBCastOctects", /* 0x73D0 */ |
| 2126 | "InOctects", /* 0x73E0 */ |
| 2127 | "OutOctects", /* 0x73F0 */ |
| 2128 | }; |
| 2129 | |
| 2130 | /* |
| 2131 | * bdx_get_settings - get device-specific settings |
| 2132 | * @netdev |
| 2133 | * @ecmd |
| 2134 | */ |
| 2135 | static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) |
| 2136 | { |
| 2137 | u32 rdintcm; |
| 2138 | u32 tdintcm; |
| 2139 | struct bdx_priv *priv = netdev->priv; |
| 2140 | |
| 2141 | rdintcm = priv->rdintcm; |
| 2142 | tdintcm = priv->tdintcm; |
| 2143 | |
| 2144 | ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); |
| 2145 | ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE); |
| 2146 | ecmd->speed = SPEED_10000; |
| 2147 | ecmd->duplex = DUPLEX_FULL; |
| 2148 | ecmd->port = PORT_FIBRE; |
| 2149 | ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */ |
| 2150 | ecmd->autoneg = AUTONEG_DISABLE; |
| 2151 | |
| 2152 | /* PCK_TH measures in multiples of FIFO bytes |
| 2153 | We translate to packets */ |
| 2154 | ecmd->maxtxpkt = |
| 2155 | ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ); |
| 2156 | ecmd->maxrxpkt = |
| 2157 | ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc)); |
| 2158 | |
| 2159 | return 0; |
| 2160 | } |
| 2161 | |
| 2162 | /* |
| 2163 | * bdx_get_drvinfo - report driver information |
| 2164 | * @netdev |
| 2165 | * @drvinfo |
| 2166 | */ |
| 2167 | static void |
| 2168 | bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) |
| 2169 | { |
| 2170 | struct bdx_priv *priv = netdev->priv; |
| 2171 | |
| 2172 | strncat(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver)); |
| 2173 | strncat(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version)); |
| 2174 | strncat(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); |
| 2175 | strncat(drvinfo->bus_info, pci_name(priv->pdev), |
| 2176 | sizeof(drvinfo->bus_info)); |
| 2177 | |
| 2178 | drvinfo->n_stats = ((priv->stats_flag) ? |
| 2179 | (sizeof(bdx_stat_names) / ETH_GSTRING_LEN) : 0); |
| 2180 | drvinfo->testinfo_len = 0; |
| 2181 | drvinfo->regdump_len = 0; |
| 2182 | drvinfo->eedump_len = 0; |
| 2183 | } |
| 2184 | |
| 2185 | /* |
| 2186 | * bdx_get_rx_csum - report whether receive checksums are turned on or off |
| 2187 | * @netdev |
| 2188 | */ |
| 2189 | static u32 bdx_get_rx_csum(struct net_device *netdev) |
| 2190 | { |
| 2191 | return 1; /* always on */ |
| 2192 | } |
| 2193 | |
| 2194 | /* |
| 2195 | * bdx_get_tx_csum - report whether transmit checksums are turned on or off |
| 2196 | * @netdev |
| 2197 | */ |
| 2198 | static u32 bdx_get_tx_csum(struct net_device *netdev) |
| 2199 | { |
| 2200 | return (netdev->features & NETIF_F_IP_CSUM) != 0; |
| 2201 | } |
| 2202 | |
| 2203 | /* |
| 2204 | * bdx_get_coalesce - get interrupt coalescing parameters |
| 2205 | * @netdev |
| 2206 | * @ecoal |
| 2207 | */ |
| 2208 | static int |
| 2209 | bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal) |
| 2210 | { |
| 2211 | u32 rdintcm; |
| 2212 | u32 tdintcm; |
| 2213 | struct bdx_priv *priv = netdev->priv; |
| 2214 | |
| 2215 | rdintcm = priv->rdintcm; |
| 2216 | tdintcm = priv->tdintcm; |
| 2217 | |
| 2218 | /* PCK_TH measures in multiples of FIFO bytes |
| 2219 | We translate to packets */ |
| 2220 | ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT; |
| 2221 | ecoal->rx_max_coalesced_frames = |
| 2222 | ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc)); |
| 2223 | |
| 2224 | ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT; |
| 2225 | ecoal->tx_max_coalesced_frames = |
| 2226 | ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ); |
| 2227 | |
| 2228 | /* adaptive parameters ignored */ |
| 2229 | return 0; |
| 2230 | } |
| 2231 | |
| 2232 | /* |
| 2233 | * bdx_set_coalesce - set interrupt coalescing parameters |
| 2234 | * @netdev |
| 2235 | * @ecoal |
| 2236 | */ |
| 2237 | static int |
| 2238 | bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal) |
| 2239 | { |
| 2240 | u32 rdintcm; |
| 2241 | u32 tdintcm; |
| 2242 | struct bdx_priv *priv = netdev->priv; |
| 2243 | int rx_coal; |
| 2244 | int tx_coal; |
| 2245 | int rx_max_coal; |
| 2246 | int tx_max_coal; |
| 2247 | |
| 2248 | /* Check for valid input */ |
| 2249 | rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT; |
| 2250 | tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT; |
| 2251 | rx_max_coal = ecoal->rx_max_coalesced_frames; |
| 2252 | tx_max_coal = ecoal->tx_max_coalesced_frames; |
| 2253 | |
| 2254 | /* Translate from packets to multiples of FIFO bytes */ |
| 2255 | rx_max_coal = |
| 2256 | (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1) |
| 2257 | / PCK_TH_MULT); |
| 2258 | tx_max_coal = |
| 2259 | (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1) |
| 2260 | / PCK_TH_MULT); |
| 2261 | |
| 2262 | if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) |
| 2263 | || (rx_max_coal > 0xF) || (tx_max_coal > 0xF)) |
| 2264 | return -EINVAL; |
| 2265 | |
| 2266 | rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm), |
| 2267 | GET_RXF_TH(priv->rdintcm), rx_max_coal); |
| 2268 | tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0, |
| 2269 | tx_max_coal); |
| 2270 | |
| 2271 | priv->rdintcm = rdintcm; |
| 2272 | priv->tdintcm = tdintcm; |
| 2273 | |
| 2274 | WRITE_REG(priv, regRDINTCM0, rdintcm); |
| 2275 | WRITE_REG(priv, regTDINTCM0, tdintcm); |
| 2276 | |
| 2277 | return 0; |
| 2278 | } |
| 2279 | |
| 2280 | /* Convert RX fifo size to number of pending packets */ |
| 2281 | static inline int bdx_rx_fifo_size_to_packets(int rx_size) |
| 2282 | { |
| 2283 | return ((FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc)); |
| 2284 | } |
| 2285 | |
| 2286 | /* Convert TX fifo size to number of pending packets */ |
| 2287 | static inline int bdx_tx_fifo_size_to_packets(int tx_size) |
| 2288 | { |
| 2289 | return ((FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ); |
| 2290 | } |
| 2291 | |
| 2292 | /* |
| 2293 | * bdx_get_ringparam - report ring sizes |
| 2294 | * @netdev |
| 2295 | * @ring |
| 2296 | */ |
| 2297 | static void |
| 2298 | bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) |
| 2299 | { |
| 2300 | struct bdx_priv *priv = netdev->priv; |
| 2301 | |
| 2302 | /*max_pending - the maximum-sized FIFO we allow */ |
| 2303 | ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3); |
| 2304 | ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3); |
| 2305 | ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size); |
| 2306 | ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size); |
| 2307 | } |
| 2308 | |
| 2309 | /* |
| 2310 | * bdx_set_ringparam - set ring sizes |
| 2311 | * @netdev |
| 2312 | * @ring |
| 2313 | */ |
| 2314 | static int |
| 2315 | bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) |
| 2316 | { |
| 2317 | struct bdx_priv *priv = netdev->priv; |
| 2318 | int rx_size = 0; |
| 2319 | int tx_size = 0; |
| 2320 | |
| 2321 | for (; rx_size < 4; rx_size++) { |
| 2322 | if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending) |
| 2323 | break; |
| 2324 | } |
| 2325 | if (rx_size == 4) |
| 2326 | rx_size = 3; |
| 2327 | |
| 2328 | for (; tx_size < 4; tx_size++) { |
| 2329 | if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending) |
| 2330 | break; |
| 2331 | } |
| 2332 | if (tx_size == 4) |
| 2333 | tx_size = 3; |
| 2334 | |
| 2335 | /*Is there anything to do? */ |
| 2336 | if ((rx_size == priv->rxf_size) |
| 2337 | && (tx_size == priv->txd_size)) |
| 2338 | return 0; |
| 2339 | |
| 2340 | priv->rxf_size = rx_size; |
| 2341 | if (rx_size > 1) |
| 2342 | priv->rxd_size = rx_size - 1; |
| 2343 | else |
| 2344 | priv->rxd_size = rx_size; |
| 2345 | |
| 2346 | priv->txf_size = priv->txd_size = tx_size; |
| 2347 | |
| 2348 | if (netif_running(netdev)) { |
| 2349 | bdx_close(netdev); |
| 2350 | bdx_open(netdev); |
| 2351 | } |
| 2352 | return 0; |
| 2353 | } |
| 2354 | |
| 2355 | /* |
| 2356 | * bdx_get_strings - return a set of strings that describe the requested objects |
| 2357 | * @netdev |
| 2358 | * @data |
| 2359 | */ |
| 2360 | static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data) |
| 2361 | { |
| 2362 | switch (stringset) { |
| 2363 | case ETH_SS_TEST: |
| 2364 | memcpy(data, *bdx_test_names, sizeof(bdx_test_names)); |
| 2365 | break; |
| 2366 | case ETH_SS_STATS: |
| 2367 | memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names)); |
| 2368 | break; |
| 2369 | } |
| 2370 | } |
| 2371 | |
| 2372 | /* |
| 2373 | * bdx_get_stats_count - return number of 64bit statistics counters |
| 2374 | * @netdev |
| 2375 | */ |
| 2376 | static int bdx_get_stats_count(struct net_device *netdev) |
| 2377 | { |
| 2378 | struct bdx_priv *priv = netdev->priv; |
| 2379 | BDX_ASSERT(sizeof(bdx_stat_names) / ETH_GSTRING_LEN |
| 2380 | != sizeof(struct bdx_stats) / sizeof(u64)); |
| 2381 | return ((priv->stats_flag) ? (sizeof(bdx_stat_names) / ETH_GSTRING_LEN) |
| 2382 | : 0); |
| 2383 | } |
| 2384 | |
| 2385 | /* |
| 2386 | * bdx_get_ethtool_stats - return device's hardware L2 statistics |
| 2387 | * @netdev |
| 2388 | * @stats |
| 2389 | * @data |
| 2390 | */ |
| 2391 | static void bdx_get_ethtool_stats(struct net_device *netdev, |
| 2392 | struct ethtool_stats *stats, u64 *data) |
| 2393 | { |
| 2394 | struct bdx_priv *priv = netdev->priv; |
| 2395 | |
| 2396 | if (priv->stats_flag) { |
| 2397 | |
| 2398 | /* Update stats from HW */ |
| 2399 | bdx_update_stats(priv); |
| 2400 | |
| 2401 | /* Copy data to user buffer */ |
| 2402 | memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats)); |
| 2403 | } |
| 2404 | } |
| 2405 | |
| 2406 | /* |
| 2407 | * bdx_ethtool_ops - ethtool interface implementation |
| 2408 | * @netdev |
| 2409 | */ |
| 2410 | static void bdx_ethtool_ops(struct net_device *netdev) |
| 2411 | { |
| 2412 | static struct ethtool_ops bdx_ethtool_ops = { |
| 2413 | .get_settings = bdx_get_settings, |
| 2414 | .get_drvinfo = bdx_get_drvinfo, |
| 2415 | .get_link = ethtool_op_get_link, |
| 2416 | .get_coalesce = bdx_get_coalesce, |
| 2417 | .set_coalesce = bdx_set_coalesce, |
| 2418 | .get_ringparam = bdx_get_ringparam, |
| 2419 | .set_ringparam = bdx_set_ringparam, |
| 2420 | .get_rx_csum = bdx_get_rx_csum, |
| 2421 | .get_tx_csum = bdx_get_tx_csum, |
| 2422 | .get_sg = ethtool_op_get_sg, |
| 2423 | .get_tso = ethtool_op_get_tso, |
| 2424 | .get_strings = bdx_get_strings, |
| 2425 | .get_stats_count = bdx_get_stats_count, |
| 2426 | .get_ethtool_stats = bdx_get_ethtool_stats, |
| 2427 | }; |
| 2428 | |
| 2429 | SET_ETHTOOL_OPS(netdev, &bdx_ethtool_ops); |
| 2430 | } |
| 2431 | |
| 2432 | /** |
| 2433 | * bdx_remove - Device Removal Routine |
| 2434 | * @pdev: PCI device information struct |
| 2435 | * |
| 2436 | * bdx_remove is called by the PCI subsystem to alert the driver |
| 2437 | * that it should release a PCI device. The could be caused by a |
| 2438 | * Hot-Plug event, or because the driver is going to be removed from |
| 2439 | * memory. |
| 2440 | **/ |
| 2441 | static void __devexit bdx_remove(struct pci_dev *pdev) |
| 2442 | { |
| 2443 | struct pci_nic *nic = pci_get_drvdata(pdev); |
| 2444 | struct net_device *ndev; |
| 2445 | int port; |
| 2446 | |
| 2447 | for (port = 0; port < nic->port_num; port++) { |
| 2448 | ndev = nic->priv[port]->ndev; |
| 2449 | unregister_netdev(ndev); |
| 2450 | free_netdev(ndev); |
| 2451 | } |
| 2452 | |
| 2453 | /*bdx_hw_reset_direct(nic->regs); */ |
| 2454 | #ifdef BDX_MSI |
| 2455 | if (nic->irq_type == IRQ_MSI) |
| 2456 | pci_disable_msi(pdev); |
| 2457 | #endif |
| 2458 | |
| 2459 | iounmap(nic->regs); |
| 2460 | pci_release_regions(pdev); |
| 2461 | pci_disable_device(pdev); |
| 2462 | pci_set_drvdata(pdev, NULL); |
| 2463 | vfree(nic); |
| 2464 | |
| 2465 | RET(); |
| 2466 | } |
| 2467 | |
| 2468 | static struct pci_driver bdx_pci_driver = { |
| 2469 | .name = BDX_DRV_NAME, |
| 2470 | .id_table = bdx_pci_tbl, |
| 2471 | .probe = bdx_probe, |
| 2472 | .remove = __devexit_p(bdx_remove), |
| 2473 | }; |
| 2474 | |
| 2475 | /* |
| 2476 | * print_driver_id - print parameters of the driver build |
| 2477 | */ |
| 2478 | static void __init print_driver_id(void) |
| 2479 | { |
| 2480 | printk(KERN_INFO "%s: %s, %s\n", BDX_DRV_NAME, BDX_DRV_DESC, |
| 2481 | BDX_DRV_VERSION); |
| 2482 | printk(KERN_INFO "%s: Options: hw_csum %s\n", BDX_DRV_NAME, |
| 2483 | BDX_MSI_STRING); |
| 2484 | } |
| 2485 | |
| 2486 | static int __init bdx_module_init(void) |
| 2487 | { |
| 2488 | ENTER; |
| 2489 | bdx_firmware_endianess(); |
| 2490 | init_txd_sizes(); |
| 2491 | print_driver_id(); |
| 2492 | RET(pci_register_driver(&bdx_pci_driver)); |
| 2493 | } |
| 2494 | |
| 2495 | module_init(bdx_module_init); |
| 2496 | |
| 2497 | static void __exit bdx_module_exit(void) |
| 2498 | { |
| 2499 | ENTER; |
| 2500 | pci_unregister_driver(&bdx_pci_driver); |
| 2501 | RET(); |
| 2502 | } |
| 2503 | |
| 2504 | module_exit(bdx_module_exit); |
| 2505 | |
| 2506 | MODULE_LICENSE("GPL"); |
| 2507 | MODULE_AUTHOR(DRIVER_AUTHOR); |
| 2508 | MODULE_DESCRIPTION(BDX_DRV_DESC); |