Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1 | /* |
| 2 | * USB Gadget driver for LPC32xx |
| 3 | * |
| 4 | * Authors: |
| 5 | * Kevin Wells <kevin.wells@nxp.com> |
| 6 | * Mike James |
| 7 | * Roland Stigge <stigge@antcom.de> |
| 8 | * |
| 9 | * Copyright (C) 2006 Philips Semiconductors |
| 10 | * Copyright (C) 2009 NXP Semiconductors |
| 11 | * Copyright (C) 2012 Roland Stigge |
| 12 | * |
| 13 | * Note: This driver is based on original work done by Mike James for |
| 14 | * the LPC3180. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License as published by |
| 18 | * the Free Software Foundation; either version 2 of the License, or |
| 19 | * (at your option) any later version. |
| 20 | * |
| 21 | * This program is distributed in the hope that it will be useful, |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 24 | * GNU General Public License for more details. |
| 25 | * |
| 26 | * You should have received a copy of the GNU General Public License |
| 27 | * along with this program; if not, write to the Free Software |
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 29 | */ |
| 30 | |
| 31 | #include <linux/kernel.h> |
| 32 | #include <linux/module.h> |
| 33 | #include <linux/platform_device.h> |
| 34 | #include <linux/delay.h> |
| 35 | #include <linux/ioport.h> |
| 36 | #include <linux/slab.h> |
| 37 | #include <linux/errno.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/list.h> |
| 40 | #include <linux/interrupt.h> |
| 41 | #include <linux/proc_fs.h> |
| 42 | #include <linux/clk.h> |
| 43 | #include <linux/usb/ch9.h> |
| 44 | #include <linux/usb/gadget.h> |
| 45 | #include <linux/i2c.h> |
| 46 | #include <linux/kthread.h> |
| 47 | #include <linux/freezer.h> |
| 48 | #include <linux/dma-mapping.h> |
| 49 | #include <linux/dmapool.h> |
| 50 | #include <linux/workqueue.h> |
| 51 | #include <linux/of.h> |
| 52 | #include <linux/usb/isp1301.h> |
| 53 | |
| 54 | #include <asm/byteorder.h> |
| 55 | #include <mach/hardware.h> |
| 56 | #include <linux/io.h> |
| 57 | #include <asm/irq.h> |
| 58 | #include <asm/system.h> |
| 59 | |
| 60 | #include <mach/platform.h> |
| 61 | #include <mach/irqs.h> |
| 62 | #include <mach/board.h> |
| 63 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES |
Alexandre Pereira da Silva | d7dbdb5 | 2012-06-20 09:37:57 -0300 | [diff] [blame] | 64 | #include <linux/debugfs.h> |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 65 | #include <linux/seq_file.h> |
| 66 | #endif |
| 67 | |
| 68 | /* |
| 69 | * USB device configuration structure |
| 70 | */ |
| 71 | typedef void (*usc_chg_event)(int); |
| 72 | struct lpc32xx_usbd_cfg { |
| 73 | int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */ |
| 74 | usc_chg_event conn_chgb; /* Connection change event (optional) */ |
| 75 | usc_chg_event susp_chgb; /* Suspend/resume event (optional) */ |
| 76 | usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */ |
| 77 | }; |
| 78 | |
| 79 | /* |
| 80 | * controller driver data structures |
| 81 | */ |
| 82 | |
| 83 | /* 16 endpoints (not to be confused with 32 hardware endpoints) */ |
| 84 | #define NUM_ENDPOINTS 16 |
| 85 | |
| 86 | /* |
| 87 | * IRQ indices make reading the code a little easier |
| 88 | */ |
| 89 | #define IRQ_USB_LP 0 |
| 90 | #define IRQ_USB_HP 1 |
| 91 | #define IRQ_USB_DEVDMA 2 |
| 92 | #define IRQ_USB_ATX 3 |
| 93 | |
| 94 | #define EP_OUT 0 /* RX (from host) */ |
| 95 | #define EP_IN 1 /* TX (to host) */ |
| 96 | |
| 97 | /* Returns the interrupt mask for the selected hardware endpoint */ |
| 98 | #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir)) |
| 99 | |
| 100 | #define EP_INT_TYPE 0 |
| 101 | #define EP_ISO_TYPE 1 |
| 102 | #define EP_BLK_TYPE 2 |
| 103 | #define EP_CTL_TYPE 3 |
| 104 | |
| 105 | /* EP0 states */ |
| 106 | #define WAIT_FOR_SETUP 0 /* Wait for setup packet */ |
| 107 | #define DATA_IN 1 /* Expect dev->host transfer */ |
| 108 | #define DATA_OUT 2 /* Expect host->dev transfer */ |
| 109 | |
| 110 | /* DD (DMA Descriptor) structure, requires word alignment, this is already |
| 111 | * defined in the LPC32XX USB device header file, but this version is slightly |
| 112 | * modified to tag some work data with each DMA descriptor. */ |
| 113 | struct lpc32xx_usbd_dd_gad { |
| 114 | u32 dd_next_phy; |
| 115 | u32 dd_setup; |
| 116 | u32 dd_buffer_addr; |
| 117 | u32 dd_status; |
| 118 | u32 dd_iso_ps_mem_addr; |
| 119 | u32 this_dma; |
| 120 | u32 iso_status[6]; /* 5 spare */ |
| 121 | u32 dd_next_v; |
| 122 | }; |
| 123 | |
| 124 | /* |
| 125 | * Logical endpoint structure |
| 126 | */ |
| 127 | struct lpc32xx_ep { |
| 128 | struct usb_ep ep; |
| 129 | struct list_head queue; |
| 130 | struct lpc32xx_udc *udc; |
| 131 | |
| 132 | u32 hwep_num_base; /* Physical hardware EP */ |
| 133 | u32 hwep_num; /* Maps to hardware endpoint */ |
| 134 | u32 maxpacket; |
| 135 | u32 lep; |
| 136 | |
| 137 | bool is_in; |
| 138 | bool req_pending; |
| 139 | u32 eptype; |
| 140 | |
| 141 | u32 totalints; |
| 142 | |
| 143 | bool wedge; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 144 | }; |
| 145 | |
| 146 | /* |
| 147 | * Common UDC structure |
| 148 | */ |
| 149 | struct lpc32xx_udc { |
| 150 | struct usb_gadget gadget; |
| 151 | struct usb_gadget_driver *driver; |
| 152 | struct platform_device *pdev; |
| 153 | struct device *dev; |
| 154 | struct dentry *pde; |
| 155 | spinlock_t lock; |
| 156 | struct i2c_client *isp1301_i2c_client; |
| 157 | |
| 158 | /* Board and device specific */ |
| 159 | struct lpc32xx_usbd_cfg *board; |
| 160 | u32 io_p_start; |
| 161 | u32 io_p_size; |
| 162 | void __iomem *udp_baseaddr; |
| 163 | int udp_irq[4]; |
| 164 | struct clk *usb_pll_clk; |
| 165 | struct clk *usb_slv_clk; |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 166 | struct clk *usb_otg_clk; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 167 | |
| 168 | /* DMA support */ |
| 169 | u32 *udca_v_base; |
| 170 | u32 udca_p_base; |
| 171 | struct dma_pool *dd_cache; |
| 172 | |
| 173 | /* Common EP and control data */ |
| 174 | u32 enabled_devints; |
| 175 | u32 enabled_hwepints; |
| 176 | u32 dev_status; |
| 177 | u32 realized_eps; |
| 178 | |
| 179 | /* VBUS detection, pullup, and power flags */ |
| 180 | u8 vbus; |
| 181 | u8 last_vbus; |
| 182 | int pullup; |
| 183 | int poweron; |
| 184 | |
| 185 | /* Work queues related to I2C support */ |
| 186 | struct work_struct pullup_job; |
| 187 | struct work_struct vbus_job; |
| 188 | struct work_struct power_job; |
| 189 | |
| 190 | /* USB device peripheral - various */ |
| 191 | struct lpc32xx_ep ep[NUM_ENDPOINTS]; |
| 192 | bool enabled; |
| 193 | bool clocked; |
| 194 | bool suspended; |
| 195 | bool selfpowered; |
| 196 | int ep0state; |
| 197 | atomic_t enabled_ep_cnt; |
| 198 | wait_queue_head_t ep_disable_wait_queue; |
| 199 | }; |
| 200 | |
| 201 | /* |
| 202 | * Endpoint request |
| 203 | */ |
| 204 | struct lpc32xx_request { |
| 205 | struct usb_request req; |
| 206 | struct list_head queue; |
| 207 | struct lpc32xx_usbd_dd_gad *dd_desc_ptr; |
| 208 | bool mapped; |
| 209 | bool send_zlp; |
| 210 | }; |
| 211 | |
| 212 | static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g) |
| 213 | { |
| 214 | return container_of(g, struct lpc32xx_udc, gadget); |
| 215 | } |
| 216 | |
| 217 | #define ep_dbg(epp, fmt, arg...) \ |
| 218 | dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg) |
| 219 | #define ep_err(epp, fmt, arg...) \ |
| 220 | dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg) |
| 221 | #define ep_info(epp, fmt, arg...) \ |
| 222 | dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg) |
| 223 | #define ep_warn(epp, fmt, arg...) \ |
| 224 | dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg) |
| 225 | |
| 226 | #define UDCA_BUFF_SIZE (128) |
| 227 | |
| 228 | /* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 229 | * be replaced with an inremap()ed pointer |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 230 | * */ |
| 231 | #define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64) |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 232 | |
| 233 | /* USB_CTRL bit defines */ |
| 234 | #define USB_SLAVE_HCLK_EN (1 << 24) |
| 235 | #define USB_HOST_NEED_CLK_EN (1 << 21) |
| 236 | #define USB_DEV_NEED_CLK_EN (1 << 22) |
| 237 | |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 238 | /********************************************************************** |
| 239 | * USB device controller register offsets |
| 240 | **********************************************************************/ |
| 241 | |
| 242 | #define USBD_DEVINTST(x) ((x) + 0x200) |
| 243 | #define USBD_DEVINTEN(x) ((x) + 0x204) |
| 244 | #define USBD_DEVINTCLR(x) ((x) + 0x208) |
| 245 | #define USBD_DEVINTSET(x) ((x) + 0x20C) |
| 246 | #define USBD_CMDCODE(x) ((x) + 0x210) |
| 247 | #define USBD_CMDDATA(x) ((x) + 0x214) |
| 248 | #define USBD_RXDATA(x) ((x) + 0x218) |
| 249 | #define USBD_TXDATA(x) ((x) + 0x21C) |
| 250 | #define USBD_RXPLEN(x) ((x) + 0x220) |
| 251 | #define USBD_TXPLEN(x) ((x) + 0x224) |
| 252 | #define USBD_CTRL(x) ((x) + 0x228) |
| 253 | #define USBD_DEVINTPRI(x) ((x) + 0x22C) |
| 254 | #define USBD_EPINTST(x) ((x) + 0x230) |
| 255 | #define USBD_EPINTEN(x) ((x) + 0x234) |
| 256 | #define USBD_EPINTCLR(x) ((x) + 0x238) |
| 257 | #define USBD_EPINTSET(x) ((x) + 0x23C) |
| 258 | #define USBD_EPINTPRI(x) ((x) + 0x240) |
| 259 | #define USBD_REEP(x) ((x) + 0x244) |
| 260 | #define USBD_EPIND(x) ((x) + 0x248) |
| 261 | #define USBD_EPMAXPSIZE(x) ((x) + 0x24C) |
| 262 | /* DMA support registers only below */ |
| 263 | /* Set, clear, or get enabled state of the DMA request status. If |
| 264 | * enabled, an IN or OUT token will start a DMA transfer for the EP */ |
| 265 | #define USBD_DMARST(x) ((x) + 0x250) |
| 266 | #define USBD_DMARCLR(x) ((x) + 0x254) |
| 267 | #define USBD_DMARSET(x) ((x) + 0x258) |
| 268 | /* DMA UDCA head pointer */ |
| 269 | #define USBD_UDCAH(x) ((x) + 0x280) |
| 270 | /* EP DMA status, enable, and disable. This is used to specifically |
| 271 | * enabled or disable DMA for a specific EP */ |
| 272 | #define USBD_EPDMAST(x) ((x) + 0x284) |
| 273 | #define USBD_EPDMAEN(x) ((x) + 0x288) |
| 274 | #define USBD_EPDMADIS(x) ((x) + 0x28C) |
| 275 | /* DMA master interrupts enable and pending interrupts */ |
| 276 | #define USBD_DMAINTST(x) ((x) + 0x290) |
| 277 | #define USBD_DMAINTEN(x) ((x) + 0x294) |
| 278 | /* DMA end of transfer interrupt enable, disable, status */ |
| 279 | #define USBD_EOTINTST(x) ((x) + 0x2A0) |
| 280 | #define USBD_EOTINTCLR(x) ((x) + 0x2A4) |
| 281 | #define USBD_EOTINTSET(x) ((x) + 0x2A8) |
| 282 | /* New DD request interrupt enable, disable, status */ |
| 283 | #define USBD_NDDRTINTST(x) ((x) + 0x2AC) |
| 284 | #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0) |
| 285 | #define USBD_NDDRTINTSET(x) ((x) + 0x2B4) |
| 286 | /* DMA error interrupt enable, disable, status */ |
| 287 | #define USBD_SYSERRTINTST(x) ((x) + 0x2B8) |
| 288 | #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC) |
| 289 | #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0) |
| 290 | |
| 291 | /********************************************************************** |
| 292 | * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/ |
| 293 | * USBD_DEVINTPRI register definitions |
| 294 | **********************************************************************/ |
| 295 | #define USBD_ERR_INT (1 << 9) |
| 296 | #define USBD_EP_RLZED (1 << 8) |
| 297 | #define USBD_TXENDPKT (1 << 7) |
| 298 | #define USBD_RXENDPKT (1 << 6) |
| 299 | #define USBD_CDFULL (1 << 5) |
| 300 | #define USBD_CCEMPTY (1 << 4) |
| 301 | #define USBD_DEV_STAT (1 << 3) |
| 302 | #define USBD_EP_SLOW (1 << 2) |
| 303 | #define USBD_EP_FAST (1 << 1) |
| 304 | #define USBD_FRAME (1 << 0) |
| 305 | |
| 306 | /********************************************************************** |
| 307 | * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/ |
| 308 | * USBD_EPINTPRI register definitions |
| 309 | **********************************************************************/ |
| 310 | /* End point selection macro (RX) */ |
| 311 | #define USBD_RX_EP_SEL(e) (1 << ((e) << 1)) |
| 312 | |
| 313 | /* End point selection macro (TX) */ |
| 314 | #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1)) |
| 315 | |
| 316 | /********************************************************************** |
| 317 | * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/ |
| 318 | * USBD_EPDMAEN/USBD_EPDMADIS/ |
| 319 | * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/ |
| 320 | * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/ |
| 321 | * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET |
| 322 | * register definitions |
| 323 | **********************************************************************/ |
| 324 | /* Endpoint selection macro */ |
| 325 | #define USBD_EP_SEL(e) (1 << (e)) |
| 326 | |
| 327 | /********************************************************************** |
| 328 | * SBD_DMAINTST/USBD_DMAINTEN |
| 329 | **********************************************************************/ |
| 330 | #define USBD_SYS_ERR_INT (1 << 2) |
| 331 | #define USBD_NEW_DD_INT (1 << 1) |
| 332 | #define USBD_EOT_INT (1 << 0) |
| 333 | |
| 334 | /********************************************************************** |
| 335 | * USBD_RXPLEN register definitions |
| 336 | **********************************************************************/ |
| 337 | #define USBD_PKT_RDY (1 << 11) |
| 338 | #define USBD_DV (1 << 10) |
| 339 | #define USBD_PK_LEN_MASK 0x3FF |
| 340 | |
| 341 | /********************************************************************** |
| 342 | * USBD_CTRL register definitions |
| 343 | **********************************************************************/ |
| 344 | #define USBD_LOG_ENDPOINT(e) ((e) << 2) |
| 345 | #define USBD_WR_EN (1 << 1) |
| 346 | #define USBD_RD_EN (1 << 0) |
| 347 | |
| 348 | /********************************************************************** |
| 349 | * USBD_CMDCODE register definitions |
| 350 | **********************************************************************/ |
| 351 | #define USBD_CMD_CODE(c) ((c) << 16) |
| 352 | #define USBD_CMD_PHASE(p) ((p) << 8) |
| 353 | |
| 354 | /********************************************************************** |
| 355 | * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions |
| 356 | **********************************************************************/ |
| 357 | #define USBD_DMAEP(e) (1 << (e)) |
| 358 | |
| 359 | /* DD (DMA Descriptor) structure, requires word alignment */ |
| 360 | struct lpc32xx_usbd_dd { |
| 361 | u32 *dd_next; |
| 362 | u32 dd_setup; |
| 363 | u32 dd_buffer_addr; |
| 364 | u32 dd_status; |
| 365 | u32 dd_iso_ps_mem_addr; |
| 366 | }; |
| 367 | |
| 368 | /* dd_setup bit defines */ |
| 369 | #define DD_SETUP_ATLE_DMA_MODE 0x01 |
| 370 | #define DD_SETUP_NEXT_DD_VALID 0x04 |
| 371 | #define DD_SETUP_ISO_EP 0x10 |
| 372 | #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5) |
| 373 | #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16) |
| 374 | |
| 375 | /* dd_status bit defines */ |
| 376 | #define DD_STATUS_DD_RETIRED 0x01 |
| 377 | #define DD_STATUS_STS_MASK 0x1E |
| 378 | #define DD_STATUS_STS_NS 0x00 /* Not serviced */ |
| 379 | #define DD_STATUS_STS_BS 0x02 /* Being serviced */ |
| 380 | #define DD_STATUS_STS_NC 0x04 /* Normal completion */ |
| 381 | #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */ |
| 382 | #define DD_STATUS_STS_DOR 0x08 /* Data overrun */ |
| 383 | #define DD_STATUS_STS_SE 0x12 /* System error */ |
| 384 | #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */ |
| 385 | #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */ |
| 386 | #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */ |
| 387 | #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F) |
| 388 | #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF) |
| 389 | |
| 390 | /* |
| 391 | * |
| 392 | * Protocol engine bits below |
| 393 | * |
| 394 | */ |
| 395 | /* Device Interrupt Bit Definitions */ |
| 396 | #define FRAME_INT 0x00000001 |
| 397 | #define EP_FAST_INT 0x00000002 |
| 398 | #define EP_SLOW_INT 0x00000004 |
| 399 | #define DEV_STAT_INT 0x00000008 |
| 400 | #define CCEMTY_INT 0x00000010 |
| 401 | #define CDFULL_INT 0x00000020 |
| 402 | #define RxENDPKT_INT 0x00000040 |
| 403 | #define TxENDPKT_INT 0x00000080 |
| 404 | #define EP_RLZED_INT 0x00000100 |
| 405 | #define ERR_INT 0x00000200 |
| 406 | |
| 407 | /* Rx & Tx Packet Length Definitions */ |
| 408 | #define PKT_LNGTH_MASK 0x000003FF |
| 409 | #define PKT_DV 0x00000400 |
| 410 | #define PKT_RDY 0x00000800 |
| 411 | |
| 412 | /* USB Control Definitions */ |
| 413 | #define CTRL_RD_EN 0x00000001 |
| 414 | #define CTRL_WR_EN 0x00000002 |
| 415 | |
| 416 | /* Command Codes */ |
| 417 | #define CMD_SET_ADDR 0x00D00500 |
| 418 | #define CMD_CFG_DEV 0x00D80500 |
| 419 | #define CMD_SET_MODE 0x00F30500 |
| 420 | #define CMD_RD_FRAME 0x00F50500 |
| 421 | #define DAT_RD_FRAME 0x00F50200 |
| 422 | #define CMD_RD_TEST 0x00FD0500 |
| 423 | #define DAT_RD_TEST 0x00FD0200 |
| 424 | #define CMD_SET_DEV_STAT 0x00FE0500 |
| 425 | #define CMD_GET_DEV_STAT 0x00FE0500 |
| 426 | #define DAT_GET_DEV_STAT 0x00FE0200 |
| 427 | #define CMD_GET_ERR_CODE 0x00FF0500 |
| 428 | #define DAT_GET_ERR_CODE 0x00FF0200 |
| 429 | #define CMD_RD_ERR_STAT 0x00FB0500 |
| 430 | #define DAT_RD_ERR_STAT 0x00FB0200 |
| 431 | #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) |
| 432 | #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) |
| 433 | #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) |
| 434 | #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) |
| 435 | #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) |
| 436 | #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) |
| 437 | #define CMD_CLR_BUF 0x00F20500 |
| 438 | #define DAT_CLR_BUF 0x00F20200 |
| 439 | #define CMD_VALID_BUF 0x00FA0500 |
| 440 | |
| 441 | /* Device Address Register Definitions */ |
| 442 | #define DEV_ADDR_MASK 0x7F |
| 443 | #define DEV_EN 0x80 |
| 444 | |
| 445 | /* Device Configure Register Definitions */ |
| 446 | #define CONF_DVICE 0x01 |
| 447 | |
| 448 | /* Device Mode Register Definitions */ |
| 449 | #define AP_CLK 0x01 |
| 450 | #define INAK_CI 0x02 |
| 451 | #define INAK_CO 0x04 |
| 452 | #define INAK_II 0x08 |
| 453 | #define INAK_IO 0x10 |
| 454 | #define INAK_BI 0x20 |
| 455 | #define INAK_BO 0x40 |
| 456 | |
| 457 | /* Device Status Register Definitions */ |
| 458 | #define DEV_CON 0x01 |
| 459 | #define DEV_CON_CH 0x02 |
| 460 | #define DEV_SUS 0x04 |
| 461 | #define DEV_SUS_CH 0x08 |
| 462 | #define DEV_RST 0x10 |
| 463 | |
| 464 | /* Error Code Register Definitions */ |
| 465 | #define ERR_EC_MASK 0x0F |
| 466 | #define ERR_EA 0x10 |
| 467 | |
| 468 | /* Error Status Register Definitions */ |
| 469 | #define ERR_PID 0x01 |
| 470 | #define ERR_UEPKT 0x02 |
| 471 | #define ERR_DCRC 0x04 |
| 472 | #define ERR_TIMOUT 0x08 |
| 473 | #define ERR_EOP 0x10 |
| 474 | #define ERR_B_OVRN 0x20 |
| 475 | #define ERR_BTSTF 0x40 |
| 476 | #define ERR_TGL 0x80 |
| 477 | |
| 478 | /* Endpoint Select Register Definitions */ |
| 479 | #define EP_SEL_F 0x01 |
| 480 | #define EP_SEL_ST 0x02 |
| 481 | #define EP_SEL_STP 0x04 |
| 482 | #define EP_SEL_PO 0x08 |
| 483 | #define EP_SEL_EPN 0x10 |
| 484 | #define EP_SEL_B_1_FULL 0x20 |
| 485 | #define EP_SEL_B_2_FULL 0x40 |
| 486 | |
| 487 | /* Endpoint Status Register Definitions */ |
| 488 | #define EP_STAT_ST 0x01 |
| 489 | #define EP_STAT_DA 0x20 |
| 490 | #define EP_STAT_RF_MO 0x40 |
| 491 | #define EP_STAT_CND_ST 0x80 |
| 492 | |
| 493 | /* Clear Buffer Register Definitions */ |
| 494 | #define CLR_BUF_PO 0x01 |
| 495 | |
| 496 | /* DMA Interrupt Bit Definitions */ |
| 497 | #define EOT_INT 0x01 |
| 498 | #define NDD_REQ_INT 0x02 |
| 499 | #define SYS_ERR_INT 0x04 |
| 500 | |
| 501 | #define DRIVER_VERSION "1.03" |
| 502 | static const char driver_name[] = "lpc32xx_udc"; |
| 503 | |
| 504 | /* |
| 505 | * |
| 506 | * proc interface support |
| 507 | * |
| 508 | */ |
| 509 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES |
| 510 | static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"}; |
| 511 | static const char debug_filename[] = "driver/udc"; |
| 512 | |
| 513 | static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep) |
| 514 | { |
| 515 | struct lpc32xx_request *req; |
| 516 | |
| 517 | seq_printf(s, "\n"); |
| 518 | seq_printf(s, "%12s, maxpacket %4d %3s", |
| 519 | ep->ep.name, ep->ep.maxpacket, |
| 520 | ep->is_in ? "in" : "out"); |
| 521 | seq_printf(s, " type %4s", epnames[ep->eptype]); |
| 522 | seq_printf(s, " ints: %12d", ep->totalints); |
| 523 | |
| 524 | if (list_empty(&ep->queue)) |
| 525 | seq_printf(s, "\t(queue empty)\n"); |
| 526 | else { |
| 527 | list_for_each_entry(req, &ep->queue, queue) { |
| 528 | u32 length = req->req.actual; |
| 529 | |
| 530 | seq_printf(s, "\treq %p len %d/%d buf %p\n", |
| 531 | &req->req, length, |
| 532 | req->req.length, req->req.buf); |
| 533 | } |
| 534 | } |
| 535 | } |
| 536 | |
| 537 | static int proc_udc_show(struct seq_file *s, void *unused) |
| 538 | { |
| 539 | struct lpc32xx_udc *udc = s->private; |
| 540 | struct lpc32xx_ep *ep; |
| 541 | unsigned long flags; |
| 542 | |
| 543 | seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION); |
| 544 | |
| 545 | spin_lock_irqsave(&udc->lock, flags); |
| 546 | |
| 547 | seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n", |
| 548 | udc->vbus ? "present" : "off", |
| 549 | udc->enabled ? (udc->vbus ? "active" : "enabled") : |
| 550 | "disabled", |
| 551 | udc->selfpowered ? "self" : "VBUS", |
| 552 | udc->suspended ? ", suspended" : "", |
| 553 | udc->driver ? udc->driver->driver.name : "(none)"); |
| 554 | |
| 555 | if (udc->enabled && udc->vbus) { |
| 556 | proc_ep_show(s, &udc->ep[0]); |
Roland Stigge | 78ca913 | 2012-08-20 10:30:13 +0200 | [diff] [blame] | 557 | list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) |
| 558 | proc_ep_show(s, ep); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | spin_unlock_irqrestore(&udc->lock, flags); |
| 562 | |
| 563 | return 0; |
| 564 | } |
| 565 | |
| 566 | static int proc_udc_open(struct inode *inode, struct file *file) |
| 567 | { |
Al Viro | d9dda78 | 2013-03-31 18:16:14 -0400 | [diff] [blame] | 568 | return single_open(file, proc_udc_show, PDE_DATA(inode)); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 569 | } |
| 570 | |
| 571 | static const struct file_operations proc_ops = { |
| 572 | .owner = THIS_MODULE, |
| 573 | .open = proc_udc_open, |
| 574 | .read = seq_read, |
| 575 | .llseek = seq_lseek, |
| 576 | .release = single_release, |
| 577 | }; |
| 578 | |
| 579 | static void create_debug_file(struct lpc32xx_udc *udc) |
| 580 | { |
| 581 | udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops); |
| 582 | } |
| 583 | |
| 584 | static void remove_debug_file(struct lpc32xx_udc *udc) |
| 585 | { |
| 586 | if (udc->pde) |
| 587 | debugfs_remove(udc->pde); |
| 588 | } |
| 589 | |
| 590 | #else |
| 591 | static inline void create_debug_file(struct lpc32xx_udc *udc) {} |
| 592 | static inline void remove_debug_file(struct lpc32xx_udc *udc) {} |
| 593 | #endif |
| 594 | |
| 595 | /* Primary initialization sequence for the ISP1301 transceiver */ |
| 596 | static void isp1301_udc_configure(struct lpc32xx_udc *udc) |
| 597 | { |
| 598 | /* LPC32XX only supports DAT_SE0 USB mode */ |
| 599 | /* This sequence is important */ |
| 600 | |
| 601 | /* Disable transparent UART mode first */ |
| 602 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 603 | (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), |
| 604 | MC1_UART_EN); |
| 605 | |
| 606 | /* Set full speed and SE0 mode */ |
| 607 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 608 | (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); |
| 609 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 610 | ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0)); |
| 611 | |
| 612 | /* |
| 613 | * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide |
| 614 | */ |
| 615 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 616 | (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); |
| 617 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 618 | ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL)); |
| 619 | |
| 620 | /* Driver VBUS_DRV high or low depending on board setup */ |
| 621 | if (udc->board->vbus_drv_pol != 0) |
| 622 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 623 | ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV); |
| 624 | else |
| 625 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 626 | ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, |
| 627 | OTG1_VBUS_DRV); |
| 628 | |
| 629 | /* Bi-directional mode with suspend control |
| 630 | * Enable both pulldowns for now - the pullup will be enable when VBUS |
| 631 | * is detected */ |
| 632 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 633 | (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); |
| 634 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 635 | ISP1301_I2C_OTG_CONTROL_1, |
| 636 | (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN)); |
| 637 | |
| 638 | /* Discharge VBUS (just in case) */ |
| 639 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 640 | ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); |
| 641 | msleep(1); |
| 642 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 643 | (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), |
| 644 | OTG1_VBUS_DISCHRG); |
| 645 | |
| 646 | /* Clear and enable VBUS high edge interrupt */ |
| 647 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 648 | ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0); |
| 649 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 650 | ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); |
| 651 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 652 | ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD); |
| 653 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 654 | ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); |
| 655 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 656 | ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD); |
| 657 | |
| 658 | /* Enable usb_need_clk clock after transceiver is initialized */ |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 659 | writel((readl(USB_CTRL) | USB_DEV_NEED_CLK_EN), USB_CTRL); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 660 | |
| 661 | dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", |
| 662 | i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00)); |
| 663 | dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", |
| 664 | i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02)); |
| 665 | dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n", |
| 666 | i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14)); |
| 667 | } |
| 668 | |
| 669 | /* Enables or disables the USB device pullup via the ISP1301 transceiver */ |
| 670 | static void isp1301_pullup_set(struct lpc32xx_udc *udc) |
| 671 | { |
| 672 | if (udc->pullup) |
| 673 | /* Enable pullup for bus signalling */ |
| 674 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 675 | ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP); |
| 676 | else |
| 677 | /* Enable pullup for bus signalling */ |
| 678 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 679 | ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, |
| 680 | OTG1_DP_PULLUP); |
| 681 | } |
| 682 | |
| 683 | static void pullup_work(struct work_struct *work) |
| 684 | { |
| 685 | struct lpc32xx_udc *udc = |
| 686 | container_of(work, struct lpc32xx_udc, pullup_job); |
| 687 | |
| 688 | isp1301_pullup_set(udc); |
| 689 | } |
| 690 | |
| 691 | static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup, |
| 692 | int block) |
| 693 | { |
| 694 | if (en_pullup == udc->pullup) |
| 695 | return; |
| 696 | |
| 697 | udc->pullup = en_pullup; |
| 698 | if (block) |
| 699 | isp1301_pullup_set(udc); |
| 700 | else |
| 701 | /* defer slow i2c pull up setting */ |
| 702 | schedule_work(&udc->pullup_job); |
| 703 | } |
| 704 | |
| 705 | #ifdef CONFIG_PM |
| 706 | /* Powers up or down the ISP1301 transceiver */ |
| 707 | static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable) |
| 708 | { |
| 709 | if (enable != 0) |
| 710 | /* Power up ISP1301 - this ISP1301 will automatically wakeup |
| 711 | when VBUS is detected */ |
| 712 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 713 | ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR, |
| 714 | MC2_GLOBAL_PWR_DN); |
| 715 | else |
| 716 | /* Power down ISP1301 */ |
| 717 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 718 | ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); |
| 719 | } |
| 720 | |
| 721 | static void power_work(struct work_struct *work) |
| 722 | { |
| 723 | struct lpc32xx_udc *udc = |
| 724 | container_of(work, struct lpc32xx_udc, power_job); |
| 725 | |
| 726 | isp1301_set_powerstate(udc, udc->poweron); |
| 727 | } |
| 728 | #endif |
| 729 | |
| 730 | /* |
| 731 | * |
| 732 | * USB protocol engine command/data read/write helper functions |
| 733 | * |
| 734 | */ |
| 735 | /* Issues a single command to the USB device state machine */ |
| 736 | static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd) |
| 737 | { |
| 738 | u32 pass = 0; |
| 739 | int to; |
| 740 | |
| 741 | /* EP may lock on CLRI if this read isn't done */ |
| 742 | u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); |
| 743 | (void) tmp; |
| 744 | |
| 745 | while (pass == 0) { |
| 746 | writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr)); |
| 747 | |
| 748 | /* Write command code */ |
| 749 | writel(cmd, USBD_CMDCODE(udc->udp_baseaddr)); |
| 750 | to = 10000; |
| 751 | while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) & |
| 752 | USBD_CCEMPTY) == 0) && (to > 0)) { |
| 753 | to--; |
| 754 | } |
| 755 | |
| 756 | if (to > 0) |
| 757 | pass = 1; |
| 758 | |
| 759 | cpu_relax(); |
| 760 | } |
| 761 | } |
| 762 | |
| 763 | /* Issues 2 commands (or command and data) to the USB device state machine */ |
| 764 | static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd, |
| 765 | u32 data) |
| 766 | { |
| 767 | udc_protocol_cmd_w(udc, cmd); |
| 768 | udc_protocol_cmd_w(udc, data); |
| 769 | } |
| 770 | |
| 771 | /* Issues a single command to the USB device state machine and reads |
| 772 | * response data */ |
| 773 | static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd) |
| 774 | { |
| 775 | u32 tmp; |
| 776 | int to = 1000; |
| 777 | |
| 778 | /* Write a command and read data from the protocol engine */ |
| 779 | writel((USBD_CDFULL | USBD_CCEMPTY), |
| 780 | USBD_DEVINTCLR(udc->udp_baseaddr)); |
| 781 | |
| 782 | /* Write command code */ |
| 783 | udc_protocol_cmd_w(udc, cmd); |
| 784 | |
| 785 | tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); |
| 786 | while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL)) |
| 787 | && (to > 0)) |
| 788 | to--; |
| 789 | if (!to) |
| 790 | dev_dbg(udc->dev, |
| 791 | "Protocol engine didn't receive response (CDFULL)\n"); |
| 792 | |
| 793 | return readl(USBD_CMDDATA(udc->udp_baseaddr)); |
| 794 | } |
| 795 | |
| 796 | /* |
| 797 | * |
| 798 | * USB device interrupt mask support functions |
| 799 | * |
| 800 | */ |
| 801 | /* Enable one or more USB device interrupts */ |
| 802 | static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask) |
| 803 | { |
| 804 | udc->enabled_devints |= devmask; |
| 805 | writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); |
| 806 | } |
| 807 | |
| 808 | /* Disable one or more USB device interrupts */ |
| 809 | static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask) |
| 810 | { |
| 811 | udc->enabled_devints &= ~mask; |
| 812 | writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); |
| 813 | } |
| 814 | |
| 815 | /* Clear one or more USB device interrupts */ |
| 816 | static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask) |
| 817 | { |
| 818 | writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr)); |
| 819 | } |
| 820 | |
| 821 | /* |
| 822 | * |
| 823 | * Endpoint interrupt disable/enable functions |
| 824 | * |
| 825 | */ |
| 826 | /* Enable one or more USB endpoint interrupts */ |
| 827 | static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep) |
| 828 | { |
| 829 | udc->enabled_hwepints |= (1 << hwep); |
| 830 | writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); |
| 831 | } |
| 832 | |
| 833 | /* Disable one or more USB endpoint interrupts */ |
| 834 | static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep) |
| 835 | { |
| 836 | udc->enabled_hwepints &= ~(1 << hwep); |
| 837 | writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); |
| 838 | } |
| 839 | |
| 840 | /* Clear one or more USB endpoint interrupts */ |
| 841 | static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep) |
| 842 | { |
| 843 | writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr)); |
| 844 | } |
| 845 | |
| 846 | /* Enable DMA for the HW channel */ |
| 847 | static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep) |
| 848 | { |
| 849 | writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr)); |
| 850 | } |
| 851 | |
| 852 | /* Disable DMA for the HW channel */ |
| 853 | static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep) |
| 854 | { |
| 855 | writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr)); |
| 856 | } |
| 857 | |
| 858 | /* |
| 859 | * |
| 860 | * Endpoint realize/unrealize functions |
| 861 | * |
| 862 | */ |
| 863 | /* Before an endpoint can be used, it needs to be realized |
| 864 | * in the USB protocol engine - this realizes the endpoint. |
| 865 | * The interrupt (FIFO or DMA) is not enabled with this function */ |
| 866 | static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep, |
| 867 | u32 maxpacket) |
| 868 | { |
| 869 | int to = 1000; |
| 870 | |
| 871 | writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); |
| 872 | writel(hwep, USBD_EPIND(udc->udp_baseaddr)); |
| 873 | udc->realized_eps |= (1 << hwep); |
| 874 | writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); |
| 875 | writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr)); |
| 876 | |
| 877 | /* Wait until endpoint is realized in hardware */ |
| 878 | while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & |
| 879 | USBD_EP_RLZED)) && (to > 0)) |
| 880 | to--; |
| 881 | if (!to) |
| 882 | dev_dbg(udc->dev, "EP not correctly realized in hardware\n"); |
| 883 | |
| 884 | writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); |
| 885 | } |
| 886 | |
| 887 | /* Unrealize an EP */ |
| 888 | static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep) |
| 889 | { |
| 890 | udc->realized_eps &= ~(1 << hwep); |
| 891 | writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); |
| 892 | } |
| 893 | |
| 894 | /* |
| 895 | * |
| 896 | * Endpoint support functions |
| 897 | * |
| 898 | */ |
| 899 | /* Select and clear endpoint interrupt */ |
| 900 | static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep) |
| 901 | { |
| 902 | udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep)); |
| 903 | return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep)); |
| 904 | } |
| 905 | |
| 906 | /* Disables the endpoint in the USB protocol engine */ |
| 907 | static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep) |
| 908 | { |
| 909 | udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), |
| 910 | DAT_WR_BYTE(EP_STAT_DA)); |
| 911 | } |
| 912 | |
| 913 | /* Stalls the endpoint - endpoint will return STALL */ |
| 914 | static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep) |
| 915 | { |
| 916 | udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), |
| 917 | DAT_WR_BYTE(EP_STAT_ST)); |
| 918 | } |
| 919 | |
| 920 | /* Clear stall or reset endpoint */ |
| 921 | static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep) |
| 922 | { |
| 923 | udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), |
| 924 | DAT_WR_BYTE(0)); |
| 925 | } |
| 926 | |
| 927 | /* Select an endpoint for endpoint status, clear, validate */ |
| 928 | static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep) |
| 929 | { |
| 930 | udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep)); |
| 931 | } |
| 932 | |
| 933 | /* |
| 934 | * |
| 935 | * Endpoint buffer management functions |
| 936 | * |
| 937 | */ |
| 938 | /* Clear the current endpoint's buffer */ |
| 939 | static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) |
| 940 | { |
| 941 | udc_select_hwep(udc, hwep); |
| 942 | udc_protocol_cmd_w(udc, CMD_CLR_BUF); |
| 943 | } |
| 944 | |
| 945 | /* Validate the current endpoint's buffer */ |
| 946 | static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) |
| 947 | { |
| 948 | udc_select_hwep(udc, hwep); |
| 949 | udc_protocol_cmd_w(udc, CMD_VALID_BUF); |
| 950 | } |
| 951 | |
| 952 | static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep) |
| 953 | { |
| 954 | /* Clear EP interrupt */ |
| 955 | uda_clear_hwepint(udc, hwep); |
| 956 | return udc_selep_clrint(udc, hwep); |
| 957 | } |
| 958 | |
| 959 | /* |
| 960 | * |
| 961 | * USB EP DMA support |
| 962 | * |
| 963 | */ |
| 964 | /* Allocate a DMA Descriptor */ |
| 965 | static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc) |
| 966 | { |
| 967 | dma_addr_t dma; |
| 968 | struct lpc32xx_usbd_dd_gad *dd; |
| 969 | |
| 970 | dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc( |
| 971 | udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma); |
| 972 | if (dd) |
| 973 | dd->this_dma = dma; |
| 974 | |
| 975 | return dd; |
| 976 | } |
| 977 | |
| 978 | /* Free a DMA Descriptor */ |
| 979 | static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd) |
| 980 | { |
| 981 | dma_pool_free(udc->dd_cache, dd, dd->this_dma); |
| 982 | } |
| 983 | |
| 984 | /* |
| 985 | * |
| 986 | * USB setup and shutdown functions |
| 987 | * |
| 988 | */ |
| 989 | /* Enables or disables most of the USB system clocks when low power mode is |
| 990 | * needed. Clocks are typically started on a connection event, and disabled |
| 991 | * when a cable is disconnected */ |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 992 | static void udc_clk_set(struct lpc32xx_udc *udc, int enable) |
| 993 | { |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 994 | if (enable != 0) { |
| 995 | if (udc->clocked) |
| 996 | return; |
| 997 | |
| 998 | udc->clocked = 1; |
| 999 | |
| 1000 | /* 48MHz PLL up */ |
| 1001 | clk_enable(udc->usb_pll_clk); |
| 1002 | |
| 1003 | /* Enable the USB device clock */ |
| 1004 | writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, |
| 1005 | USB_CTRL); |
| 1006 | |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 1007 | clk_enable(udc->usb_otg_clk); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1008 | } else { |
| 1009 | if (!udc->clocked) |
| 1010 | return; |
| 1011 | |
| 1012 | udc->clocked = 0; |
| 1013 | |
| 1014 | /* Never disable the USB_HCLK during normal operation */ |
| 1015 | |
| 1016 | /* 48MHz PLL dpwn */ |
| 1017 | clk_disable(udc->usb_pll_clk); |
| 1018 | |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 1019 | /* Disable the USB device clock */ |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1020 | writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN, |
| 1021 | USB_CTRL); |
| 1022 | |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 1023 | clk_disable(udc->usb_otg_clk); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1024 | } |
| 1025 | } |
| 1026 | |
| 1027 | /* Set/reset USB device address */ |
| 1028 | static void udc_set_address(struct lpc32xx_udc *udc, u32 addr) |
| 1029 | { |
| 1030 | /* Address will be latched at the end of the status phase, or |
| 1031 | latched immediately if function is called twice */ |
| 1032 | udc_protocol_cmd_data_w(udc, CMD_SET_ADDR, |
| 1033 | DAT_WR_BYTE(DEV_EN | addr)); |
| 1034 | } |
| 1035 | |
| 1036 | /* Setup up a IN request for DMA transfer - this consists of determining the |
| 1037 | * list of DMA addresses for the transfer, allocating DMA Descriptors, |
| 1038 | * installing the DD into the UDCA, and then enabling the DMA for that EP */ |
| 1039 | static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) |
| 1040 | { |
| 1041 | struct lpc32xx_request *req; |
| 1042 | u32 hwep = ep->hwep_num; |
| 1043 | |
| 1044 | ep->req_pending = 1; |
| 1045 | |
| 1046 | /* There will always be a request waiting here */ |
| 1047 | req = list_entry(ep->queue.next, struct lpc32xx_request, queue); |
| 1048 | |
| 1049 | /* Place the DD Descriptor into the UDCA */ |
| 1050 | udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; |
| 1051 | |
| 1052 | /* Enable DMA and interrupt for the HW EP */ |
| 1053 | udc_ep_dma_enable(udc, hwep); |
| 1054 | |
| 1055 | /* Clear ZLP if last packet is not of MAXP size */ |
| 1056 | if (req->req.length % ep->ep.maxpacket) |
| 1057 | req->send_zlp = 0; |
| 1058 | |
| 1059 | return 0; |
| 1060 | } |
| 1061 | |
| 1062 | /* Setup up a OUT request for DMA transfer - this consists of determining the |
| 1063 | * list of DMA addresses for the transfer, allocating DMA Descriptors, |
| 1064 | * installing the DD into the UDCA, and then enabling the DMA for that EP */ |
| 1065 | static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) |
| 1066 | { |
| 1067 | struct lpc32xx_request *req; |
| 1068 | u32 hwep = ep->hwep_num; |
| 1069 | |
| 1070 | ep->req_pending = 1; |
| 1071 | |
| 1072 | /* There will always be a request waiting here */ |
| 1073 | req = list_entry(ep->queue.next, struct lpc32xx_request, queue); |
| 1074 | |
| 1075 | /* Place the DD Descriptor into the UDCA */ |
| 1076 | udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; |
| 1077 | |
| 1078 | /* Enable DMA and interrupt for the HW EP */ |
| 1079 | udc_ep_dma_enable(udc, hwep); |
| 1080 | return 0; |
| 1081 | } |
| 1082 | |
| 1083 | static void udc_disable(struct lpc32xx_udc *udc) |
| 1084 | { |
| 1085 | u32 i; |
| 1086 | |
| 1087 | /* Disable device */ |
| 1088 | udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); |
| 1089 | udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0)); |
| 1090 | |
| 1091 | /* Disable all device interrupts (including EP0) */ |
| 1092 | uda_disable_devint(udc, 0x3FF); |
| 1093 | |
| 1094 | /* Disable and reset all endpoint interrupts */ |
| 1095 | for (i = 0; i < 32; i++) { |
| 1096 | uda_disable_hwepint(udc, i); |
| 1097 | uda_clear_hwepint(udc, i); |
| 1098 | udc_disable_hwep(udc, i); |
| 1099 | udc_unrealize_hwep(udc, i); |
| 1100 | udc->udca_v_base[i] = 0; |
| 1101 | |
| 1102 | /* Disable and clear all interrupts and DMA */ |
| 1103 | udc_ep_dma_disable(udc, i); |
| 1104 | writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr)); |
| 1105 | writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr)); |
| 1106 | writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr)); |
| 1107 | writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr)); |
| 1108 | } |
| 1109 | |
| 1110 | /* Disable DMA interrupts */ |
| 1111 | writel(0, USBD_DMAINTEN(udc->udp_baseaddr)); |
| 1112 | |
| 1113 | writel(0, USBD_UDCAH(udc->udp_baseaddr)); |
| 1114 | } |
| 1115 | |
| 1116 | static void udc_enable(struct lpc32xx_udc *udc) |
| 1117 | { |
| 1118 | u32 i; |
| 1119 | struct lpc32xx_ep *ep = &udc->ep[0]; |
| 1120 | |
| 1121 | /* Start with known state */ |
| 1122 | udc_disable(udc); |
| 1123 | |
| 1124 | /* Enable device */ |
| 1125 | udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON)); |
| 1126 | |
| 1127 | /* EP interrupts on high priority, FRAME interrupt on low priority */ |
| 1128 | writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr)); |
| 1129 | writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr)); |
| 1130 | |
| 1131 | /* Clear any pending device interrupts */ |
| 1132 | writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr)); |
| 1133 | |
| 1134 | /* Setup UDCA - not yet used (DMA) */ |
| 1135 | writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr)); |
| 1136 | |
| 1137 | /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */ |
| 1138 | for (i = 0; i <= 1; i++) { |
| 1139 | udc_realize_hwep(udc, i, ep->ep.maxpacket); |
| 1140 | uda_enable_hwepint(udc, i); |
| 1141 | udc_select_hwep(udc, i); |
| 1142 | udc_clrstall_hwep(udc, i); |
| 1143 | udc_clr_buffer_hwep(udc, i); |
| 1144 | } |
| 1145 | |
| 1146 | /* Device interrupt setup */ |
| 1147 | uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | |
| 1148 | USBD_EP_FAST)); |
| 1149 | uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | |
| 1150 | USBD_EP_FAST)); |
| 1151 | |
| 1152 | /* Set device address to 0 - called twice to force a latch in the USB |
| 1153 | engine without the need of a setup packet status closure */ |
| 1154 | udc_set_address(udc, 0); |
| 1155 | udc_set_address(udc, 0); |
| 1156 | |
| 1157 | /* Enable master DMA interrupts */ |
| 1158 | writel((USBD_SYS_ERR_INT | USBD_EOT_INT), |
| 1159 | USBD_DMAINTEN(udc->udp_baseaddr)); |
| 1160 | |
| 1161 | udc->dev_status = 0; |
| 1162 | } |
| 1163 | |
| 1164 | /* |
| 1165 | * |
| 1166 | * USB device board specific events handled via callbacks |
| 1167 | * |
| 1168 | */ |
| 1169 | /* Connection change event - notify board function of change */ |
| 1170 | static void uda_power_event(struct lpc32xx_udc *udc, u32 conn) |
| 1171 | { |
| 1172 | /* Just notify of a connection change event (optional) */ |
| 1173 | if (udc->board->conn_chgb != NULL) |
| 1174 | udc->board->conn_chgb(conn); |
| 1175 | } |
| 1176 | |
| 1177 | /* Suspend/resume event - notify board function of change */ |
| 1178 | static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn) |
| 1179 | { |
| 1180 | /* Just notify of a Suspend/resume change event (optional) */ |
| 1181 | if (udc->board->susp_chgb != NULL) |
| 1182 | udc->board->susp_chgb(conn); |
| 1183 | |
| 1184 | if (conn) |
| 1185 | udc->suspended = 0; |
| 1186 | else |
| 1187 | udc->suspended = 1; |
| 1188 | } |
| 1189 | |
| 1190 | /* Remote wakeup enable/disable - notify board function of change */ |
| 1191 | static void uda_remwkp_cgh(struct lpc32xx_udc *udc) |
| 1192 | { |
| 1193 | if (udc->board->rmwk_chgb != NULL) |
| 1194 | udc->board->rmwk_chgb(udc->dev_status & |
| 1195 | (1 << USB_DEVICE_REMOTE_WAKEUP)); |
| 1196 | } |
| 1197 | |
| 1198 | /* Reads data from FIFO, adjusts for alignment and data size */ |
| 1199 | static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) |
| 1200 | { |
| 1201 | int n, i, bl; |
| 1202 | u16 *p16; |
| 1203 | u32 *p32, tmp, cbytes; |
| 1204 | |
| 1205 | /* Use optimal data transfer method based on source address and size */ |
| 1206 | switch (((u32) data) & 0x3) { |
| 1207 | case 0: /* 32-bit aligned */ |
| 1208 | p32 = (u32 *) data; |
| 1209 | cbytes = (bytes & ~0x3); |
| 1210 | |
| 1211 | /* Copy 32-bit aligned data first */ |
| 1212 | for (n = 0; n < cbytes; n += 4) |
| 1213 | *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr)); |
| 1214 | |
| 1215 | /* Handle any remaining bytes */ |
| 1216 | bl = bytes - cbytes; |
| 1217 | if (bl) { |
| 1218 | tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); |
| 1219 | for (n = 0; n < bl; n++) |
| 1220 | data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); |
| 1221 | |
| 1222 | } |
| 1223 | break; |
| 1224 | |
| 1225 | case 1: /* 8-bit aligned */ |
| 1226 | case 3: |
| 1227 | /* Each byte has to be handled independently */ |
| 1228 | for (n = 0; n < bytes; n += 4) { |
| 1229 | tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); |
| 1230 | |
| 1231 | bl = bytes - n; |
| 1232 | if (bl > 3) |
| 1233 | bl = 3; |
| 1234 | |
| 1235 | for (i = 0; i < bl; i++) |
| 1236 | data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF); |
| 1237 | } |
| 1238 | break; |
| 1239 | |
| 1240 | case 2: /* 16-bit aligned */ |
| 1241 | p16 = (u16 *) data; |
| 1242 | cbytes = (bytes & ~0x3); |
| 1243 | |
| 1244 | /* Copy 32-bit sized objects first with 16-bit alignment */ |
| 1245 | for (n = 0; n < cbytes; n += 4) { |
| 1246 | tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); |
| 1247 | *p16++ = (u16)(tmp & 0xFFFF); |
| 1248 | *p16++ = (u16)((tmp >> 16) & 0xFFFF); |
| 1249 | } |
| 1250 | |
| 1251 | /* Handle any remaining bytes */ |
| 1252 | bl = bytes - cbytes; |
| 1253 | if (bl) { |
| 1254 | tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); |
| 1255 | for (n = 0; n < bl; n++) |
| 1256 | data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); |
| 1257 | } |
| 1258 | break; |
| 1259 | } |
| 1260 | } |
| 1261 | |
| 1262 | /* Read data from the FIFO for an endpoint. This function is for endpoints (such |
| 1263 | * as EP0) that don't use DMA. This function should only be called if a packet |
| 1264 | * is known to be ready to read for the endpoint. Note that the endpoint must |
| 1265 | * be selected in the protocol engine prior to this call. */ |
| 1266 | static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, |
| 1267 | u32 bytes) |
| 1268 | { |
| 1269 | u32 tmpv; |
| 1270 | int to = 1000; |
| 1271 | u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN; |
| 1272 | |
| 1273 | /* Setup read of endpoint */ |
| 1274 | writel(hwrep, USBD_CTRL(udc->udp_baseaddr)); |
| 1275 | |
| 1276 | /* Wait until packet is ready */ |
| 1277 | while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) & |
| 1278 | PKT_RDY) == 0) && (to > 0)) |
| 1279 | to--; |
| 1280 | if (!to) |
| 1281 | dev_dbg(udc->dev, "No packet ready on FIFO EP read\n"); |
| 1282 | |
| 1283 | /* Mask out count */ |
| 1284 | tmp = tmpv & PKT_LNGTH_MASK; |
| 1285 | if (bytes < tmp) |
| 1286 | tmp = bytes; |
| 1287 | |
| 1288 | if ((tmp > 0) && (data != NULL)) |
| 1289 | udc_pop_fifo(udc, (u8 *) data, tmp); |
| 1290 | |
| 1291 | writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); |
| 1292 | |
| 1293 | /* Clear the buffer */ |
| 1294 | udc_clr_buffer_hwep(udc, hwep); |
| 1295 | |
| 1296 | return tmp; |
| 1297 | } |
| 1298 | |
| 1299 | /* Stuffs data into the FIFO, adjusts for alignment and data size */ |
| 1300 | static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) |
| 1301 | { |
| 1302 | int n, i, bl; |
| 1303 | u16 *p16; |
| 1304 | u32 *p32, tmp, cbytes; |
| 1305 | |
| 1306 | /* Use optimal data transfer method based on source address and size */ |
| 1307 | switch (((u32) data) & 0x3) { |
| 1308 | case 0: /* 32-bit aligned */ |
| 1309 | p32 = (u32 *) data; |
| 1310 | cbytes = (bytes & ~0x3); |
| 1311 | |
| 1312 | /* Copy 32-bit aligned data first */ |
| 1313 | for (n = 0; n < cbytes; n += 4) |
| 1314 | writel(*p32++, USBD_TXDATA(udc->udp_baseaddr)); |
| 1315 | |
| 1316 | /* Handle any remaining bytes */ |
| 1317 | bl = bytes - cbytes; |
| 1318 | if (bl) { |
| 1319 | tmp = 0; |
| 1320 | for (n = 0; n < bl; n++) |
| 1321 | tmp |= data[cbytes + n] << (n * 8); |
| 1322 | |
| 1323 | writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); |
| 1324 | } |
| 1325 | break; |
| 1326 | |
| 1327 | case 1: /* 8-bit aligned */ |
| 1328 | case 3: |
| 1329 | /* Each byte has to be handled independently */ |
| 1330 | for (n = 0; n < bytes; n += 4) { |
| 1331 | bl = bytes - n; |
| 1332 | if (bl > 4) |
| 1333 | bl = 4; |
| 1334 | |
| 1335 | tmp = 0; |
| 1336 | for (i = 0; i < bl; i++) |
| 1337 | tmp |= data[n + i] << (i * 8); |
| 1338 | |
| 1339 | writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); |
| 1340 | } |
| 1341 | break; |
| 1342 | |
| 1343 | case 2: /* 16-bit aligned */ |
| 1344 | p16 = (u16 *) data; |
| 1345 | cbytes = (bytes & ~0x3); |
| 1346 | |
| 1347 | /* Copy 32-bit aligned data first */ |
| 1348 | for (n = 0; n < cbytes; n += 4) { |
| 1349 | tmp = *p16++ & 0xFFFF; |
| 1350 | tmp |= (*p16++ & 0xFFFF) << 16; |
| 1351 | writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); |
| 1352 | } |
| 1353 | |
| 1354 | /* Handle any remaining bytes */ |
| 1355 | bl = bytes - cbytes; |
| 1356 | if (bl) { |
| 1357 | tmp = 0; |
| 1358 | for (n = 0; n < bl; n++) |
| 1359 | tmp |= data[cbytes + n] << (n * 8); |
| 1360 | |
| 1361 | writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); |
| 1362 | } |
| 1363 | break; |
| 1364 | } |
| 1365 | } |
| 1366 | |
| 1367 | /* Write data to the FIFO for an endpoint. This function is for endpoints (such |
| 1368 | * as EP0) that don't use DMA. Note that the endpoint must be selected in the |
| 1369 | * protocol engine prior to this call. */ |
| 1370 | static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, |
| 1371 | u32 bytes) |
| 1372 | { |
| 1373 | u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN; |
| 1374 | |
| 1375 | if ((bytes > 0) && (data == NULL)) |
| 1376 | return; |
| 1377 | |
| 1378 | /* Setup write of endpoint */ |
| 1379 | writel(hwwep, USBD_CTRL(udc->udp_baseaddr)); |
| 1380 | |
| 1381 | writel(bytes, USBD_TXPLEN(udc->udp_baseaddr)); |
| 1382 | |
| 1383 | /* Need at least 1 byte to trigger TX */ |
| 1384 | if (bytes == 0) |
| 1385 | writel(0, USBD_TXDATA(udc->udp_baseaddr)); |
| 1386 | else |
| 1387 | udc_stuff_fifo(udc, (u8 *) data, bytes); |
| 1388 | |
| 1389 | writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); |
| 1390 | |
| 1391 | udc_val_buffer_hwep(udc, hwep); |
| 1392 | } |
| 1393 | |
| 1394 | /* USB device reset - resets USB to a default state with just EP0 |
| 1395 | enabled */ |
| 1396 | static void uda_usb_reset(struct lpc32xx_udc *udc) |
| 1397 | { |
| 1398 | u32 i = 0; |
| 1399 | /* Re-init device controller and EP0 */ |
| 1400 | udc_enable(udc); |
| 1401 | udc->gadget.speed = USB_SPEED_FULL; |
| 1402 | |
| 1403 | for (i = 1; i < NUM_ENDPOINTS; i++) { |
| 1404 | struct lpc32xx_ep *ep = &udc->ep[i]; |
| 1405 | ep->req_pending = 0; |
| 1406 | } |
| 1407 | } |
| 1408 | |
| 1409 | /* Send a ZLP on EP0 */ |
| 1410 | static void udc_ep0_send_zlp(struct lpc32xx_udc *udc) |
| 1411 | { |
| 1412 | udc_write_hwep(udc, EP_IN, NULL, 0); |
| 1413 | } |
| 1414 | |
| 1415 | /* Get current frame number */ |
| 1416 | static u16 udc_get_current_frame(struct lpc32xx_udc *udc) |
| 1417 | { |
| 1418 | u16 flo, fhi; |
| 1419 | |
| 1420 | udc_protocol_cmd_w(udc, CMD_RD_FRAME); |
| 1421 | flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); |
| 1422 | fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); |
| 1423 | |
| 1424 | return (fhi << 8) | flo; |
| 1425 | } |
| 1426 | |
| 1427 | /* Set the device as configured - enables all endpoints */ |
| 1428 | static inline void udc_set_device_configured(struct lpc32xx_udc *udc) |
| 1429 | { |
| 1430 | udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE)); |
| 1431 | } |
| 1432 | |
| 1433 | /* Set the device as unconfigured - disables all endpoints */ |
| 1434 | static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc) |
| 1435 | { |
| 1436 | udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); |
| 1437 | } |
| 1438 | |
| 1439 | /* reinit == restore initial software state */ |
| 1440 | static void udc_reinit(struct lpc32xx_udc *udc) |
| 1441 | { |
| 1442 | u32 i; |
| 1443 | |
| 1444 | INIT_LIST_HEAD(&udc->gadget.ep_list); |
| 1445 | INIT_LIST_HEAD(&udc->gadget.ep0->ep_list); |
| 1446 | |
| 1447 | for (i = 0; i < NUM_ENDPOINTS; i++) { |
| 1448 | struct lpc32xx_ep *ep = &udc->ep[i]; |
| 1449 | |
| 1450 | if (i != 0) |
| 1451 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); |
Robert Baldyga | e117e74 | 2013-12-13 12:23:38 +0100 | [diff] [blame] | 1452 | usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1453 | INIT_LIST_HEAD(&ep->queue); |
| 1454 | ep->req_pending = 0; |
| 1455 | } |
| 1456 | |
| 1457 | udc->ep0state = WAIT_FOR_SETUP; |
| 1458 | } |
| 1459 | |
| 1460 | /* Must be called with lock */ |
| 1461 | static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status) |
| 1462 | { |
| 1463 | struct lpc32xx_udc *udc = ep->udc; |
| 1464 | |
| 1465 | list_del_init(&req->queue); |
| 1466 | if (req->req.status == -EINPROGRESS) |
| 1467 | req->req.status = status; |
| 1468 | else |
| 1469 | status = req->req.status; |
| 1470 | |
| 1471 | if (ep->lep) { |
Felipe Balbi | 369ac9c | 2013-01-28 17:13:27 +0200 | [diff] [blame] | 1472 | usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1473 | |
| 1474 | /* Free DDs */ |
| 1475 | udc_dd_free(udc, req->dd_desc_ptr); |
| 1476 | } |
| 1477 | |
| 1478 | if (status && status != -ESHUTDOWN) |
| 1479 | ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status); |
| 1480 | |
| 1481 | ep->req_pending = 0; |
| 1482 | spin_unlock(&udc->lock); |
| 1483 | req->req.complete(&ep->ep, &req->req); |
| 1484 | spin_lock(&udc->lock); |
| 1485 | } |
| 1486 | |
| 1487 | /* Must be called with lock */ |
| 1488 | static void nuke(struct lpc32xx_ep *ep, int status) |
| 1489 | { |
| 1490 | struct lpc32xx_request *req; |
| 1491 | |
| 1492 | while (!list_empty(&ep->queue)) { |
| 1493 | req = list_entry(ep->queue.next, struct lpc32xx_request, queue); |
| 1494 | done(ep, req, status); |
| 1495 | } |
| 1496 | |
Roland Stigge | 78ca913 | 2012-08-20 10:30:13 +0200 | [diff] [blame] | 1497 | if (status == -ESHUTDOWN) { |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1498 | uda_disable_hwepint(ep->udc, ep->hwep_num); |
| 1499 | udc_disable_hwep(ep->udc, ep->hwep_num); |
| 1500 | } |
| 1501 | } |
| 1502 | |
| 1503 | /* IN endpoint 0 transfer */ |
| 1504 | static int udc_ep0_in_req(struct lpc32xx_udc *udc) |
| 1505 | { |
| 1506 | struct lpc32xx_request *req; |
| 1507 | struct lpc32xx_ep *ep0 = &udc->ep[0]; |
| 1508 | u32 tsend, ts = 0; |
| 1509 | |
| 1510 | if (list_empty(&ep0->queue)) |
| 1511 | /* Nothing to send */ |
| 1512 | return 0; |
| 1513 | else |
| 1514 | req = list_entry(ep0->queue.next, struct lpc32xx_request, |
| 1515 | queue); |
| 1516 | |
| 1517 | tsend = ts = req->req.length - req->req.actual; |
| 1518 | if (ts == 0) { |
| 1519 | /* Send a ZLP */ |
| 1520 | udc_ep0_send_zlp(udc); |
| 1521 | done(ep0, req, 0); |
| 1522 | return 1; |
| 1523 | } else if (ts > ep0->ep.maxpacket) |
| 1524 | ts = ep0->ep.maxpacket; /* Just send what we can */ |
| 1525 | |
| 1526 | /* Write data to the EP0 FIFO and start transfer */ |
| 1527 | udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts); |
| 1528 | |
| 1529 | /* Increment data pointer */ |
| 1530 | req->req.actual += ts; |
| 1531 | |
| 1532 | if (tsend >= ep0->ep.maxpacket) |
| 1533 | return 0; /* Stay in data transfer state */ |
| 1534 | |
| 1535 | /* Transfer request is complete */ |
| 1536 | udc->ep0state = WAIT_FOR_SETUP; |
| 1537 | done(ep0, req, 0); |
| 1538 | return 1; |
| 1539 | } |
| 1540 | |
| 1541 | /* OUT endpoint 0 transfer */ |
| 1542 | static int udc_ep0_out_req(struct lpc32xx_udc *udc) |
| 1543 | { |
| 1544 | struct lpc32xx_request *req; |
| 1545 | struct lpc32xx_ep *ep0 = &udc->ep[0]; |
| 1546 | u32 tr, bufferspace; |
| 1547 | |
| 1548 | if (list_empty(&ep0->queue)) |
| 1549 | return 0; |
| 1550 | else |
| 1551 | req = list_entry(ep0->queue.next, struct lpc32xx_request, |
| 1552 | queue); |
| 1553 | |
| 1554 | if (req) { |
| 1555 | if (req->req.length == 0) { |
| 1556 | /* Just dequeue request */ |
| 1557 | done(ep0, req, 0); |
| 1558 | udc->ep0state = WAIT_FOR_SETUP; |
| 1559 | return 1; |
| 1560 | } |
| 1561 | |
| 1562 | /* Get data from FIFO */ |
| 1563 | bufferspace = req->req.length - req->req.actual; |
| 1564 | if (bufferspace > ep0->ep.maxpacket) |
| 1565 | bufferspace = ep0->ep.maxpacket; |
| 1566 | |
| 1567 | /* Copy data to buffer */ |
| 1568 | prefetchw(req->req.buf + req->req.actual); |
| 1569 | tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual, |
| 1570 | bufferspace); |
| 1571 | req->req.actual += bufferspace; |
| 1572 | |
| 1573 | if (tr < ep0->ep.maxpacket) { |
| 1574 | /* This is the last packet */ |
| 1575 | done(ep0, req, 0); |
| 1576 | udc->ep0state = WAIT_FOR_SETUP; |
| 1577 | return 1; |
| 1578 | } |
| 1579 | } |
| 1580 | |
| 1581 | return 0; |
| 1582 | } |
| 1583 | |
| 1584 | /* Must be called with lock */ |
| 1585 | static void stop_activity(struct lpc32xx_udc *udc) |
| 1586 | { |
| 1587 | struct usb_gadget_driver *driver = udc->driver; |
| 1588 | int i; |
| 1589 | |
| 1590 | if (udc->gadget.speed == USB_SPEED_UNKNOWN) |
| 1591 | driver = NULL; |
| 1592 | |
| 1593 | udc->gadget.speed = USB_SPEED_UNKNOWN; |
| 1594 | udc->suspended = 0; |
| 1595 | |
| 1596 | for (i = 0; i < NUM_ENDPOINTS; i++) { |
| 1597 | struct lpc32xx_ep *ep = &udc->ep[i]; |
| 1598 | nuke(ep, -ESHUTDOWN); |
| 1599 | } |
| 1600 | if (driver) { |
| 1601 | spin_unlock(&udc->lock); |
| 1602 | driver->disconnect(&udc->gadget); |
| 1603 | spin_lock(&udc->lock); |
| 1604 | } |
| 1605 | |
| 1606 | isp1301_pullup_enable(udc, 0, 0); |
| 1607 | udc_disable(udc); |
| 1608 | udc_reinit(udc); |
| 1609 | } |
| 1610 | |
| 1611 | /* |
| 1612 | * Activate or kill host pullup |
| 1613 | * Can be called with or without lock |
| 1614 | */ |
| 1615 | static void pullup(struct lpc32xx_udc *udc, int is_on) |
| 1616 | { |
| 1617 | if (!udc->clocked) |
| 1618 | return; |
| 1619 | |
| 1620 | if (!udc->enabled || !udc->vbus) |
| 1621 | is_on = 0; |
| 1622 | |
| 1623 | if (is_on != udc->pullup) |
| 1624 | isp1301_pullup_enable(udc, is_on, 0); |
| 1625 | } |
| 1626 | |
| 1627 | /* Must be called without lock */ |
| 1628 | static int lpc32xx_ep_disable(struct usb_ep *_ep) |
| 1629 | { |
| 1630 | struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); |
| 1631 | struct lpc32xx_udc *udc = ep->udc; |
| 1632 | unsigned long flags; |
| 1633 | |
| 1634 | if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0)) |
| 1635 | return -EINVAL; |
| 1636 | spin_lock_irqsave(&udc->lock, flags); |
| 1637 | |
| 1638 | nuke(ep, -ESHUTDOWN); |
| 1639 | |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1640 | /* Clear all DMA statuses for this EP */ |
| 1641 | udc_ep_dma_disable(udc, ep->hwep_num); |
| 1642 | writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); |
| 1643 | writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); |
| 1644 | writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); |
| 1645 | writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); |
| 1646 | |
| 1647 | /* Remove the DD pointer in the UDCA */ |
| 1648 | udc->udca_v_base[ep->hwep_num] = 0; |
| 1649 | |
| 1650 | /* Disable and reset endpoint and interrupt */ |
| 1651 | uda_clear_hwepint(udc, ep->hwep_num); |
| 1652 | udc_unrealize_hwep(udc, ep->hwep_num); |
| 1653 | |
| 1654 | ep->hwep_num = 0; |
| 1655 | |
| 1656 | spin_unlock_irqrestore(&udc->lock, flags); |
| 1657 | |
| 1658 | atomic_dec(&udc->enabled_ep_cnt); |
| 1659 | wake_up(&udc->ep_disable_wait_queue); |
| 1660 | |
| 1661 | return 0; |
| 1662 | } |
| 1663 | |
| 1664 | /* Must be called without lock */ |
| 1665 | static int lpc32xx_ep_enable(struct usb_ep *_ep, |
| 1666 | const struct usb_endpoint_descriptor *desc) |
| 1667 | { |
| 1668 | struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); |
| 1669 | struct lpc32xx_udc *udc = ep->udc; |
| 1670 | u16 maxpacket; |
| 1671 | u32 tmp; |
| 1672 | unsigned long flags; |
| 1673 | |
| 1674 | /* Verify EP data */ |
Roland Stigge | 78ca913 | 2012-08-20 10:30:13 +0200 | [diff] [blame] | 1675 | if ((!_ep) || (!ep) || (!desc) || |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1676 | (desc->bDescriptorType != USB_DT_ENDPOINT)) { |
| 1677 | dev_dbg(udc->dev, "bad ep or descriptor\n"); |
| 1678 | return -EINVAL; |
| 1679 | } |
| 1680 | maxpacket = usb_endpoint_maxp(desc); |
| 1681 | if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) { |
| 1682 | dev_dbg(udc->dev, "bad ep descriptor's packet size\n"); |
| 1683 | return -EINVAL; |
| 1684 | } |
| 1685 | |
| 1686 | /* Don't touch EP0 */ |
| 1687 | if (ep->hwep_num_base == 0) { |
| 1688 | dev_dbg(udc->dev, "Can't re-enable EP0!!!\n"); |
| 1689 | return -EINVAL; |
| 1690 | } |
| 1691 | |
| 1692 | /* Is driver ready? */ |
| 1693 | if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { |
| 1694 | dev_dbg(udc->dev, "bogus device state\n"); |
| 1695 | return -ESHUTDOWN; |
| 1696 | } |
| 1697 | |
| 1698 | tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
| 1699 | switch (tmp) { |
| 1700 | case USB_ENDPOINT_XFER_CONTROL: |
| 1701 | return -EINVAL; |
| 1702 | |
| 1703 | case USB_ENDPOINT_XFER_INT: |
| 1704 | if (maxpacket > ep->maxpacket) { |
| 1705 | dev_dbg(udc->dev, |
| 1706 | "Bad INT endpoint maxpacket %d\n", maxpacket); |
| 1707 | return -EINVAL; |
| 1708 | } |
| 1709 | break; |
| 1710 | |
| 1711 | case USB_ENDPOINT_XFER_BULK: |
| 1712 | switch (maxpacket) { |
| 1713 | case 8: |
| 1714 | case 16: |
| 1715 | case 32: |
| 1716 | case 64: |
| 1717 | break; |
| 1718 | |
| 1719 | default: |
| 1720 | dev_dbg(udc->dev, |
| 1721 | "Bad BULK endpoint maxpacket %d\n", maxpacket); |
| 1722 | return -EINVAL; |
| 1723 | } |
| 1724 | break; |
| 1725 | |
| 1726 | case USB_ENDPOINT_XFER_ISOC: |
| 1727 | break; |
| 1728 | } |
| 1729 | spin_lock_irqsave(&udc->lock, flags); |
| 1730 | |
| 1731 | /* Initialize endpoint to match the selected descriptor */ |
| 1732 | ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1733 | ep->ep.maxpacket = maxpacket; |
| 1734 | |
| 1735 | /* Map hardware endpoint from base and direction */ |
| 1736 | if (ep->is_in) |
| 1737 | /* IN endpoints are offset 1 from the OUT endpoint */ |
| 1738 | ep->hwep_num = ep->hwep_num_base + EP_IN; |
| 1739 | else |
| 1740 | ep->hwep_num = ep->hwep_num_base; |
| 1741 | |
| 1742 | ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name, |
| 1743 | ep->hwep_num, maxpacket, (ep->is_in == 1)); |
| 1744 | |
| 1745 | /* Realize the endpoint, interrupt is enabled later when |
| 1746 | * buffers are queued, IN EPs will NAK until buffers are ready */ |
| 1747 | udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket); |
| 1748 | udc_clr_buffer_hwep(udc, ep->hwep_num); |
| 1749 | uda_disable_hwepint(udc, ep->hwep_num); |
| 1750 | udc_clrstall_hwep(udc, ep->hwep_num); |
| 1751 | |
| 1752 | /* Clear all DMA statuses for this EP */ |
| 1753 | udc_ep_dma_disable(udc, ep->hwep_num); |
| 1754 | writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); |
| 1755 | writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); |
| 1756 | writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); |
| 1757 | writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); |
| 1758 | |
| 1759 | spin_unlock_irqrestore(&udc->lock, flags); |
| 1760 | |
| 1761 | atomic_inc(&udc->enabled_ep_cnt); |
| 1762 | return 0; |
| 1763 | } |
| 1764 | |
| 1765 | /* |
| 1766 | * Allocate a USB request list |
| 1767 | * Can be called with or without lock |
| 1768 | */ |
| 1769 | static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep, |
| 1770 | gfp_t gfp_flags) |
| 1771 | { |
| 1772 | struct lpc32xx_request *req; |
| 1773 | |
| 1774 | req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags); |
| 1775 | if (!req) |
| 1776 | return NULL; |
| 1777 | |
| 1778 | INIT_LIST_HEAD(&req->queue); |
| 1779 | return &req->req; |
| 1780 | } |
| 1781 | |
| 1782 | /* |
| 1783 | * De-allocate a USB request list |
| 1784 | * Can be called with or without lock |
| 1785 | */ |
| 1786 | static void lpc32xx_ep_free_request(struct usb_ep *_ep, |
| 1787 | struct usb_request *_req) |
| 1788 | { |
| 1789 | struct lpc32xx_request *req; |
| 1790 | |
| 1791 | req = container_of(_req, struct lpc32xx_request, req); |
| 1792 | BUG_ON(!list_empty(&req->queue)); |
| 1793 | kfree(req); |
| 1794 | } |
| 1795 | |
| 1796 | /* Must be called without lock */ |
| 1797 | static int lpc32xx_ep_queue(struct usb_ep *_ep, |
| 1798 | struct usb_request *_req, gfp_t gfp_flags) |
| 1799 | { |
| 1800 | struct lpc32xx_request *req; |
| 1801 | struct lpc32xx_ep *ep; |
| 1802 | struct lpc32xx_udc *udc; |
| 1803 | unsigned long flags; |
| 1804 | int status = 0; |
| 1805 | |
| 1806 | req = container_of(_req, struct lpc32xx_request, req); |
| 1807 | ep = container_of(_ep, struct lpc32xx_ep, ep); |
| 1808 | |
| 1809 | if (!_req || !_req->complete || !_req->buf || |
| 1810 | !list_empty(&req->queue)) |
| 1811 | return -EINVAL; |
| 1812 | |
| 1813 | udc = ep->udc; |
| 1814 | |
Roland Stigge | 78ca913 | 2012-08-20 10:30:13 +0200 | [diff] [blame] | 1815 | if (!_ep) { |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1816 | dev_dbg(udc->dev, "invalid ep\n"); |
| 1817 | return -EINVAL; |
| 1818 | } |
| 1819 | |
| 1820 | |
| 1821 | if ((!udc) || (!udc->driver) || |
| 1822 | (udc->gadget.speed == USB_SPEED_UNKNOWN)) { |
| 1823 | dev_dbg(udc->dev, "invalid device\n"); |
| 1824 | return -EINVAL; |
| 1825 | } |
| 1826 | |
| 1827 | if (ep->lep) { |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1828 | struct lpc32xx_usbd_dd_gad *dd; |
| 1829 | |
Felipe Balbi | 369ac9c | 2013-01-28 17:13:27 +0200 | [diff] [blame] | 1830 | status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in); |
| 1831 | if (status) |
| 1832 | return status; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1833 | |
| 1834 | /* For the request, build a list of DDs */ |
| 1835 | dd = udc_dd_alloc(udc); |
| 1836 | if (!dd) { |
| 1837 | /* Error allocating DD */ |
| 1838 | return -ENOMEM; |
| 1839 | } |
| 1840 | req->dd_desc_ptr = dd; |
| 1841 | |
| 1842 | /* Setup the DMA descriptor */ |
| 1843 | dd->dd_next_phy = dd->dd_next_v = 0; |
| 1844 | dd->dd_buffer_addr = req->req.dma; |
| 1845 | dd->dd_status = 0; |
| 1846 | |
| 1847 | /* Special handling for ISO EPs */ |
| 1848 | if (ep->eptype == EP_ISO_TYPE) { |
| 1849 | dd->dd_setup = DD_SETUP_ISO_EP | |
| 1850 | DD_SETUP_PACKETLEN(0) | |
| 1851 | DD_SETUP_DMALENBYTES(1); |
| 1852 | dd->dd_iso_ps_mem_addr = dd->this_dma + 24; |
| 1853 | if (ep->is_in) |
| 1854 | dd->iso_status[0] = req->req.length; |
| 1855 | else |
| 1856 | dd->iso_status[0] = 0; |
| 1857 | } else |
| 1858 | dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) | |
| 1859 | DD_SETUP_DMALENBYTES(req->req.length); |
| 1860 | } |
| 1861 | |
| 1862 | ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name, |
| 1863 | _req, _req->length, _req->buf, ep->is_in, _req->zero); |
| 1864 | |
| 1865 | spin_lock_irqsave(&udc->lock, flags); |
| 1866 | |
| 1867 | _req->status = -EINPROGRESS; |
| 1868 | _req->actual = 0; |
| 1869 | req->send_zlp = _req->zero; |
| 1870 | |
| 1871 | /* Kickstart empty queues */ |
| 1872 | if (list_empty(&ep->queue)) { |
| 1873 | list_add_tail(&req->queue, &ep->queue); |
| 1874 | |
| 1875 | if (ep->hwep_num_base == 0) { |
| 1876 | /* Handle expected data direction */ |
| 1877 | if (ep->is_in) { |
| 1878 | /* IN packet to host */ |
| 1879 | udc->ep0state = DATA_IN; |
| 1880 | status = udc_ep0_in_req(udc); |
| 1881 | } else { |
| 1882 | /* OUT packet from host */ |
| 1883 | udc->ep0state = DATA_OUT; |
| 1884 | status = udc_ep0_out_req(udc); |
| 1885 | } |
| 1886 | } else if (ep->is_in) { |
| 1887 | /* IN packet to host and kick off transfer */ |
| 1888 | if (!ep->req_pending) |
| 1889 | udc_ep_in_req_dma(udc, ep); |
| 1890 | } else |
| 1891 | /* OUT packet from host and kick off list */ |
| 1892 | if (!ep->req_pending) |
| 1893 | udc_ep_out_req_dma(udc, ep); |
| 1894 | } else |
| 1895 | list_add_tail(&req->queue, &ep->queue); |
| 1896 | |
| 1897 | spin_unlock_irqrestore(&udc->lock, flags); |
| 1898 | |
| 1899 | return (status < 0) ? status : 0; |
| 1900 | } |
| 1901 | |
| 1902 | /* Must be called without lock */ |
| 1903 | static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
| 1904 | { |
| 1905 | struct lpc32xx_ep *ep; |
| 1906 | struct lpc32xx_request *req; |
| 1907 | unsigned long flags; |
| 1908 | |
| 1909 | ep = container_of(_ep, struct lpc32xx_ep, ep); |
| 1910 | if (!_ep || ep->hwep_num_base == 0) |
| 1911 | return -EINVAL; |
| 1912 | |
| 1913 | spin_lock_irqsave(&ep->udc->lock, flags); |
| 1914 | |
| 1915 | /* make sure it's actually queued on this endpoint */ |
| 1916 | list_for_each_entry(req, &ep->queue, queue) { |
| 1917 | if (&req->req == _req) |
| 1918 | break; |
| 1919 | } |
| 1920 | if (&req->req != _req) { |
| 1921 | spin_unlock_irqrestore(&ep->udc->lock, flags); |
| 1922 | return -EINVAL; |
| 1923 | } |
| 1924 | |
| 1925 | done(ep, req, -ECONNRESET); |
| 1926 | |
| 1927 | spin_unlock_irqrestore(&ep->udc->lock, flags); |
| 1928 | |
| 1929 | return 0; |
| 1930 | } |
| 1931 | |
| 1932 | /* Must be called without lock */ |
| 1933 | static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value) |
| 1934 | { |
| 1935 | struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); |
| 1936 | struct lpc32xx_udc *udc = ep->udc; |
| 1937 | unsigned long flags; |
| 1938 | |
Roland Stigge | 78ca913 | 2012-08-20 10:30:13 +0200 | [diff] [blame] | 1939 | if ((!ep) || (ep->hwep_num <= 1)) |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 1940 | return -EINVAL; |
| 1941 | |
| 1942 | /* Don't halt an IN EP */ |
| 1943 | if (ep->is_in) |
| 1944 | return -EAGAIN; |
| 1945 | |
| 1946 | spin_lock_irqsave(&udc->lock, flags); |
| 1947 | |
| 1948 | if (value == 1) { |
| 1949 | /* stall */ |
| 1950 | udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), |
| 1951 | DAT_WR_BYTE(EP_STAT_ST)); |
| 1952 | } else { |
| 1953 | /* End stall */ |
| 1954 | ep->wedge = 0; |
| 1955 | udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), |
| 1956 | DAT_WR_BYTE(0)); |
| 1957 | } |
| 1958 | |
| 1959 | spin_unlock_irqrestore(&udc->lock, flags); |
| 1960 | |
| 1961 | return 0; |
| 1962 | } |
| 1963 | |
| 1964 | /* set the halt feature and ignores clear requests */ |
| 1965 | static int lpc32xx_ep_set_wedge(struct usb_ep *_ep) |
| 1966 | { |
| 1967 | struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); |
| 1968 | |
| 1969 | if (!_ep || !ep->udc) |
| 1970 | return -EINVAL; |
| 1971 | |
| 1972 | ep->wedge = 1; |
| 1973 | |
| 1974 | return usb_ep_set_halt(_ep); |
| 1975 | } |
| 1976 | |
| 1977 | static const struct usb_ep_ops lpc32xx_ep_ops = { |
| 1978 | .enable = lpc32xx_ep_enable, |
| 1979 | .disable = lpc32xx_ep_disable, |
| 1980 | .alloc_request = lpc32xx_ep_alloc_request, |
| 1981 | .free_request = lpc32xx_ep_free_request, |
| 1982 | .queue = lpc32xx_ep_queue, |
| 1983 | .dequeue = lpc32xx_ep_dequeue, |
| 1984 | .set_halt = lpc32xx_ep_set_halt, |
| 1985 | .set_wedge = lpc32xx_ep_set_wedge, |
| 1986 | }; |
| 1987 | |
| 1988 | /* Send a ZLP on a non-0 IN EP */ |
| 1989 | void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) |
| 1990 | { |
| 1991 | /* Clear EP status */ |
| 1992 | udc_clearep_getsts(udc, ep->hwep_num); |
| 1993 | |
| 1994 | /* Send ZLP via FIFO mechanism */ |
| 1995 | udc_write_hwep(udc, ep->hwep_num, NULL, 0); |
| 1996 | } |
| 1997 | |
| 1998 | /* |
| 1999 | * Handle EP completion for ZLP |
| 2000 | * This function will only be called when a delayed ZLP needs to be sent out |
| 2001 | * after a DMA transfer has filled both buffers. |
| 2002 | */ |
| 2003 | void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) |
| 2004 | { |
| 2005 | u32 epstatus; |
| 2006 | struct lpc32xx_request *req; |
| 2007 | |
| 2008 | if (ep->hwep_num <= 0) |
| 2009 | return; |
| 2010 | |
| 2011 | uda_clear_hwepint(udc, ep->hwep_num); |
| 2012 | |
| 2013 | /* If this interrupt isn't enabled, return now */ |
| 2014 | if (!(udc->enabled_hwepints & (1 << ep->hwep_num))) |
| 2015 | return; |
| 2016 | |
| 2017 | /* Get endpoint status */ |
| 2018 | epstatus = udc_clearep_getsts(udc, ep->hwep_num); |
| 2019 | |
| 2020 | /* |
| 2021 | * This should never happen, but protect against writing to the |
| 2022 | * buffer when full. |
| 2023 | */ |
| 2024 | if (epstatus & EP_SEL_F) |
| 2025 | return; |
| 2026 | |
| 2027 | if (ep->is_in) { |
| 2028 | udc_send_in_zlp(udc, ep); |
| 2029 | uda_disable_hwepint(udc, ep->hwep_num); |
| 2030 | } else |
| 2031 | return; |
| 2032 | |
| 2033 | /* If there isn't a request waiting, something went wrong */ |
| 2034 | req = list_entry(ep->queue.next, struct lpc32xx_request, queue); |
| 2035 | if (req) { |
| 2036 | done(ep, req, 0); |
| 2037 | |
| 2038 | /* Start another request if ready */ |
| 2039 | if (!list_empty(&ep->queue)) { |
| 2040 | if (ep->is_in) |
| 2041 | udc_ep_in_req_dma(udc, ep); |
| 2042 | else |
| 2043 | udc_ep_out_req_dma(udc, ep); |
| 2044 | } else |
| 2045 | ep->req_pending = 0; |
| 2046 | } |
| 2047 | } |
| 2048 | |
| 2049 | |
| 2050 | /* DMA end of transfer completion */ |
| 2051 | static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) |
| 2052 | { |
| 2053 | u32 status, epstatus; |
| 2054 | struct lpc32xx_request *req; |
| 2055 | struct lpc32xx_usbd_dd_gad *dd; |
| 2056 | |
| 2057 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES |
| 2058 | ep->totalints++; |
| 2059 | #endif |
| 2060 | |
| 2061 | req = list_entry(ep->queue.next, struct lpc32xx_request, queue); |
| 2062 | if (!req) { |
| 2063 | ep_err(ep, "DMA interrupt on no req!\n"); |
| 2064 | return; |
| 2065 | } |
| 2066 | dd = req->dd_desc_ptr; |
| 2067 | |
| 2068 | /* DMA descriptor should always be retired for this call */ |
| 2069 | if (!(dd->dd_status & DD_STATUS_DD_RETIRED)) |
| 2070 | ep_warn(ep, "DMA descriptor did not retire\n"); |
| 2071 | |
| 2072 | /* Disable DMA */ |
| 2073 | udc_ep_dma_disable(udc, ep->hwep_num); |
| 2074 | writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr)); |
| 2075 | writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr)); |
| 2076 | |
| 2077 | /* System error? */ |
| 2078 | if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) & |
| 2079 | (1 << ep->hwep_num)) { |
| 2080 | writel((1 << ep->hwep_num), |
| 2081 | USBD_SYSERRTINTCLR(udc->udp_baseaddr)); |
| 2082 | ep_err(ep, "AHB critical error!\n"); |
| 2083 | ep->req_pending = 0; |
| 2084 | |
| 2085 | /* The error could have occurred on a packet of a multipacket |
| 2086 | * transfer, so recovering the transfer is not possible. Close |
| 2087 | * the request with an error */ |
| 2088 | done(ep, req, -ECONNABORTED); |
| 2089 | return; |
| 2090 | } |
| 2091 | |
| 2092 | /* Handle the current DD's status */ |
| 2093 | status = dd->dd_status; |
| 2094 | switch (status & DD_STATUS_STS_MASK) { |
| 2095 | case DD_STATUS_STS_NS: |
| 2096 | /* DD not serviced? This shouldn't happen! */ |
| 2097 | ep->req_pending = 0; |
| 2098 | ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n", |
| 2099 | status); |
| 2100 | |
| 2101 | done(ep, req, -ECONNABORTED); |
| 2102 | return; |
| 2103 | |
| 2104 | case DD_STATUS_STS_BS: |
| 2105 | /* Interrupt only fires on EOT - This shouldn't happen! */ |
| 2106 | ep->req_pending = 0; |
| 2107 | ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n", |
| 2108 | status); |
| 2109 | done(ep, req, -ECONNABORTED); |
| 2110 | return; |
| 2111 | |
| 2112 | case DD_STATUS_STS_NC: |
| 2113 | case DD_STATUS_STS_DUR: |
| 2114 | /* Really just a short packet, not an underrun */ |
| 2115 | /* This is a good status and what we expect */ |
| 2116 | break; |
| 2117 | |
| 2118 | default: |
| 2119 | /* Data overrun, system error, or unknown */ |
| 2120 | ep->req_pending = 0; |
| 2121 | ep_err(ep, "DMA critical EP error: System error (0x%x)!\n", |
| 2122 | status); |
| 2123 | done(ep, req, -ECONNABORTED); |
| 2124 | return; |
| 2125 | } |
| 2126 | |
| 2127 | /* ISO endpoints are handled differently */ |
| 2128 | if (ep->eptype == EP_ISO_TYPE) { |
| 2129 | if (ep->is_in) |
| 2130 | req->req.actual = req->req.length; |
| 2131 | else |
| 2132 | req->req.actual = dd->iso_status[0] & 0xFFFF; |
| 2133 | } else |
| 2134 | req->req.actual += DD_STATUS_CURDMACNT(status); |
| 2135 | |
| 2136 | /* Send a ZLP if necessary. This will be done for non-int |
| 2137 | * packets which have a size that is a divisor of MAXP */ |
| 2138 | if (req->send_zlp) { |
| 2139 | /* |
| 2140 | * If at least 1 buffer is available, send the ZLP now. |
| 2141 | * Otherwise, the ZLP send needs to be deferred until a |
| 2142 | * buffer is available. |
| 2143 | */ |
| 2144 | if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) { |
| 2145 | udc_clearep_getsts(udc, ep->hwep_num); |
| 2146 | uda_enable_hwepint(udc, ep->hwep_num); |
| 2147 | epstatus = udc_clearep_getsts(udc, ep->hwep_num); |
| 2148 | |
| 2149 | /* Let the EP interrupt handle the ZLP */ |
| 2150 | return; |
| 2151 | } else |
| 2152 | udc_send_in_zlp(udc, ep); |
| 2153 | } |
| 2154 | |
| 2155 | /* Transfer request is complete */ |
| 2156 | done(ep, req, 0); |
| 2157 | |
| 2158 | /* Start another request if ready */ |
| 2159 | udc_clearep_getsts(udc, ep->hwep_num); |
| 2160 | if (!list_empty((&ep->queue))) { |
| 2161 | if (ep->is_in) |
| 2162 | udc_ep_in_req_dma(udc, ep); |
| 2163 | else |
| 2164 | udc_ep_out_req_dma(udc, ep); |
| 2165 | } else |
| 2166 | ep->req_pending = 0; |
| 2167 | |
| 2168 | } |
| 2169 | |
| 2170 | /* |
| 2171 | * |
| 2172 | * Endpoint 0 functions |
| 2173 | * |
| 2174 | */ |
| 2175 | static void udc_handle_dev(struct lpc32xx_udc *udc) |
| 2176 | { |
| 2177 | u32 tmp; |
| 2178 | |
| 2179 | udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT); |
| 2180 | tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT); |
| 2181 | |
| 2182 | if (tmp & DEV_RST) |
| 2183 | uda_usb_reset(udc); |
| 2184 | else if (tmp & DEV_CON_CH) |
| 2185 | uda_power_event(udc, (tmp & DEV_CON)); |
| 2186 | else if (tmp & DEV_SUS_CH) { |
| 2187 | if (tmp & DEV_SUS) { |
| 2188 | if (udc->vbus == 0) |
| 2189 | stop_activity(udc); |
| 2190 | else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && |
| 2191 | udc->driver) { |
| 2192 | /* Power down transceiver */ |
| 2193 | udc->poweron = 0; |
| 2194 | schedule_work(&udc->pullup_job); |
| 2195 | uda_resm_susp_event(udc, 1); |
| 2196 | } |
| 2197 | } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && |
| 2198 | udc->driver && udc->vbus) { |
| 2199 | uda_resm_susp_event(udc, 0); |
| 2200 | /* Power up transceiver */ |
| 2201 | udc->poweron = 1; |
| 2202 | schedule_work(&udc->pullup_job); |
| 2203 | } |
| 2204 | } |
| 2205 | } |
| 2206 | |
| 2207 | static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex) |
| 2208 | { |
| 2209 | struct lpc32xx_ep *ep; |
| 2210 | u32 ep0buff = 0, tmp; |
| 2211 | |
| 2212 | switch (reqtype & USB_RECIP_MASK) { |
| 2213 | case USB_RECIP_INTERFACE: |
| 2214 | break; /* Not supported */ |
| 2215 | |
| 2216 | case USB_RECIP_DEVICE: |
| 2217 | ep0buff = (udc->selfpowered << USB_DEVICE_SELF_POWERED); |
| 2218 | if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP)) |
| 2219 | ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP); |
| 2220 | break; |
| 2221 | |
| 2222 | case USB_RECIP_ENDPOINT: |
| 2223 | tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; |
| 2224 | ep = &udc->ep[tmp]; |
Roland Stigge | 78ca913 | 2012-08-20 10:30:13 +0200 | [diff] [blame] | 2225 | if ((tmp == 0) || (tmp >= NUM_ENDPOINTS)) |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2226 | return -EOPNOTSUPP; |
| 2227 | |
| 2228 | if (wIndex & USB_DIR_IN) { |
| 2229 | if (!ep->is_in) |
| 2230 | return -EOPNOTSUPP; /* Something's wrong */ |
| 2231 | } else if (ep->is_in) |
| 2232 | return -EOPNOTSUPP; /* Not an IN endpoint */ |
| 2233 | |
| 2234 | /* Get status of the endpoint */ |
| 2235 | udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num)); |
| 2236 | tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num)); |
| 2237 | |
| 2238 | if (tmp & EP_SEL_ST) |
| 2239 | ep0buff = (1 << USB_ENDPOINT_HALT); |
| 2240 | else |
| 2241 | ep0buff = 0; |
| 2242 | break; |
| 2243 | |
| 2244 | default: |
| 2245 | break; |
| 2246 | } |
| 2247 | |
| 2248 | /* Return data */ |
| 2249 | udc_write_hwep(udc, EP_IN, &ep0buff, 2); |
| 2250 | |
| 2251 | return 0; |
| 2252 | } |
| 2253 | |
| 2254 | static void udc_handle_ep0_setup(struct lpc32xx_udc *udc) |
| 2255 | { |
| 2256 | struct lpc32xx_ep *ep, *ep0 = &udc->ep[0]; |
| 2257 | struct usb_ctrlrequest ctrlpkt; |
| 2258 | int i, bytes; |
| 2259 | u16 wIndex, wValue, wLength, reqtype, req, tmp; |
| 2260 | |
| 2261 | /* Nuke previous transfers */ |
| 2262 | nuke(ep0, -EPROTO); |
| 2263 | |
| 2264 | /* Get setup packet */ |
| 2265 | bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8); |
| 2266 | if (bytes != 8) { |
| 2267 | ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n", |
| 2268 | bytes); |
| 2269 | return; |
| 2270 | } |
| 2271 | |
| 2272 | /* Native endianness */ |
| 2273 | wIndex = le16_to_cpu(ctrlpkt.wIndex); |
| 2274 | wValue = le16_to_cpu(ctrlpkt.wValue); |
| 2275 | wLength = le16_to_cpu(ctrlpkt.wLength); |
| 2276 | reqtype = le16_to_cpu(ctrlpkt.bRequestType); |
| 2277 | |
| 2278 | /* Set direction of EP0 */ |
| 2279 | if (likely(reqtype & USB_DIR_IN)) |
| 2280 | ep0->is_in = 1; |
| 2281 | else |
| 2282 | ep0->is_in = 0; |
| 2283 | |
| 2284 | /* Handle SETUP packet */ |
| 2285 | req = le16_to_cpu(ctrlpkt.bRequest); |
| 2286 | switch (req) { |
| 2287 | case USB_REQ_CLEAR_FEATURE: |
| 2288 | case USB_REQ_SET_FEATURE: |
| 2289 | switch (reqtype) { |
| 2290 | case (USB_TYPE_STANDARD | USB_RECIP_DEVICE): |
| 2291 | if (wValue != USB_DEVICE_REMOTE_WAKEUP) |
| 2292 | goto stall; /* Nothing else handled */ |
| 2293 | |
| 2294 | /* Tell board about event */ |
| 2295 | if (req == USB_REQ_CLEAR_FEATURE) |
| 2296 | udc->dev_status &= |
| 2297 | ~(1 << USB_DEVICE_REMOTE_WAKEUP); |
| 2298 | else |
| 2299 | udc->dev_status |= |
| 2300 | (1 << USB_DEVICE_REMOTE_WAKEUP); |
| 2301 | uda_remwkp_cgh(udc); |
| 2302 | goto zlp_send; |
| 2303 | |
| 2304 | case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT): |
| 2305 | tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; |
| 2306 | if ((wValue != USB_ENDPOINT_HALT) || |
| 2307 | (tmp >= NUM_ENDPOINTS)) |
| 2308 | break; |
| 2309 | |
| 2310 | /* Find hardware endpoint from logical endpoint */ |
| 2311 | ep = &udc->ep[tmp]; |
| 2312 | tmp = ep->hwep_num; |
| 2313 | if (tmp == 0) |
| 2314 | break; |
| 2315 | |
| 2316 | if (req == USB_REQ_SET_FEATURE) |
| 2317 | udc_stall_hwep(udc, tmp); |
| 2318 | else if (!ep->wedge) |
| 2319 | udc_clrstall_hwep(udc, tmp); |
| 2320 | |
| 2321 | goto zlp_send; |
| 2322 | |
| 2323 | default: |
| 2324 | break; |
| 2325 | } |
| 2326 | |
| 2327 | |
| 2328 | case USB_REQ_SET_ADDRESS: |
| 2329 | if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) { |
| 2330 | udc_set_address(udc, wValue); |
| 2331 | goto zlp_send; |
| 2332 | } |
| 2333 | break; |
| 2334 | |
| 2335 | case USB_REQ_GET_STATUS: |
| 2336 | udc_get_status(udc, reqtype, wIndex); |
| 2337 | return; |
| 2338 | |
| 2339 | default: |
| 2340 | break; /* Let GadgetFS handle the descriptor instead */ |
| 2341 | } |
| 2342 | |
| 2343 | if (likely(udc->driver)) { |
| 2344 | /* device-2-host (IN) or no data setup command, process |
| 2345 | * immediately */ |
| 2346 | spin_unlock(&udc->lock); |
| 2347 | i = udc->driver->setup(&udc->gadget, &ctrlpkt); |
| 2348 | |
| 2349 | spin_lock(&udc->lock); |
| 2350 | if (req == USB_REQ_SET_CONFIGURATION) { |
| 2351 | /* Configuration is set after endpoints are realized */ |
| 2352 | if (wValue) { |
| 2353 | /* Set configuration */ |
| 2354 | udc_set_device_configured(udc); |
| 2355 | |
| 2356 | udc_protocol_cmd_data_w(udc, CMD_SET_MODE, |
| 2357 | DAT_WR_BYTE(AP_CLK | |
| 2358 | INAK_BI | INAK_II)); |
| 2359 | } else { |
| 2360 | /* Clear configuration */ |
| 2361 | udc_set_device_unconfigured(udc); |
| 2362 | |
| 2363 | /* Disable NAK interrupts */ |
| 2364 | udc_protocol_cmd_data_w(udc, CMD_SET_MODE, |
| 2365 | DAT_WR_BYTE(AP_CLK)); |
| 2366 | } |
| 2367 | } |
| 2368 | |
| 2369 | if (i < 0) { |
| 2370 | /* setup processing failed, force stall */ |
Alexandre Pereira da Silva | 0696f92 | 2012-10-15 09:47:36 -0300 | [diff] [blame] | 2371 | dev_dbg(udc->dev, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2372 | "req %02x.%02x protocol STALL; stat %d\n", |
| 2373 | reqtype, req, i); |
| 2374 | udc->ep0state = WAIT_FOR_SETUP; |
| 2375 | goto stall; |
| 2376 | } |
| 2377 | } |
| 2378 | |
| 2379 | if (!ep0->is_in) |
| 2380 | udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */ |
| 2381 | |
| 2382 | return; |
| 2383 | |
| 2384 | stall: |
| 2385 | udc_stall_hwep(udc, EP_IN); |
| 2386 | return; |
| 2387 | |
| 2388 | zlp_send: |
| 2389 | udc_ep0_send_zlp(udc); |
| 2390 | return; |
| 2391 | } |
| 2392 | |
| 2393 | /* IN endpoint 0 transfer */ |
| 2394 | static void udc_handle_ep0_in(struct lpc32xx_udc *udc) |
| 2395 | { |
| 2396 | struct lpc32xx_ep *ep0 = &udc->ep[0]; |
| 2397 | u32 epstatus; |
| 2398 | |
| 2399 | /* Clear EP interrupt */ |
| 2400 | epstatus = udc_clearep_getsts(udc, EP_IN); |
| 2401 | |
| 2402 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES |
| 2403 | ep0->totalints++; |
| 2404 | #endif |
| 2405 | |
| 2406 | /* Stalled? Clear stall and reset buffers */ |
| 2407 | if (epstatus & EP_SEL_ST) { |
| 2408 | udc_clrstall_hwep(udc, EP_IN); |
| 2409 | nuke(ep0, -ECONNABORTED); |
| 2410 | udc->ep0state = WAIT_FOR_SETUP; |
| 2411 | return; |
| 2412 | } |
| 2413 | |
| 2414 | /* Is a buffer available? */ |
| 2415 | if (!(epstatus & EP_SEL_F)) { |
| 2416 | /* Handle based on current state */ |
| 2417 | if (udc->ep0state == DATA_IN) |
| 2418 | udc_ep0_in_req(udc); |
| 2419 | else { |
| 2420 | /* Unknown state for EP0 oe end of DATA IN phase */ |
| 2421 | nuke(ep0, -ECONNABORTED); |
| 2422 | udc->ep0state = WAIT_FOR_SETUP; |
| 2423 | } |
| 2424 | } |
| 2425 | } |
| 2426 | |
| 2427 | /* OUT endpoint 0 transfer */ |
| 2428 | static void udc_handle_ep0_out(struct lpc32xx_udc *udc) |
| 2429 | { |
| 2430 | struct lpc32xx_ep *ep0 = &udc->ep[0]; |
| 2431 | u32 epstatus; |
| 2432 | |
| 2433 | /* Clear EP interrupt */ |
| 2434 | epstatus = udc_clearep_getsts(udc, EP_OUT); |
| 2435 | |
| 2436 | |
| 2437 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES |
| 2438 | ep0->totalints++; |
| 2439 | #endif |
| 2440 | |
| 2441 | /* Stalled? */ |
| 2442 | if (epstatus & EP_SEL_ST) { |
| 2443 | udc_clrstall_hwep(udc, EP_OUT); |
| 2444 | nuke(ep0, -ECONNABORTED); |
| 2445 | udc->ep0state = WAIT_FOR_SETUP; |
| 2446 | return; |
| 2447 | } |
| 2448 | |
| 2449 | /* A NAK may occur if a packet couldn't be received yet */ |
| 2450 | if (epstatus & EP_SEL_EPN) |
| 2451 | return; |
| 2452 | /* Setup packet incoming? */ |
| 2453 | if (epstatus & EP_SEL_STP) { |
| 2454 | nuke(ep0, 0); |
| 2455 | udc->ep0state = WAIT_FOR_SETUP; |
| 2456 | } |
| 2457 | |
| 2458 | /* Data available? */ |
| 2459 | if (epstatus & EP_SEL_F) |
| 2460 | /* Handle based on current state */ |
| 2461 | switch (udc->ep0state) { |
| 2462 | case WAIT_FOR_SETUP: |
| 2463 | udc_handle_ep0_setup(udc); |
| 2464 | break; |
| 2465 | |
| 2466 | case DATA_OUT: |
| 2467 | udc_ep0_out_req(udc); |
| 2468 | break; |
| 2469 | |
| 2470 | default: |
| 2471 | /* Unknown state for EP0 */ |
| 2472 | nuke(ep0, -ECONNABORTED); |
| 2473 | udc->ep0state = WAIT_FOR_SETUP; |
| 2474 | } |
| 2475 | } |
| 2476 | |
| 2477 | /* Must be called without lock */ |
| 2478 | static int lpc32xx_get_frame(struct usb_gadget *gadget) |
| 2479 | { |
| 2480 | int frame; |
| 2481 | unsigned long flags; |
| 2482 | struct lpc32xx_udc *udc = to_udc(gadget); |
| 2483 | |
| 2484 | if (!udc->clocked) |
| 2485 | return -EINVAL; |
| 2486 | |
| 2487 | spin_lock_irqsave(&udc->lock, flags); |
| 2488 | |
| 2489 | frame = (int) udc_get_current_frame(udc); |
| 2490 | |
| 2491 | spin_unlock_irqrestore(&udc->lock, flags); |
| 2492 | |
| 2493 | return frame; |
| 2494 | } |
| 2495 | |
| 2496 | static int lpc32xx_wakeup(struct usb_gadget *gadget) |
| 2497 | { |
| 2498 | return -ENOTSUPP; |
| 2499 | } |
| 2500 | |
| 2501 | static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on) |
| 2502 | { |
| 2503 | struct lpc32xx_udc *udc = to_udc(gadget); |
| 2504 | |
| 2505 | /* Always self-powered */ |
| 2506 | udc->selfpowered = (is_on != 0); |
| 2507 | |
| 2508 | return 0; |
| 2509 | } |
| 2510 | |
| 2511 | /* |
| 2512 | * vbus is here! turn everything on that's ready |
| 2513 | * Must be called without lock |
| 2514 | */ |
| 2515 | static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active) |
| 2516 | { |
| 2517 | unsigned long flags; |
| 2518 | struct lpc32xx_udc *udc = to_udc(gadget); |
| 2519 | |
| 2520 | spin_lock_irqsave(&udc->lock, flags); |
| 2521 | |
| 2522 | /* Doesn't need lock */ |
| 2523 | if (udc->driver) { |
| 2524 | udc_clk_set(udc, 1); |
| 2525 | udc_enable(udc); |
| 2526 | pullup(udc, is_active); |
| 2527 | } else { |
| 2528 | stop_activity(udc); |
| 2529 | pullup(udc, 0); |
| 2530 | |
| 2531 | spin_unlock_irqrestore(&udc->lock, flags); |
| 2532 | /* |
| 2533 | * Wait for all the endpoints to disable, |
| 2534 | * before disabling clocks. Don't wait if |
| 2535 | * endpoints are not enabled. |
| 2536 | */ |
| 2537 | if (atomic_read(&udc->enabled_ep_cnt)) |
| 2538 | wait_event_interruptible(udc->ep_disable_wait_queue, |
| 2539 | (atomic_read(&udc->enabled_ep_cnt) == 0)); |
| 2540 | |
| 2541 | spin_lock_irqsave(&udc->lock, flags); |
| 2542 | |
| 2543 | udc_clk_set(udc, 0); |
| 2544 | } |
| 2545 | |
| 2546 | spin_unlock_irqrestore(&udc->lock, flags); |
| 2547 | |
| 2548 | return 0; |
| 2549 | } |
| 2550 | |
| 2551 | /* Can be called with or without lock */ |
| 2552 | static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on) |
| 2553 | { |
| 2554 | struct lpc32xx_udc *udc = to_udc(gadget); |
| 2555 | |
| 2556 | /* Doesn't need lock */ |
| 2557 | pullup(udc, is_on); |
| 2558 | |
| 2559 | return 0; |
| 2560 | } |
| 2561 | |
Roland Stigge | 252d8ce | 2012-08-20 10:30:12 +0200 | [diff] [blame] | 2562 | static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *); |
| 2563 | static int lpc32xx_stop(struct usb_gadget *, struct usb_gadget_driver *); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2564 | |
| 2565 | static const struct usb_gadget_ops lpc32xx_udc_ops = { |
| 2566 | .get_frame = lpc32xx_get_frame, |
| 2567 | .wakeup = lpc32xx_wakeup, |
| 2568 | .set_selfpowered = lpc32xx_set_selfpowered, |
| 2569 | .vbus_session = lpc32xx_vbus_session, |
| 2570 | .pullup = lpc32xx_pullup, |
Roland Stigge | 252d8ce | 2012-08-20 10:30:12 +0200 | [diff] [blame] | 2571 | .udc_start = lpc32xx_start, |
| 2572 | .udc_stop = lpc32xx_stop, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2573 | }; |
| 2574 | |
| 2575 | static void nop_release(struct device *dev) |
| 2576 | { |
| 2577 | /* nothing to free */ |
| 2578 | } |
| 2579 | |
Roland Stigge | c4846a1 | 2012-08-20 10:30:14 +0200 | [diff] [blame] | 2580 | static const struct lpc32xx_udc controller_template = { |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2581 | .gadget = { |
| 2582 | .ops = &lpc32xx_udc_ops, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2583 | .name = driver_name, |
| 2584 | .dev = { |
| 2585 | .init_name = "gadget", |
| 2586 | .release = nop_release, |
| 2587 | } |
| 2588 | }, |
| 2589 | .ep[0] = { |
| 2590 | .ep = { |
| 2591 | .name = "ep0", |
| 2592 | .ops = &lpc32xx_ep_ops, |
| 2593 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2594 | .maxpacket = 64, |
| 2595 | .hwep_num_base = 0, |
| 2596 | .hwep_num = 0, /* Can be 0 or 1, has special handling */ |
| 2597 | .lep = 0, |
| 2598 | .eptype = EP_CTL_TYPE, |
| 2599 | }, |
| 2600 | .ep[1] = { |
| 2601 | .ep = { |
| 2602 | .name = "ep1-int", |
| 2603 | .ops = &lpc32xx_ep_ops, |
| 2604 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2605 | .maxpacket = 64, |
| 2606 | .hwep_num_base = 2, |
| 2607 | .hwep_num = 0, /* 2 or 3, will be set later */ |
| 2608 | .lep = 1, |
| 2609 | .eptype = EP_INT_TYPE, |
| 2610 | }, |
| 2611 | .ep[2] = { |
| 2612 | .ep = { |
| 2613 | .name = "ep2-bulk", |
| 2614 | .ops = &lpc32xx_ep_ops, |
| 2615 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2616 | .maxpacket = 64, |
| 2617 | .hwep_num_base = 4, |
| 2618 | .hwep_num = 0, /* 4 or 5, will be set later */ |
| 2619 | .lep = 2, |
| 2620 | .eptype = EP_BLK_TYPE, |
| 2621 | }, |
| 2622 | .ep[3] = { |
| 2623 | .ep = { |
| 2624 | .name = "ep3-iso", |
| 2625 | .ops = &lpc32xx_ep_ops, |
| 2626 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2627 | .maxpacket = 1023, |
| 2628 | .hwep_num_base = 6, |
| 2629 | .hwep_num = 0, /* 6 or 7, will be set later */ |
| 2630 | .lep = 3, |
| 2631 | .eptype = EP_ISO_TYPE, |
| 2632 | }, |
| 2633 | .ep[4] = { |
| 2634 | .ep = { |
| 2635 | .name = "ep4-int", |
| 2636 | .ops = &lpc32xx_ep_ops, |
| 2637 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2638 | .maxpacket = 64, |
| 2639 | .hwep_num_base = 8, |
| 2640 | .hwep_num = 0, /* 8 or 9, will be set later */ |
| 2641 | .lep = 4, |
| 2642 | .eptype = EP_INT_TYPE, |
| 2643 | }, |
| 2644 | .ep[5] = { |
| 2645 | .ep = { |
| 2646 | .name = "ep5-bulk", |
| 2647 | .ops = &lpc32xx_ep_ops, |
| 2648 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2649 | .maxpacket = 64, |
| 2650 | .hwep_num_base = 10, |
| 2651 | .hwep_num = 0, /* 10 or 11, will be set later */ |
| 2652 | .lep = 5, |
| 2653 | .eptype = EP_BLK_TYPE, |
| 2654 | }, |
| 2655 | .ep[6] = { |
| 2656 | .ep = { |
| 2657 | .name = "ep6-iso", |
| 2658 | .ops = &lpc32xx_ep_ops, |
| 2659 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2660 | .maxpacket = 1023, |
| 2661 | .hwep_num_base = 12, |
| 2662 | .hwep_num = 0, /* 12 or 13, will be set later */ |
| 2663 | .lep = 6, |
| 2664 | .eptype = EP_ISO_TYPE, |
| 2665 | }, |
| 2666 | .ep[7] = { |
| 2667 | .ep = { |
| 2668 | .name = "ep7-int", |
| 2669 | .ops = &lpc32xx_ep_ops, |
| 2670 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2671 | .maxpacket = 64, |
| 2672 | .hwep_num_base = 14, |
| 2673 | .hwep_num = 0, |
| 2674 | .lep = 7, |
| 2675 | .eptype = EP_INT_TYPE, |
| 2676 | }, |
| 2677 | .ep[8] = { |
| 2678 | .ep = { |
| 2679 | .name = "ep8-bulk", |
| 2680 | .ops = &lpc32xx_ep_ops, |
| 2681 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2682 | .maxpacket = 64, |
| 2683 | .hwep_num_base = 16, |
| 2684 | .hwep_num = 0, |
| 2685 | .lep = 8, |
| 2686 | .eptype = EP_BLK_TYPE, |
| 2687 | }, |
| 2688 | .ep[9] = { |
| 2689 | .ep = { |
| 2690 | .name = "ep9-iso", |
| 2691 | .ops = &lpc32xx_ep_ops, |
| 2692 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2693 | .maxpacket = 1023, |
| 2694 | .hwep_num_base = 18, |
| 2695 | .hwep_num = 0, |
| 2696 | .lep = 9, |
| 2697 | .eptype = EP_ISO_TYPE, |
| 2698 | }, |
| 2699 | .ep[10] = { |
| 2700 | .ep = { |
| 2701 | .name = "ep10-int", |
| 2702 | .ops = &lpc32xx_ep_ops, |
| 2703 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2704 | .maxpacket = 64, |
| 2705 | .hwep_num_base = 20, |
| 2706 | .hwep_num = 0, |
| 2707 | .lep = 10, |
| 2708 | .eptype = EP_INT_TYPE, |
| 2709 | }, |
| 2710 | .ep[11] = { |
| 2711 | .ep = { |
| 2712 | .name = "ep11-bulk", |
| 2713 | .ops = &lpc32xx_ep_ops, |
| 2714 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2715 | .maxpacket = 64, |
| 2716 | .hwep_num_base = 22, |
| 2717 | .hwep_num = 0, |
| 2718 | .lep = 11, |
| 2719 | .eptype = EP_BLK_TYPE, |
| 2720 | }, |
| 2721 | .ep[12] = { |
| 2722 | .ep = { |
| 2723 | .name = "ep12-iso", |
| 2724 | .ops = &lpc32xx_ep_ops, |
| 2725 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2726 | .maxpacket = 1023, |
| 2727 | .hwep_num_base = 24, |
| 2728 | .hwep_num = 0, |
| 2729 | .lep = 12, |
| 2730 | .eptype = EP_ISO_TYPE, |
| 2731 | }, |
| 2732 | .ep[13] = { |
| 2733 | .ep = { |
| 2734 | .name = "ep13-int", |
| 2735 | .ops = &lpc32xx_ep_ops, |
| 2736 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2737 | .maxpacket = 64, |
| 2738 | .hwep_num_base = 26, |
| 2739 | .hwep_num = 0, |
| 2740 | .lep = 13, |
| 2741 | .eptype = EP_INT_TYPE, |
| 2742 | }, |
| 2743 | .ep[14] = { |
| 2744 | .ep = { |
| 2745 | .name = "ep14-bulk", |
| 2746 | .ops = &lpc32xx_ep_ops, |
| 2747 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2748 | .maxpacket = 64, |
| 2749 | .hwep_num_base = 28, |
| 2750 | .hwep_num = 0, |
| 2751 | .lep = 14, |
| 2752 | .eptype = EP_BLK_TYPE, |
| 2753 | }, |
| 2754 | .ep[15] = { |
| 2755 | .ep = { |
| 2756 | .name = "ep15-bulk", |
| 2757 | .ops = &lpc32xx_ep_ops, |
| 2758 | }, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2759 | .maxpacket = 1023, |
| 2760 | .hwep_num_base = 30, |
| 2761 | .hwep_num = 0, |
| 2762 | .lep = 15, |
| 2763 | .eptype = EP_BLK_TYPE, |
| 2764 | }, |
| 2765 | }; |
| 2766 | |
| 2767 | /* ISO and status interrupts */ |
| 2768 | static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc) |
| 2769 | { |
| 2770 | u32 tmp, devstat; |
| 2771 | struct lpc32xx_udc *udc = _udc; |
| 2772 | |
| 2773 | spin_lock(&udc->lock); |
| 2774 | |
| 2775 | /* Read the device status register */ |
| 2776 | devstat = readl(USBD_DEVINTST(udc->udp_baseaddr)); |
| 2777 | |
| 2778 | devstat &= ~USBD_EP_FAST; |
| 2779 | writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr)); |
| 2780 | devstat = devstat & udc->enabled_devints; |
| 2781 | |
| 2782 | /* Device specific handling needed? */ |
| 2783 | if (devstat & USBD_DEV_STAT) |
| 2784 | udc_handle_dev(udc); |
| 2785 | |
| 2786 | /* Start of frame? (devstat & FRAME_INT): |
| 2787 | * The frame interrupt isn't really needed for ISO support, |
| 2788 | * as the driver will queue the necessary packets */ |
| 2789 | |
| 2790 | /* Error? */ |
| 2791 | if (devstat & ERR_INT) { |
| 2792 | /* All types of errors, from cable removal during transfer to |
| 2793 | * misc protocol and bit errors. These are mostly for just info, |
| 2794 | * as the USB hardware will work around these. If these errors |
| 2795 | * happen alot, something is wrong. */ |
| 2796 | udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT); |
| 2797 | tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT); |
| 2798 | dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp); |
| 2799 | } |
| 2800 | |
| 2801 | spin_unlock(&udc->lock); |
| 2802 | |
| 2803 | return IRQ_HANDLED; |
| 2804 | } |
| 2805 | |
| 2806 | /* EP interrupts */ |
| 2807 | static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc) |
| 2808 | { |
| 2809 | u32 tmp; |
| 2810 | struct lpc32xx_udc *udc = _udc; |
| 2811 | |
| 2812 | spin_lock(&udc->lock); |
| 2813 | |
| 2814 | /* Read the device status register */ |
| 2815 | writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr)); |
| 2816 | |
| 2817 | /* Endpoints */ |
| 2818 | tmp = readl(USBD_EPINTST(udc->udp_baseaddr)); |
| 2819 | |
| 2820 | /* Special handling for EP0 */ |
| 2821 | if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { |
| 2822 | /* Handle EP0 IN */ |
| 2823 | if (tmp & (EP_MASK_SEL(0, EP_IN))) |
| 2824 | udc_handle_ep0_in(udc); |
| 2825 | |
| 2826 | /* Handle EP0 OUT */ |
| 2827 | if (tmp & (EP_MASK_SEL(0, EP_OUT))) |
| 2828 | udc_handle_ep0_out(udc); |
| 2829 | } |
| 2830 | |
| 2831 | /* All other EPs */ |
| 2832 | if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { |
| 2833 | int i; |
| 2834 | |
| 2835 | /* Handle other EP interrupts */ |
| 2836 | for (i = 1; i < NUM_ENDPOINTS; i++) { |
| 2837 | if (tmp & (1 << udc->ep[i].hwep_num)) |
| 2838 | udc_handle_eps(udc, &udc->ep[i]); |
| 2839 | } |
| 2840 | } |
| 2841 | |
| 2842 | spin_unlock(&udc->lock); |
| 2843 | |
| 2844 | return IRQ_HANDLED; |
| 2845 | } |
| 2846 | |
| 2847 | static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc) |
| 2848 | { |
| 2849 | struct lpc32xx_udc *udc = _udc; |
| 2850 | |
| 2851 | int i; |
| 2852 | u32 tmp; |
| 2853 | |
| 2854 | spin_lock(&udc->lock); |
| 2855 | |
| 2856 | /* Handle EP DMA EOT interrupts */ |
| 2857 | tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) | |
| 2858 | (readl(USBD_EPDMAST(udc->udp_baseaddr)) & |
| 2859 | readl(USBD_NDDRTINTST(udc->udp_baseaddr))) | |
| 2860 | readl(USBD_SYSERRTINTST(udc->udp_baseaddr)); |
| 2861 | for (i = 1; i < NUM_ENDPOINTS; i++) { |
| 2862 | if (tmp & (1 << udc->ep[i].hwep_num)) |
| 2863 | udc_handle_dma_ep(udc, &udc->ep[i]); |
| 2864 | } |
| 2865 | |
| 2866 | spin_unlock(&udc->lock); |
| 2867 | |
| 2868 | return IRQ_HANDLED; |
| 2869 | } |
| 2870 | |
| 2871 | /* |
| 2872 | * |
| 2873 | * VBUS detection, pullup handler, and Gadget cable state notification |
| 2874 | * |
| 2875 | */ |
| 2876 | static void vbus_work(struct work_struct *work) |
| 2877 | { |
| 2878 | u8 value; |
| 2879 | struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc, |
| 2880 | vbus_job); |
| 2881 | |
| 2882 | if (udc->enabled != 0) { |
| 2883 | /* Discharge VBUS real quick */ |
| 2884 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 2885 | ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); |
| 2886 | |
| 2887 | /* Give VBUS some time (100mS) to discharge */ |
| 2888 | msleep(100); |
| 2889 | |
| 2890 | /* Disable VBUS discharge resistor */ |
| 2891 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 2892 | ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, |
| 2893 | OTG1_VBUS_DISCHRG); |
| 2894 | |
| 2895 | /* Clear interrupt */ |
| 2896 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, |
| 2897 | ISP1301_I2C_INTERRUPT_LATCH | |
| 2898 | ISP1301_I2C_REG_CLEAR_ADDR, ~0); |
| 2899 | |
| 2900 | /* Get the VBUS status from the transceiver */ |
| 2901 | value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client, |
Alexandre Pereira da Silva | 69da85e | 2012-10-15 09:47:35 -0300 | [diff] [blame] | 2902 | ISP1301_I2C_INTERRUPT_SOURCE); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2903 | |
| 2904 | /* VBUS on or off? */ |
Alexandre Pereira da Silva | 69da85e | 2012-10-15 09:47:35 -0300 | [diff] [blame] | 2905 | if (value & INT_SESS_VLD) |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2906 | udc->vbus = 1; |
| 2907 | else |
| 2908 | udc->vbus = 0; |
| 2909 | |
| 2910 | /* VBUS changed? */ |
| 2911 | if (udc->last_vbus != udc->vbus) { |
| 2912 | udc->last_vbus = udc->vbus; |
| 2913 | lpc32xx_vbus_session(&udc->gadget, udc->vbus); |
| 2914 | } |
| 2915 | } |
| 2916 | |
| 2917 | /* Re-enable after completion */ |
| 2918 | enable_irq(udc->udp_irq[IRQ_USB_ATX]); |
| 2919 | } |
| 2920 | |
| 2921 | static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc) |
| 2922 | { |
| 2923 | struct lpc32xx_udc *udc = _udc; |
| 2924 | |
| 2925 | /* Defer handling of VBUS IRQ to work queue */ |
| 2926 | disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]); |
| 2927 | schedule_work(&udc->vbus_job); |
| 2928 | |
| 2929 | return IRQ_HANDLED; |
| 2930 | } |
| 2931 | |
Roland Stigge | 252d8ce | 2012-08-20 10:30:12 +0200 | [diff] [blame] | 2932 | static int lpc32xx_start(struct usb_gadget *gadget, |
| 2933 | struct usb_gadget_driver *driver) |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2934 | { |
Roland Stigge | 252d8ce | 2012-08-20 10:30:12 +0200 | [diff] [blame] | 2935 | struct lpc32xx_udc *udc = to_udc(gadget); |
| 2936 | int i; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2937 | |
Roland Stigge | 252d8ce | 2012-08-20 10:30:12 +0200 | [diff] [blame] | 2938 | if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) { |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2939 | dev_err(udc->dev, "bad parameter.\n"); |
| 2940 | return -EINVAL; |
| 2941 | } |
| 2942 | |
| 2943 | if (udc->driver) { |
| 2944 | dev_err(udc->dev, "UDC already has a gadget driver\n"); |
| 2945 | return -EBUSY; |
| 2946 | } |
| 2947 | |
| 2948 | udc->driver = driver; |
Alexandre Pereira da Silva | eebc0d3 | 2012-06-26 11:27:09 -0300 | [diff] [blame] | 2949 | udc->gadget.dev.of_node = udc->dev->of_node; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2950 | udc->enabled = 1; |
| 2951 | udc->selfpowered = 1; |
| 2952 | udc->vbus = 0; |
| 2953 | |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2954 | /* Force VBUS process once to check for cable insertion */ |
| 2955 | udc->last_vbus = udc->vbus = 0; |
| 2956 | schedule_work(&udc->vbus_job); |
| 2957 | |
| 2958 | /* Do not re-enable ATX IRQ (3) */ |
| 2959 | for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++) |
| 2960 | enable_irq(udc->udp_irq[i]); |
| 2961 | |
| 2962 | return 0; |
| 2963 | } |
| 2964 | |
Roland Stigge | 252d8ce | 2012-08-20 10:30:12 +0200 | [diff] [blame] | 2965 | static int lpc32xx_stop(struct usb_gadget *gadget, |
| 2966 | struct usb_gadget_driver *driver) |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2967 | { |
| 2968 | int i; |
Roland Stigge | 252d8ce | 2012-08-20 10:30:12 +0200 | [diff] [blame] | 2969 | struct lpc32xx_udc *udc = to_udc(gadget); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2970 | |
Roland Stigge | 252d8ce | 2012-08-20 10:30:12 +0200 | [diff] [blame] | 2971 | if (!driver || driver != udc->driver) |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2972 | return -EINVAL; |
| 2973 | |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2974 | for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++) |
| 2975 | disable_irq(udc->udp_irq[i]); |
| 2976 | |
| 2977 | if (udc->clocked) { |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2978 | spin_lock(&udc->lock); |
| 2979 | stop_activity(udc); |
| 2980 | spin_unlock(&udc->lock); |
| 2981 | |
| 2982 | /* |
| 2983 | * Wait for all the endpoints to disable, |
| 2984 | * before disabling clocks. Don't wait if |
| 2985 | * endpoints are not enabled. |
| 2986 | */ |
| 2987 | if (atomic_read(&udc->enabled_ep_cnt)) |
| 2988 | wait_event_interruptible(udc->ep_disable_wait_queue, |
| 2989 | (atomic_read(&udc->enabled_ep_cnt) == 0)); |
| 2990 | |
| 2991 | spin_lock(&udc->lock); |
| 2992 | udc_clk_set(udc, 0); |
| 2993 | spin_unlock(&udc->lock); |
| 2994 | } |
| 2995 | |
| 2996 | udc->enabled = 0; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2997 | udc->driver = NULL; |
| 2998 | |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 2999 | return 0; |
| 3000 | } |
| 3001 | |
| 3002 | static void lpc32xx_udc_shutdown(struct platform_device *dev) |
| 3003 | { |
| 3004 | /* Force disconnect on reboot */ |
Roland Stigge | 252d8ce | 2012-08-20 10:30:12 +0200 | [diff] [blame] | 3005 | struct lpc32xx_udc *udc = platform_get_drvdata(dev); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3006 | |
| 3007 | pullup(udc, 0); |
| 3008 | } |
| 3009 | |
| 3010 | /* |
| 3011 | * Callbacks to be overridden by options passed via OF (TODO) |
| 3012 | */ |
| 3013 | |
| 3014 | static void lpc32xx_usbd_conn_chg(int conn) |
| 3015 | { |
| 3016 | /* Do nothing, it might be nice to enable an LED |
| 3017 | * based on conn state being !0 */ |
| 3018 | } |
| 3019 | |
| 3020 | static void lpc32xx_usbd_susp_chg(int susp) |
| 3021 | { |
| 3022 | /* Device suspend if susp != 0 */ |
| 3023 | } |
| 3024 | |
| 3025 | static void lpc32xx_rmwkup_chg(int remote_wakup_enable) |
| 3026 | { |
| 3027 | /* Enable or disable USB remote wakeup */ |
| 3028 | } |
| 3029 | |
| 3030 | struct lpc32xx_usbd_cfg lpc32xx_usbddata = { |
| 3031 | .vbus_drv_pol = 0, |
| 3032 | .conn_chgb = &lpc32xx_usbd_conn_chg, |
| 3033 | .susp_chgb = &lpc32xx_usbd_susp_chg, |
| 3034 | .rmwk_chgb = &lpc32xx_rmwkup_chg, |
| 3035 | }; |
| 3036 | |
| 3037 | |
| 3038 | static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F; |
| 3039 | |
| 3040 | static int __init lpc32xx_udc_probe(struct platform_device *pdev) |
| 3041 | { |
| 3042 | struct device *dev = &pdev->dev; |
Roland Stigge | c4846a1 | 2012-08-20 10:30:14 +0200 | [diff] [blame] | 3043 | struct lpc32xx_udc *udc; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3044 | int retval, i; |
| 3045 | struct resource *res; |
| 3046 | dma_addr_t dma_handle; |
| 3047 | struct device_node *isp1301_node; |
| 3048 | |
Roland Stigge | c4846a1 | 2012-08-20 10:30:14 +0200 | [diff] [blame] | 3049 | udc = kzalloc(sizeof(*udc), GFP_KERNEL); |
| 3050 | if (!udc) |
| 3051 | return -ENOMEM; |
| 3052 | |
| 3053 | memcpy(udc, &controller_template, sizeof(*udc)); |
| 3054 | for (i = 0; i <= 15; i++) |
| 3055 | udc->ep[i].udc = udc; |
| 3056 | udc->gadget.ep0 = &udc->ep[0].ep; |
| 3057 | |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3058 | /* init software state */ |
| 3059 | udc->gadget.dev.parent = dev; |
| 3060 | udc->pdev = pdev; |
| 3061 | udc->dev = &pdev->dev; |
| 3062 | udc->enabled = 0; |
| 3063 | |
| 3064 | if (pdev->dev.of_node) { |
| 3065 | isp1301_node = of_parse_phandle(pdev->dev.of_node, |
| 3066 | "transceiver", 0); |
| 3067 | } else { |
| 3068 | isp1301_node = NULL; |
| 3069 | } |
| 3070 | |
| 3071 | udc->isp1301_i2c_client = isp1301_get_client(isp1301_node); |
Roland Stigge | c4846a1 | 2012-08-20 10:30:14 +0200 | [diff] [blame] | 3072 | if (!udc->isp1301_i2c_client) { |
| 3073 | retval = -EPROBE_DEFER; |
| 3074 | goto phy_fail; |
| 3075 | } |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3076 | |
| 3077 | dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n", |
| 3078 | udc->isp1301_i2c_client->addr); |
| 3079 | |
| 3080 | pdev->dev.dma_mask = &lpc32xx_usbd_dmamask; |
Russell King | 22d9d8e | 2013-06-10 16:28:49 +0100 | [diff] [blame] | 3081 | retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
| 3082 | if (retval) |
| 3083 | goto resource_fail; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3084 | |
| 3085 | udc->board = &lpc32xx_usbddata; |
| 3086 | |
| 3087 | /* |
| 3088 | * Resources are mapped as follows: |
| 3089 | * IORESOURCE_MEM, base address and size of USB space |
| 3090 | * IORESOURCE_IRQ, USB device low priority interrupt number |
| 3091 | * IORESOURCE_IRQ, USB device high priority interrupt number |
| 3092 | * IORESOURCE_IRQ, USB device interrupt number |
| 3093 | * IORESOURCE_IRQ, USB transceiver interrupt number |
| 3094 | */ |
| 3095 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Roland Stigge | c4846a1 | 2012-08-20 10:30:14 +0200 | [diff] [blame] | 3096 | if (!res) { |
| 3097 | retval = -ENXIO; |
| 3098 | goto resource_fail; |
| 3099 | } |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3100 | |
| 3101 | spin_lock_init(&udc->lock); |
| 3102 | |
| 3103 | /* Get IRQs */ |
| 3104 | for (i = 0; i < 4; i++) { |
| 3105 | udc->udp_irq[i] = platform_get_irq(pdev, i); |
| 3106 | if (udc->udp_irq[i] < 0) { |
| 3107 | dev_err(udc->dev, |
| 3108 | "irq resource %d not available!\n", i); |
Roland Stigge | c4846a1 | 2012-08-20 10:30:14 +0200 | [diff] [blame] | 3109 | retval = udc->udp_irq[i]; |
| 3110 | goto irq_fail; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3111 | } |
| 3112 | } |
| 3113 | |
| 3114 | udc->io_p_start = res->start; |
| 3115 | udc->io_p_size = resource_size(res); |
| 3116 | if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) { |
| 3117 | dev_err(udc->dev, "someone's using UDC memory\n"); |
Roland Stigge | c4846a1 | 2012-08-20 10:30:14 +0200 | [diff] [blame] | 3118 | retval = -EBUSY; |
| 3119 | goto request_mem_region_fail; |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3120 | } |
| 3121 | |
| 3122 | udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size); |
| 3123 | if (!udc->udp_baseaddr) { |
| 3124 | retval = -ENOMEM; |
| 3125 | dev_err(udc->dev, "IO map failure\n"); |
| 3126 | goto io_map_fail; |
| 3127 | } |
| 3128 | |
| 3129 | /* Enable AHB slave USB clock, needed for further USB clock control */ |
| 3130 | writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL); |
| 3131 | |
| 3132 | /* Get required clocks */ |
| 3133 | udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5"); |
| 3134 | if (IS_ERR(udc->usb_pll_clk)) { |
| 3135 | dev_err(udc->dev, "failed to acquire USB PLL\n"); |
| 3136 | retval = PTR_ERR(udc->usb_pll_clk); |
| 3137 | goto pll_get_fail; |
| 3138 | } |
| 3139 | udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd"); |
| 3140 | if (IS_ERR(udc->usb_slv_clk)) { |
| 3141 | dev_err(udc->dev, "failed to acquire USB device clock\n"); |
| 3142 | retval = PTR_ERR(udc->usb_slv_clk); |
| 3143 | goto usb_clk_get_fail; |
| 3144 | } |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 3145 | udc->usb_otg_clk = clk_get(&pdev->dev, "ck_usb_otg"); |
| 3146 | if (IS_ERR(udc->usb_otg_clk)) { |
| 3147 | dev_err(udc->dev, "failed to acquire USB otg clock\n"); |
Julia Lawall | 44fd6c0 | 2012-08-25 21:57:06 +0200 | [diff] [blame] | 3148 | retval = PTR_ERR(udc->usb_otg_clk); |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 3149 | goto usb_otg_clk_get_fail; |
| 3150 | } |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3151 | |
| 3152 | /* Setup PLL clock to 48MHz */ |
| 3153 | retval = clk_enable(udc->usb_pll_clk); |
| 3154 | if (retval < 0) { |
| 3155 | dev_err(udc->dev, "failed to start USB PLL\n"); |
| 3156 | goto pll_enable_fail; |
| 3157 | } |
| 3158 | |
| 3159 | retval = clk_set_rate(udc->usb_pll_clk, 48000); |
| 3160 | if (retval < 0) { |
| 3161 | dev_err(udc->dev, "failed to set USB clock rate\n"); |
| 3162 | goto pll_set_fail; |
| 3163 | } |
| 3164 | |
| 3165 | writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL); |
| 3166 | |
| 3167 | /* Enable USB device clock */ |
| 3168 | retval = clk_enable(udc->usb_slv_clk); |
| 3169 | if (retval < 0) { |
| 3170 | dev_err(udc->dev, "failed to start USB device clock\n"); |
| 3171 | goto usb_clk_enable_fail; |
| 3172 | } |
| 3173 | |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 3174 | /* Enable USB OTG clock */ |
| 3175 | retval = clk_enable(udc->usb_otg_clk); |
| 3176 | if (retval < 0) { |
| 3177 | dev_err(udc->dev, "failed to start USB otg clock\n"); |
| 3178 | goto usb_otg_clk_enable_fail; |
| 3179 | } |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3180 | |
| 3181 | /* Setup deferred workqueue data */ |
| 3182 | udc->poweron = udc->pullup = 0; |
| 3183 | INIT_WORK(&udc->pullup_job, pullup_work); |
| 3184 | INIT_WORK(&udc->vbus_job, vbus_work); |
| 3185 | #ifdef CONFIG_PM |
| 3186 | INIT_WORK(&udc->power_job, power_work); |
| 3187 | #endif |
| 3188 | |
| 3189 | /* All clocks are now on */ |
| 3190 | udc->clocked = 1; |
| 3191 | |
| 3192 | isp1301_udc_configure(udc); |
| 3193 | /* Allocate memory for the UDCA */ |
| 3194 | udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE, |
| 3195 | &dma_handle, |
| 3196 | (GFP_KERNEL | GFP_DMA)); |
| 3197 | if (!udc->udca_v_base) { |
| 3198 | dev_err(udc->dev, "error getting UDCA region\n"); |
| 3199 | retval = -ENOMEM; |
| 3200 | goto i2c_fail; |
| 3201 | } |
| 3202 | udc->udca_p_base = dma_handle; |
| 3203 | dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n", |
| 3204 | UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base); |
| 3205 | |
| 3206 | /* Setup the DD DMA memory pool */ |
| 3207 | udc->dd_cache = dma_pool_create("udc_dd", udc->dev, |
| 3208 | sizeof(struct lpc32xx_usbd_dd_gad), |
| 3209 | sizeof(u32), 0); |
| 3210 | if (!udc->dd_cache) { |
| 3211 | dev_err(udc->dev, "error getting DD DMA region\n"); |
| 3212 | retval = -ENOMEM; |
| 3213 | goto dma_alloc_fail; |
| 3214 | } |
| 3215 | |
| 3216 | /* Clear USB peripheral and initialize gadget endpoints */ |
| 3217 | udc_disable(udc); |
| 3218 | udc_reinit(udc); |
| 3219 | |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3220 | /* Request IRQs - low and high priority USB device IRQs are routed to |
| 3221 | * the same handler, while the DMA interrupt is routed elsewhere */ |
| 3222 | retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq, |
| 3223 | 0, "udc_lp", udc); |
| 3224 | if (retval < 0) { |
| 3225 | dev_err(udc->dev, "LP request irq %d failed\n", |
| 3226 | udc->udp_irq[IRQ_USB_LP]); |
| 3227 | goto irq_lp_fail; |
| 3228 | } |
| 3229 | retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq, |
| 3230 | 0, "udc_hp", udc); |
| 3231 | if (retval < 0) { |
| 3232 | dev_err(udc->dev, "HP request irq %d failed\n", |
| 3233 | udc->udp_irq[IRQ_USB_HP]); |
| 3234 | goto irq_hp_fail; |
| 3235 | } |
| 3236 | |
| 3237 | retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA], |
| 3238 | lpc32xx_usb_devdma_irq, 0, "udc_dma", udc); |
| 3239 | if (retval < 0) { |
| 3240 | dev_err(udc->dev, "DEV request irq %d failed\n", |
| 3241 | udc->udp_irq[IRQ_USB_DEVDMA]); |
| 3242 | goto irq_dev_fail; |
| 3243 | } |
| 3244 | |
| 3245 | /* The transceiver interrupt is used for VBUS detection and will |
| 3246 | kick off the VBUS handler function */ |
| 3247 | retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq, |
| 3248 | 0, "udc_otg", udc); |
| 3249 | if (retval < 0) { |
| 3250 | dev_err(udc->dev, "VBUS request irq %d failed\n", |
| 3251 | udc->udp_irq[IRQ_USB_ATX]); |
| 3252 | goto irq_xcvr_fail; |
| 3253 | } |
| 3254 | |
| 3255 | /* Initialize wait queue */ |
| 3256 | init_waitqueue_head(&udc->ep_disable_wait_queue); |
| 3257 | atomic_set(&udc->enabled_ep_cnt, 0); |
| 3258 | |
| 3259 | /* Keep all IRQs disabled until GadgetFS starts up */ |
| 3260 | for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++) |
| 3261 | disable_irq(udc->udp_irq[i]); |
| 3262 | |
| 3263 | retval = usb_add_gadget_udc(dev, &udc->gadget); |
| 3264 | if (retval < 0) |
| 3265 | goto add_gadget_fail; |
| 3266 | |
| 3267 | dev_set_drvdata(dev, udc); |
| 3268 | device_init_wakeup(dev, 1); |
| 3269 | create_debug_file(udc); |
| 3270 | |
| 3271 | /* Disable clocks for now */ |
| 3272 | udc_clk_set(udc, 0); |
| 3273 | |
| 3274 | dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION); |
| 3275 | return 0; |
| 3276 | |
| 3277 | add_gadget_fail: |
| 3278 | free_irq(udc->udp_irq[IRQ_USB_ATX], udc); |
| 3279 | irq_xcvr_fail: |
| 3280 | free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc); |
| 3281 | irq_dev_fail: |
| 3282 | free_irq(udc->udp_irq[IRQ_USB_HP], udc); |
| 3283 | irq_hp_fail: |
| 3284 | free_irq(udc->udp_irq[IRQ_USB_LP], udc); |
| 3285 | irq_lp_fail: |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3286 | dma_pool_destroy(udc->dd_cache); |
| 3287 | dma_alloc_fail: |
| 3288 | dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, |
| 3289 | udc->udca_v_base, udc->udca_p_base); |
| 3290 | i2c_fail: |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 3291 | clk_disable(udc->usb_otg_clk); |
| 3292 | usb_otg_clk_enable_fail: |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3293 | clk_disable(udc->usb_slv_clk); |
| 3294 | usb_clk_enable_fail: |
| 3295 | pll_set_fail: |
| 3296 | clk_disable(udc->usb_pll_clk); |
| 3297 | pll_enable_fail: |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 3298 | clk_put(udc->usb_otg_clk); |
Felipe Balbi | ade79d1 | 2014-03-10 13:30:53 -0500 | [diff] [blame] | 3299 | usb_otg_clk_get_fail: |
| 3300 | clk_put(udc->usb_slv_clk); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3301 | usb_clk_get_fail: |
| 3302 | clk_put(udc->usb_pll_clk); |
| 3303 | pll_get_fail: |
| 3304 | iounmap(udc->udp_baseaddr); |
| 3305 | io_map_fail: |
| 3306 | release_mem_region(udc->io_p_start, udc->io_p_size); |
| 3307 | dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval); |
Roland Stigge | c4846a1 | 2012-08-20 10:30:14 +0200 | [diff] [blame] | 3308 | request_mem_region_fail: |
| 3309 | irq_fail: |
| 3310 | resource_fail: |
| 3311 | phy_fail: |
| 3312 | kfree(udc); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3313 | return retval; |
| 3314 | } |
| 3315 | |
Bill Pemberton | fb4e98a | 2012-11-19 13:26:20 -0500 | [diff] [blame] | 3316 | static int lpc32xx_udc_remove(struct platform_device *pdev) |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3317 | { |
| 3318 | struct lpc32xx_udc *udc = platform_get_drvdata(pdev); |
| 3319 | |
| 3320 | usb_del_gadget_udc(&udc->gadget); |
| 3321 | if (udc->driver) |
| 3322 | return -EBUSY; |
| 3323 | |
| 3324 | udc_clk_set(udc, 1); |
| 3325 | udc_disable(udc); |
| 3326 | pullup(udc, 0); |
| 3327 | |
| 3328 | free_irq(udc->udp_irq[IRQ_USB_ATX], udc); |
| 3329 | |
| 3330 | device_init_wakeup(&pdev->dev, 0); |
| 3331 | remove_debug_file(udc); |
| 3332 | |
| 3333 | dma_pool_destroy(udc->dd_cache); |
| 3334 | dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, |
| 3335 | udc->udca_v_base, udc->udca_p_base); |
| 3336 | free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc); |
| 3337 | free_irq(udc->udp_irq[IRQ_USB_HP], udc); |
| 3338 | free_irq(udc->udp_irq[IRQ_USB_LP], udc); |
| 3339 | |
Alexandre Pereira da Silva | 5085669 | 2012-06-20 09:03:15 -0300 | [diff] [blame] | 3340 | clk_disable(udc->usb_otg_clk); |
| 3341 | clk_put(udc->usb_otg_clk); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3342 | clk_disable(udc->usb_slv_clk); |
| 3343 | clk_put(udc->usb_slv_clk); |
| 3344 | clk_disable(udc->usb_pll_clk); |
| 3345 | clk_put(udc->usb_pll_clk); |
| 3346 | iounmap(udc->udp_baseaddr); |
| 3347 | release_mem_region(udc->io_p_start, udc->io_p_size); |
Roland Stigge | c4846a1 | 2012-08-20 10:30:14 +0200 | [diff] [blame] | 3348 | kfree(udc); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3349 | |
| 3350 | return 0; |
| 3351 | } |
| 3352 | |
| 3353 | #ifdef CONFIG_PM |
| 3354 | static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg) |
| 3355 | { |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3356 | struct lpc32xx_udc *udc = platform_get_drvdata(pdev); |
| 3357 | |
| 3358 | if (udc->clocked) { |
| 3359 | /* Power down ISP */ |
| 3360 | udc->poweron = 0; |
| 3361 | isp1301_set_powerstate(udc, 0); |
| 3362 | |
| 3363 | /* Disable clocking */ |
| 3364 | udc_clk_set(udc, 0); |
| 3365 | |
| 3366 | /* Keep clock flag on, so we know to re-enable clocks |
| 3367 | on resume */ |
| 3368 | udc->clocked = 1; |
| 3369 | |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3370 | /* Kill global USB clock */ |
| 3371 | clk_disable(udc->usb_slv_clk); |
| 3372 | } |
| 3373 | |
| 3374 | return 0; |
| 3375 | } |
| 3376 | |
| 3377 | static int lpc32xx_udc_resume(struct platform_device *pdev) |
| 3378 | { |
| 3379 | struct lpc32xx_udc *udc = platform_get_drvdata(pdev); |
| 3380 | |
| 3381 | if (udc->clocked) { |
| 3382 | /* Enable global USB clock */ |
| 3383 | clk_enable(udc->usb_slv_clk); |
| 3384 | |
| 3385 | /* Enable clocking */ |
| 3386 | udc_clk_set(udc, 1); |
| 3387 | |
| 3388 | /* ISP back to normal power mode */ |
| 3389 | udc->poweron = 1; |
| 3390 | isp1301_set_powerstate(udc, 1); |
| 3391 | } |
| 3392 | |
| 3393 | return 0; |
| 3394 | } |
| 3395 | #else |
| 3396 | #define lpc32xx_udc_suspend NULL |
| 3397 | #define lpc32xx_udc_resume NULL |
| 3398 | #endif |
| 3399 | |
| 3400 | #ifdef CONFIG_OF |
| 3401 | static struct of_device_id lpc32xx_udc_of_match[] = { |
| 3402 | { .compatible = "nxp,lpc3220-udc", }, |
| 3403 | { }, |
| 3404 | }; |
| 3405 | MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match); |
| 3406 | #endif |
| 3407 | |
| 3408 | static struct platform_driver lpc32xx_udc_driver = { |
Bill Pemberton | 7690417 | 2012-11-19 13:21:08 -0500 | [diff] [blame] | 3409 | .remove = lpc32xx_udc_remove, |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3410 | .shutdown = lpc32xx_udc_shutdown, |
| 3411 | .suspend = lpc32xx_udc_suspend, |
| 3412 | .resume = lpc32xx_udc_resume, |
| 3413 | .driver = { |
| 3414 | .name = (char *) driver_name, |
| 3415 | .owner = THIS_MODULE, |
| 3416 | .of_match_table = of_match_ptr(lpc32xx_udc_of_match), |
| 3417 | }, |
| 3418 | }; |
| 3419 | |
Fabio Porcedda | 52f7a82 | 2013-01-09 12:15:28 +0100 | [diff] [blame] | 3420 | module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe); |
Roland Stigge | 24a28e4 | 2012-04-29 16:47:05 +0200 | [diff] [blame] | 3421 | |
| 3422 | MODULE_DESCRIPTION("LPC32XX udc driver"); |
| 3423 | MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); |
| 3424 | MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); |
| 3425 | MODULE_LICENSE("GPL"); |
| 3426 | MODULE_ALIAS("platform:lpc32xx_udc"); |