Gregory CLEMENT | ab8ba01 | 2012-11-17 15:22:23 +0100 | [diff] [blame] | 1 | Device Tree Clock bindings for cpu clock of Marvell EBU platforms |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible : shall be one of the following: |
| 5 | "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP |
Thomas Petazzoni | ee2d8ea | 2014-07-09 17:45:11 +0200 | [diff] [blame] | 6 | - reg : Address and length of the clock complex register set, followed |
| 7 | by address and length of the PMU DFS registers |
Gregory CLEMENT | ab8ba01 | 2012-11-17 15:22:23 +0100 | [diff] [blame] | 8 | - #clock-cells : should be set to 1. |
| 9 | - clocks : shall be the input parent clock phandle for the clock. |
| 10 | |
| 11 | cpuclk: clock-complex@d0018700 { |
| 12 | #clock-cells = <1>; |
| 13 | compatible = "marvell,armada-xp-cpu-clock"; |
Thomas Petazzoni | ee2d8ea | 2014-07-09 17:45:11 +0200 | [diff] [blame] | 14 | reg = <0xd0018700 0xA0>, <0x1c054 0x10>; |
Gregory CLEMENT | ab8ba01 | 2012-11-17 15:22:23 +0100 | [diff] [blame] | 15 | clocks = <&coreclk 1>; |
| 16 | } |
| 17 | |
| 18 | cpu@0 { |
| 19 | compatible = "marvell,sheeva-v7"; |
| 20 | reg = <0>; |
| 21 | clocks = <&cpuclk 0>; |
| 22 | }; |