SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * linux/arch/arm/mach-at91/clock.c |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 David Brownell |
| 5 | * Copyright (C) 2005 Ivan Kokshaysky |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/fs.h> |
| 17 | #include <linux/debugfs.h> |
| 18 | #include <linux/seq_file.h> |
| 19 | #include <linux/list.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 25 | #include <linux/io.h> |
Jean-Christophe PLAGNIOL-VILLARD | eb5e76f | 2012-03-02 20:44:23 +0800 | [diff] [blame] | 26 | #include <linux/of_address.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 27 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 28 | #include <mach/hardware.h> |
| 29 | #include <mach/at91_pmc.h> |
| 30 | #include <mach/cpu.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 31 | |
Jean-Christophe PLAGNIOL-VILLARD | 0d78171 | 2012-02-05 20:25:32 +0800 | [diff] [blame] | 32 | #include <asm/proc-fns.h> |
| 33 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 34 | #include "clock.h" |
Andrew Victor | 5e38efa | 2009-12-15 21:57:27 +0100 | [diff] [blame] | 35 | #include "generic.h" |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 36 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 37 | void __iomem *at91_pmc_base; |
Joachim Eastwood | f19b797 | 2012-04-07 19:30:22 +0200 | [diff] [blame] | 38 | EXPORT_SYMBOL_GPL(at91_pmc_base); |
Andrew Victor | 55c20c0 | 2006-06-20 19:31:39 +0100 | [diff] [blame] | 39 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 40 | /* |
| 41 | * There's a lot more which can be done with clocks, including cpufreq |
| 42 | * integration, slow clock mode support (for system suspend), letting |
| 43 | * PLLB be used at other rates (on boards that don't need USB), etc. |
| 44 | */ |
| 45 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 46 | #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) |
| 47 | #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) |
| 48 | #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 49 | #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 50 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 51 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 52 | /* |
| 53 | * Chips have some kind of clocks : group them by functionality |
| 54 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 9918cea | 2012-01-26 14:07:09 +0100 | [diff] [blame] | 55 | #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 56 | || cpu_is_at91sam9g45() \ |
| 57 | || cpu_is_at91sam9x5()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 58 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 59 | #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 60 | || cpu_is_at91sam9g45() \ |
Hong Xu | 74db4fb | 2012-04-17 14:26:31 +0800 | [diff] [blame] | 61 | || cpu_is_at91sam9x5() \ |
| 62 | || cpu_is_at91sam9n12()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 63 | |
Nicolas Ferre | eab4170 | 2009-06-26 15:37:00 +0100 | [diff] [blame] | 64 | #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 65 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 66 | #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 67 | || cpu_is_at91sam9g45() \ |
Hong Xu | 74db4fb | 2012-04-17 14:26:31 +0800 | [diff] [blame] | 68 | || cpu_is_at91sam9x5() \ |
| 69 | || cpu_is_at91sam9n12())) |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 70 | |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 71 | #define cpu_has_upll() (cpu_is_at91sam9g45() \ |
| 72 | || cpu_is_at91sam9x5()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 73 | |
| 74 | /* USB host HS & FS */ |
| 75 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) |
| 76 | |
| 77 | /* USB device FS only */ |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 78 | #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 79 | || cpu_is_at91sam9g45() \ |
| 80 | || cpu_is_at91sam9x5())) |
| 81 | |
| 82 | #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ |
Hong Xu | 74db4fb | 2012-04-17 14:26:31 +0800 | [diff] [blame] | 83 | || cpu_is_at91sam9x5() \ |
| 84 | || cpu_is_at91sam9n12()) |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 85 | |
| 86 | #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ |
Hong Xu | 74db4fb | 2012-04-17 14:26:31 +0800 | [diff] [blame] | 87 | || cpu_is_at91sam9x5() \ |
| 88 | || cpu_is_at91sam9n12()) |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 89 | |
Hong Xu | 74db4fb | 2012-04-17 14:26:31 +0800 | [diff] [blame] | 90 | #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ |
| 91 | || cpu_is_at91sam9n12()) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 92 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 93 | static LIST_HEAD(clocks); |
| 94 | static DEFINE_SPINLOCK(clk_lock); |
| 95 | |
| 96 | static u32 at91_pllb_usb_init; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 97 | |
| 98 | /* |
| 99 | * Four primary clock sources: two crystal oscillators (32K, main), and |
| 100 | * two PLLs. PLLA usually runs the master clock; and PLLB must run at |
| 101 | * 48 MHz (unless no USB function clocks are needed). The main clock and |
| 102 | * both PLLs are turned off to run in "slow clock mode" (system suspend). |
| 103 | */ |
| 104 | static struct clk clk32k = { |
| 105 | .name = "clk32k", |
| 106 | .rate_hz = AT91_SLOW_CLOCK, |
| 107 | .users = 1, /* always on */ |
| 108 | .id = 0, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 109 | .type = CLK_TYPE_PRIMARY, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 110 | }; |
| 111 | static struct clk main_clk = { |
| 112 | .name = "main", |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 113 | .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 114 | .id = 1, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 115 | .type = CLK_TYPE_PRIMARY, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 116 | }; |
| 117 | static struct clk plla = { |
| 118 | .name = "plla", |
| 119 | .parent = &main_clk, |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 120 | .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 121 | .id = 2, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 122 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 123 | }; |
| 124 | |
| 125 | static void pllb_mode(struct clk *clk, int is_on) |
| 126 | { |
| 127 | u32 value; |
| 128 | |
| 129 | if (is_on) { |
| 130 | is_on = AT91_PMC_LOCKB; |
| 131 | value = at91_pllb_usb_init; |
| 132 | } else |
| 133 | value = 0; |
| 134 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 135 | // REVISIT: Add work-around for AT91RM9200 Errata #26 ? |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 136 | at91_pmc_write(AT91_CKGR_PLLBR, value); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 137 | |
| 138 | do { |
| 139 | cpu_relax(); |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 140 | } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | static struct clk pllb = { |
| 144 | .name = "pllb", |
| 145 | .parent = &main_clk, |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 146 | .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 147 | .mode = pllb_mode, |
| 148 | .id = 3, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 149 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 150 | }; |
| 151 | |
| 152 | static void pmc_sys_mode(struct clk *clk, int is_on) |
| 153 | { |
| 154 | if (is_on) |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 155 | at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 156 | else |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 157 | at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 158 | } |
| 159 | |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 160 | static void pmc_uckr_mode(struct clk *clk, int is_on) |
| 161 | { |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 162 | unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR); |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 163 | |
| 164 | if (is_on) { |
| 165 | is_on = AT91_PMC_LOCKU; |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 166 | at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 167 | } else |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 168 | at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 169 | |
| 170 | do { |
| 171 | cpu_relax(); |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 172 | } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 173 | } |
| 174 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 175 | /* USB function clocks (PLLB must be 48 MHz) */ |
| 176 | static struct clk udpck = { |
| 177 | .name = "udpck", |
| 178 | .parent = &pllb, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 179 | .mode = pmc_sys_mode, |
| 180 | }; |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 181 | struct clk utmi_clk = { |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 182 | .name = "utmi_clk", |
| 183 | .parent = &main_clk, |
| 184 | .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */ |
| 185 | .mode = pmc_uckr_mode, |
| 186 | .type = CLK_TYPE_PLL, |
| 187 | }; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 188 | static struct clk uhpck = { |
| 189 | .name = "uhpck", |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 190 | /*.parent = ... we choose parent at runtime */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 191 | .mode = pmc_sys_mode, |
| 192 | }; |
| 193 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 194 | |
| 195 | /* |
| 196 | * The master clock is divided from the CPU clock (by 1-4). It's used for |
| 197 | * memory, interfaces to on-chip peripherals, the AIC, and sometimes more |
| 198 | * (e.g baud rate generation). It's sourced from one of the primary clocks. |
| 199 | */ |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 200 | struct clk mck = { |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 201 | .name = "mck", |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 202 | .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 203 | }; |
| 204 | |
| 205 | static void pmc_periph_mode(struct clk *clk, int is_on) |
| 206 | { |
| 207 | if (is_on) |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 208 | at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 209 | else |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 210 | at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 211 | } |
| 212 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 213 | static struct clk __init *at91_css_to_clk(unsigned long css) |
| 214 | { |
| 215 | switch (css) { |
| 216 | case AT91_PMC_CSS_SLOW: |
| 217 | return &clk32k; |
| 218 | case AT91_PMC_CSS_MAIN: |
| 219 | return &main_clk; |
| 220 | case AT91_PMC_CSS_PLLA: |
| 221 | return &plla; |
| 222 | case AT91_PMC_CSS_PLLB: |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 223 | if (cpu_has_upll()) |
| 224 | /* CSS_PLLB == CSS_UPLL */ |
| 225 | return &utmi_clk; |
| 226 | else if (cpu_has_pllb()) |
| 227 | return &pllb; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 228 | break; |
| 229 | /* alternate PMC: can use master clock */ |
| 230 | case AT91_PMC_CSS_MASTER: |
| 231 | return &mck; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 232 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 233 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 234 | return NULL; |
| 235 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 236 | |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 237 | static int pmc_prescaler_divider(u32 reg) |
| 238 | { |
| 239 | if (cpu_has_alt_prescaler()) { |
| 240 | return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET); |
| 241 | } else { |
| 242 | return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET); |
| 243 | } |
| 244 | } |
| 245 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 246 | static void __clk_enable(struct clk *clk) |
| 247 | { |
| 248 | if (clk->parent) |
| 249 | __clk_enable(clk->parent); |
| 250 | if (clk->users++ == 0 && clk->mode) |
| 251 | clk->mode(clk, 1); |
| 252 | } |
| 253 | |
| 254 | int clk_enable(struct clk *clk) |
| 255 | { |
| 256 | unsigned long flags; |
| 257 | |
| 258 | spin_lock_irqsave(&clk_lock, flags); |
| 259 | __clk_enable(clk); |
| 260 | spin_unlock_irqrestore(&clk_lock, flags); |
| 261 | return 0; |
| 262 | } |
| 263 | EXPORT_SYMBOL(clk_enable); |
| 264 | |
| 265 | static void __clk_disable(struct clk *clk) |
| 266 | { |
| 267 | BUG_ON(clk->users == 0); |
| 268 | if (--clk->users == 0 && clk->mode) |
| 269 | clk->mode(clk, 0); |
| 270 | if (clk->parent) |
| 271 | __clk_disable(clk->parent); |
| 272 | } |
| 273 | |
| 274 | void clk_disable(struct clk *clk) |
| 275 | { |
| 276 | unsigned long flags; |
| 277 | |
| 278 | spin_lock_irqsave(&clk_lock, flags); |
| 279 | __clk_disable(clk); |
| 280 | spin_unlock_irqrestore(&clk_lock, flags); |
| 281 | } |
| 282 | EXPORT_SYMBOL(clk_disable); |
| 283 | |
| 284 | unsigned long clk_get_rate(struct clk *clk) |
| 285 | { |
| 286 | unsigned long flags; |
| 287 | unsigned long rate; |
| 288 | |
| 289 | spin_lock_irqsave(&clk_lock, flags); |
| 290 | for (;;) { |
| 291 | rate = clk->rate_hz; |
| 292 | if (rate || !clk->parent) |
| 293 | break; |
| 294 | clk = clk->parent; |
| 295 | } |
| 296 | spin_unlock_irqrestore(&clk_lock, flags); |
| 297 | return rate; |
| 298 | } |
| 299 | EXPORT_SYMBOL(clk_get_rate); |
| 300 | |
| 301 | /*------------------------------------------------------------------------*/ |
| 302 | |
| 303 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
| 304 | |
| 305 | /* |
| 306 | * For now, only the programmable clocks support reparenting (MCK could |
| 307 | * do this too, with care) or rate changing (the PLLs could do this too, |
| 308 | * ditto MCK but that's more for cpufreq). Drivers may reparent to get |
| 309 | * a better rate match; we don't. |
| 310 | */ |
| 311 | |
| 312 | long clk_round_rate(struct clk *clk, unsigned long rate) |
| 313 | { |
| 314 | unsigned long flags; |
| 315 | unsigned prescale; |
| 316 | unsigned long actual; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 317 | unsigned long prev = ULONG_MAX; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 318 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 319 | if (!clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 320 | return -EINVAL; |
| 321 | spin_lock_irqsave(&clk_lock, flags); |
| 322 | |
| 323 | actual = clk->parent->rate_hz; |
| 324 | for (prescale = 0; prescale < 7; prescale++) { |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 325 | if (actual > rate) |
| 326 | prev = actual; |
| 327 | |
| 328 | if (actual && actual <= rate) { |
| 329 | if ((prev - rate) < (rate - actual)) { |
| 330 | actual = prev; |
| 331 | prescale--; |
| 332 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 333 | break; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 334 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 335 | actual >>= 1; |
| 336 | } |
| 337 | |
| 338 | spin_unlock_irqrestore(&clk_lock, flags); |
| 339 | return (prescale < 7) ? actual : -ENOENT; |
| 340 | } |
| 341 | EXPORT_SYMBOL(clk_round_rate); |
| 342 | |
| 343 | int clk_set_rate(struct clk *clk, unsigned long rate) |
| 344 | { |
| 345 | unsigned long flags; |
| 346 | unsigned prescale; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 347 | unsigned long prescale_offset, css_mask; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 348 | unsigned long actual; |
| 349 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 350 | if (!clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 351 | return -EINVAL; |
| 352 | if (clk->users) |
| 353 | return -EBUSY; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 354 | |
| 355 | if (cpu_has_alt_prescaler()) { |
| 356 | prescale_offset = PMC_ALT_PRES_OFFSET; |
| 357 | css_mask = AT91_PMC_ALT_PCKR_CSS; |
| 358 | } else { |
| 359 | prescale_offset = PMC_PRES_OFFSET; |
| 360 | css_mask = AT91_PMC_CSS; |
| 361 | } |
| 362 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 363 | spin_lock_irqsave(&clk_lock, flags); |
| 364 | |
| 365 | actual = clk->parent->rate_hz; |
| 366 | for (prescale = 0; prescale < 7; prescale++) { |
| 367 | if (actual && actual <= rate) { |
| 368 | u32 pckr; |
| 369 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 370 | pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id)); |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 371 | pckr &= css_mask; /* keep clock selection */ |
| 372 | pckr |= prescale << prescale_offset; |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 373 | at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 374 | clk->rate_hz = actual; |
| 375 | break; |
| 376 | } |
| 377 | actual >>= 1; |
| 378 | } |
| 379 | |
| 380 | spin_unlock_irqrestore(&clk_lock, flags); |
| 381 | return (prescale < 7) ? actual : -ENOENT; |
| 382 | } |
| 383 | EXPORT_SYMBOL(clk_set_rate); |
| 384 | |
| 385 | struct clk *clk_get_parent(struct clk *clk) |
| 386 | { |
| 387 | return clk->parent; |
| 388 | } |
| 389 | EXPORT_SYMBOL(clk_get_parent); |
| 390 | |
| 391 | int clk_set_parent(struct clk *clk, struct clk *parent) |
| 392 | { |
| 393 | unsigned long flags; |
| 394 | |
| 395 | if (clk->users) |
| 396 | return -EBUSY; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 397 | if (!clk_is_primary(parent) || !clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 398 | return -EINVAL; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 399 | |
| 400 | if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB) |
| 401 | return -EINVAL; |
| 402 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 403 | spin_lock_irqsave(&clk_lock, flags); |
| 404 | |
| 405 | clk->rate_hz = parent->rate_hz; |
| 406 | clk->parent = parent; |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 407 | at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 408 | |
| 409 | spin_unlock_irqrestore(&clk_lock, flags); |
| 410 | return 0; |
| 411 | } |
| 412 | EXPORT_SYMBOL(clk_set_parent); |
| 413 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 414 | /* establish PCK0..PCKN parentage and rate */ |
David Brownell | 72e7ae8 | 2008-02-06 22:03:42 +0100 | [diff] [blame] | 415 | static void __init init_programmable_clock(struct clk *clk) |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 416 | { |
| 417 | struct clk *parent; |
| 418 | u32 pckr; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 419 | unsigned int css_mask; |
| 420 | |
| 421 | if (cpu_has_alt_prescaler()) |
| 422 | css_mask = AT91_PMC_ALT_PCKR_CSS; |
| 423 | else |
| 424 | css_mask = AT91_PMC_CSS; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 425 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 426 | pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id)); |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 427 | parent = at91_css_to_clk(pckr & css_mask); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 428 | clk->parent = parent; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 429 | clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 430 | } |
| 431 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 432 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ |
| 433 | |
| 434 | /*------------------------------------------------------------------------*/ |
| 435 | |
| 436 | #ifdef CONFIG_DEBUG_FS |
| 437 | |
| 438 | static int at91_clk_show(struct seq_file *s, void *unused) |
| 439 | { |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 440 | u32 scsr, pcsr, uckr = 0, sr; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 441 | struct clk *clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 442 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 443 | scsr = at91_pmc_read(AT91_PMC_SCSR); |
| 444 | pcsr = at91_pmc_read(AT91_PMC_PCSR); |
| 445 | sr = at91_pmc_read(AT91_PMC_SR); |
Nicolas Ferre | 940192e | 2012-02-23 09:44:37 +0100 | [diff] [blame] | 446 | seq_printf(s, "SCSR = %8x\n", scsr); |
| 447 | seq_printf(s, "PCSR = %8x\n", pcsr); |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 448 | seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); |
| 449 | seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); |
| 450 | seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 451 | if (cpu_has_pllb()) |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 452 | seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR)); |
Nicolas Ferre | 940192e | 2012-02-23 09:44:37 +0100 | [diff] [blame] | 453 | if (cpu_has_utmi()) { |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 454 | uckr = at91_pmc_read(AT91_CKGR_UCKR); |
Nicolas Ferre | 940192e | 2012-02-23 09:44:37 +0100 | [diff] [blame] | 455 | seq_printf(s, "UCKR = %8x\n", uckr); |
| 456 | } |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 457 | seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 458 | if (cpu_has_upll()) |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 459 | seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB)); |
Nicolas Ferre | 940192e | 2012-02-23 09:44:37 +0100 | [diff] [blame] | 460 | seq_printf(s, "SR = %8x\n", sr); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 461 | |
| 462 | seq_printf(s, "\n"); |
| 463 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 464 | list_for_each_entry(clk, &clocks, node) { |
| 465 | char *state; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 466 | |
| 467 | if (clk->mode == pmc_sys_mode) |
| 468 | state = (scsr & clk->pmc_mask) ? "on" : "off"; |
| 469 | else if (clk->mode == pmc_periph_mode) |
| 470 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 471 | else if (clk->mode == pmc_uckr_mode) |
| 472 | state = (uckr & clk->pmc_mask) ? "on" : "off"; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 473 | else if (clk->pmc_mask) |
| 474 | state = (sr & clk->pmc_mask) ? "on" : "off"; |
| 475 | else if (clk == &clk32k || clk == &main_clk) |
| 476 | state = "on"; |
| 477 | else |
| 478 | state = ""; |
| 479 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 480 | seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 481 | clk->name, clk->users, state, clk_get_rate(clk), |
| 482 | clk->parent ? clk->parent->name : ""); |
| 483 | } |
| 484 | return 0; |
| 485 | } |
| 486 | |
| 487 | static int at91_clk_open(struct inode *inode, struct file *file) |
| 488 | { |
| 489 | return single_open(file, at91_clk_show, NULL); |
| 490 | } |
| 491 | |
Arjan van de Ven | 5dfe4c9 | 2007-02-12 00:55:31 -0800 | [diff] [blame] | 492 | static const struct file_operations at91_clk_operations = { |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 493 | .open = at91_clk_open, |
| 494 | .read = seq_read, |
| 495 | .llseek = seq_lseek, |
| 496 | .release = single_release, |
| 497 | }; |
| 498 | |
| 499 | static int __init at91_clk_debugfs_init(void) |
| 500 | { |
| 501 | /* /sys/kernel/debug/at91_clk */ |
| 502 | (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations); |
| 503 | |
| 504 | return 0; |
| 505 | } |
| 506 | postcore_initcall(at91_clk_debugfs_init); |
| 507 | |
| 508 | #endif |
| 509 | |
| 510 | /*------------------------------------------------------------------------*/ |
| 511 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 512 | /* Register a new clock */ |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 513 | static void __init at91_clk_add(struct clk *clk) |
| 514 | { |
| 515 | list_add_tail(&clk->node, &clocks); |
| 516 | |
| 517 | clk->cl.con_id = clk->name; |
| 518 | clk->cl.clk = clk; |
| 519 | clkdev_add(&clk->cl); |
| 520 | } |
| 521 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 522 | int __init clk_register(struct clk *clk) |
| 523 | { |
| 524 | if (clk_is_peripheral(clk)) { |
Nicolas Ferre | 5afddee | 2010-09-09 19:58:23 +0200 | [diff] [blame] | 525 | if (!clk->parent) |
| 526 | clk->parent = &mck; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 527 | clk->mode = pmc_periph_mode; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 528 | } |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 529 | else if (clk_is_sys(clk)) { |
| 530 | clk->parent = &mck; |
| 531 | clk->mode = pmc_sys_mode; |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 532 | } |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 533 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
| 534 | else if (clk_is_programmable(clk)) { |
| 535 | clk->mode = pmc_sys_mode; |
| 536 | init_programmable_clock(clk); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 537 | } |
| 538 | #endif |
| 539 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 540 | at91_clk_add(clk); |
| 541 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 542 | return 0; |
| 543 | } |
| 544 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 545 | /*------------------------------------------------------------------------*/ |
| 546 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 547 | static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) |
| 548 | { |
| 549 | unsigned mul, div; |
| 550 | |
| 551 | div = reg & 0xff; |
| 552 | mul = (reg >> 16) & 0x7ff; |
| 553 | if (div && mul) { |
| 554 | freq /= div; |
| 555 | freq *= mul + 1; |
| 556 | } else |
| 557 | freq = 0; |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 558 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 559 | return freq; |
| 560 | } |
| 561 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 562 | static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg) |
| 563 | { |
| 564 | if (pll == &pllb && (reg & AT91_PMC_USB96M)) |
| 565 | return freq / 2; |
| 566 | else |
| 567 | return freq; |
| 568 | } |
| 569 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 570 | static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) |
| 571 | { |
| 572 | unsigned i, div = 0, mul = 0, diff = 1 << 30; |
| 573 | unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; |
| 574 | |
| 575 | /* PLL output max 240 MHz (or 180 MHz per errata) */ |
| 576 | if (out_freq > 240000000) |
| 577 | goto fail; |
| 578 | |
| 579 | for (i = 1; i < 256; i++) { |
| 580 | int diff1; |
| 581 | unsigned input, mul1; |
| 582 | |
| 583 | /* |
| 584 | * PLL input between 1MHz and 32MHz per spec, but lower |
| 585 | * frequences seem necessary in some cases so allow 100K. |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 586 | * Warning: some newer products need 2MHz min. |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 587 | */ |
| 588 | input = main_freq / i; |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 589 | if (cpu_is_at91sam9g20() && input < 2000000) |
| 590 | continue; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 591 | if (input < 100000) |
| 592 | continue; |
| 593 | if (input > 32000000) |
| 594 | continue; |
| 595 | |
| 596 | mul1 = out_freq / input; |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 597 | if (cpu_is_at91sam9g20() && mul > 63) |
| 598 | continue; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 599 | if (mul1 > 2048) |
| 600 | continue; |
| 601 | if (mul1 < 2) |
| 602 | goto fail; |
| 603 | |
| 604 | diff1 = out_freq - input * mul1; |
| 605 | if (diff1 < 0) |
| 606 | diff1 = -diff1; |
| 607 | if (diff > diff1) { |
| 608 | diff = diff1; |
| 609 | div = i; |
| 610 | mul = mul1; |
| 611 | if (diff == 0) |
| 612 | break; |
| 613 | } |
| 614 | } |
| 615 | if (i == 256 && diff > (out_freq >> 5)) |
| 616 | goto fail; |
| 617 | return ret | ((mul - 1) << 16) | div; |
| 618 | fail: |
| 619 | return 0; |
| 620 | } |
| 621 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 622 | static struct clk *const standard_pmc_clocks[] __initdata = { |
| 623 | /* four primary clocks */ |
| 624 | &clk32k, |
| 625 | &main_clk, |
| 626 | &plla, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 627 | |
| 628 | /* MCK */ |
| 629 | &mck |
| 630 | }; |
| 631 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 632 | /* PLLB generated USB full speed clock init */ |
| 633 | static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) |
| 634 | { |
| 635 | /* |
| 636 | * USB clock init: choose 48 MHz PLLB value, |
| 637 | * disable 48MHz clock during usb peripheral suspend. |
| 638 | * |
| 639 | * REVISIT: assumes MCK doesn't derive from PLLB! |
| 640 | */ |
| 641 | uhpck.parent = &pllb; |
| 642 | |
| 643 | at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; |
| 644 | pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); |
| 645 | if (cpu_is_at91rm9200()) { |
| 646 | uhpck.pmc_mask = AT91RM9200_PMC_UHP; |
| 647 | udpck.pmc_mask = AT91RM9200_PMC_UDP; |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 648 | at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); |
Nicolas Ferre | eab4170 | 2009-06-26 15:37:00 +0100 | [diff] [blame] | 649 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || |
| 650 | cpu_is_at91sam9263() || cpu_is_at91sam9g20() || |
Jean-Christophe PLAGNIOL-VILLARD | 7a2207a | 2011-05-17 20:51:14 +0800 | [diff] [blame] | 651 | cpu_is_at91sam9g10()) { |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 652 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
| 653 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 654 | } |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 655 | at91_pmc_write(AT91_CKGR_PLLBR, 0); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 656 | |
| 657 | udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 658 | uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 659 | } |
| 660 | |
| 661 | /* UPLL generated USB full speed clock init */ |
| 662 | static void __init at91_upll_usbfs_clock_init(unsigned long main_clock) |
| 663 | { |
| 664 | /* |
| 665 | * USB clock init: choose 480 MHz from UPLL, |
| 666 | */ |
| 667 | unsigned int usbr = AT91_PMC_USBS_UPLL; |
| 668 | |
| 669 | /* Setup divider by 10 to reach 48 MHz */ |
| 670 | usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; |
| 671 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 672 | at91_pmc_write(AT91_PMC_USB, usbr); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 673 | |
| 674 | /* Now set uhpck values */ |
| 675 | uhpck.parent = &utmi_clk; |
| 676 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
Ryan Mallon | 8251544 | 2010-06-02 12:55:36 +1200 | [diff] [blame] | 677 | uhpck.rate_hz = utmi_clk.rate_hz; |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 678 | uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 679 | } |
| 680 | |
Jean-Christophe PLAGNIOL-VILLARD | eb5e76f | 2012-03-02 20:44:23 +0800 | [diff] [blame] | 681 | static int __init at91_pmc_init(unsigned long main_clock) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 682 | { |
| 683 | unsigned tmp, freq, mckr; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 684 | int i; |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 685 | int pll_overclock = false; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 686 | |
| 687 | /* |
| 688 | * When the bootloader initialized the main oscillator correctly, |
| 689 | * there's no problem using the cycle counter. But if it didn't, |
| 690 | * or when using oscillator bypass mode, we must be told the speed |
| 691 | * of the main clock. |
| 692 | */ |
| 693 | if (!main_clock) { |
| 694 | do { |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 695 | tmp = at91_pmc_read(AT91_CKGR_MCFR); |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 696 | } while (!(tmp & AT91_PMC_MAINRDY)); |
| 697 | main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 698 | } |
| 699 | main_clk.rate_hz = main_clock; |
| 700 | |
| 701 | /* report if PLLA is more than mildly overclocked */ |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 702 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 703 | if (cpu_has_300M_plla()) { |
| 704 | if (plla.rate_hz > 300000000) |
| 705 | pll_overclock = true; |
| 706 | } else if (cpu_has_800M_plla()) { |
| 707 | if (plla.rate_hz > 800000000) |
| 708 | pll_overclock = true; |
| 709 | } else { |
| 710 | if (plla.rate_hz > 209000000) |
| 711 | pll_overclock = true; |
| 712 | } |
| 713 | if (pll_overclock) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 714 | pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); |
| 715 | |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 716 | if (cpu_has_plladiv2()) { |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 717 | mckr = at91_pmc_read(AT91_PMC_MCKR); |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 718 | plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */ |
| 719 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 720 | |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 721 | if (!cpu_has_pllb() && cpu_has_upll()) { |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 722 | /* setup UTMI clock as the fourth primary clock |
| 723 | * (instead of pllb) */ |
| 724 | utmi_clk.type |= CLK_TYPE_PRIMARY; |
| 725 | utmi_clk.id = 3; |
| 726 | } |
| 727 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 728 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 729 | /* |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 730 | * USB HS clock init |
| 731 | */ |
Andrew Victor | 5e38efa | 2009-12-15 21:57:27 +0100 | [diff] [blame] | 732 | if (cpu_has_utmi()) { |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 733 | /* |
| 734 | * multiplier is hard-wired to 40 |
| 735 | * (obtain the USB High Speed 480 MHz when input is 12 MHz) |
| 736 | */ |
| 737 | utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 738 | |
| 739 | /* UTMI bias and PLL are managed at the same time */ |
| 740 | if (cpu_has_upll()) |
| 741 | utmi_clk.pmc_mask |= AT91_PMC_BIASEN; |
Andrew Victor | 5e38efa | 2009-12-15 21:57:27 +0100 | [diff] [blame] | 742 | } |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 743 | |
| 744 | /* |
| 745 | * USB FS clock init |
| 746 | */ |
| 747 | if (cpu_has_pllb()) |
| 748 | at91_pllb_usbfs_clock_init(main_clock); |
| 749 | if (cpu_has_upll()) |
| 750 | /* assumes that we choose UPLL for USB and not PLLA */ |
| 751 | at91_upll_usbfs_clock_init(main_clock); |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 752 | |
| 753 | /* |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 754 | * MCK and CPU derive from one of those primary clocks. |
| 755 | * For now, assume this parentage won't change. |
| 756 | */ |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 757 | mckr = at91_pmc_read(AT91_PMC_MCKR); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 758 | mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 759 | freq = mck.parent->rate_hz; |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 760 | freq /= pmc_prescaler_divider(mckr); /* prescale */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 761 | if (cpu_is_at91rm9200()) { |
Andrew Victor | a95c729 | 2007-11-19 11:52:09 +0100 | [diff] [blame] | 762 | mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 763 | } else if (cpu_is_at91sam9g20()) { |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 764 | mck.rate_hz = (mckr & AT91_PMC_MDIV) ? |
| 765 | freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ |
| 766 | if (mckr & AT91_PMC_PDIV) |
| 767 | freq /= 2; /* processor clock division */ |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 768 | } else if (cpu_has_mdiv3()) { |
Nicolas Ferre | 2ef9df7 | 2009-06-26 15:36:57 +0100 | [diff] [blame] | 769 | mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? |
| 770 | freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 771 | } else { |
Andrew Victor | 5e38efa | 2009-12-15 21:57:27 +0100 | [diff] [blame] | 772 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 773 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 774 | |
Nicolas Ferre | 1112872 | 2011-03-10 19:08:54 +0100 | [diff] [blame] | 775 | if (cpu_has_alt_prescaler()) { |
| 776 | /* Programmable clocks can use MCK */ |
| 777 | mck.type |= CLK_TYPE_PRIMARY; |
| 778 | mck.id = 4; |
| 779 | } |
| 780 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 781 | /* Register the PMC's standard clocks */ |
| 782 | for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 783 | at91_clk_add(standard_pmc_clocks[i]); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 784 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 785 | if (cpu_has_pllb()) |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 786 | at91_clk_add(&pllb); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 787 | |
| 788 | if (cpu_has_uhp()) |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 789 | at91_clk_add(&uhpck); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 790 | |
| 791 | if (cpu_has_udpfs()) |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 792 | at91_clk_add(&udpck); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 793 | |
| 794 | if (cpu_has_utmi()) |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 795 | at91_clk_add(&utmi_clk); |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 796 | |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 797 | /* MCK and CPU clock are "always on" */ |
| 798 | clk_enable(&mck); |
| 799 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 800 | printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", |
| 801 | freq / 1000000, (unsigned) mck.rate_hz / 1000000, |
| 802 | (unsigned) main_clock / 1000000, |
| 803 | ((unsigned) main_clock % 1000000) / 1000); |
| 804 | |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 805 | return 0; |
| 806 | } |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 807 | |
Jean-Christophe PLAGNIOL-VILLARD | eb5e76f | 2012-03-02 20:44:23 +0800 | [diff] [blame] | 808 | #if defined(CONFIG_OF) |
| 809 | static struct of_device_id pmc_ids[] = { |
| 810 | { .compatible = "atmel,at91rm9200-pmc" }, |
| 811 | { /*sentinel*/ } |
| 812 | }; |
| 813 | |
| 814 | static struct of_device_id osc_ids[] = { |
| 815 | { .compatible = "atmel,osc" }, |
| 816 | { /*sentinel*/ } |
| 817 | }; |
| 818 | |
| 819 | int __init at91_dt_clock_init(void) |
| 820 | { |
| 821 | struct device_node *np; |
| 822 | u32 main_clock = 0; |
| 823 | |
| 824 | np = of_find_matching_node(NULL, pmc_ids); |
| 825 | if (!np) |
| 826 | panic("unable to find compatible pmc node in dtb\n"); |
| 827 | |
| 828 | at91_pmc_base = of_iomap(np, 0); |
| 829 | if (!at91_pmc_base) |
| 830 | panic("unable to map pmc cpu registers\n"); |
| 831 | |
| 832 | of_node_put(np); |
| 833 | |
| 834 | /* retrieve the freqency of fixed clocks from device tree */ |
| 835 | np = of_find_matching_node(NULL, osc_ids); |
| 836 | if (np) { |
| 837 | u32 rate; |
| 838 | if (!of_property_read_u32(np, "clock-frequency", &rate)) |
| 839 | main_clock = rate; |
| 840 | } |
| 841 | |
| 842 | of_node_put(np); |
| 843 | |
| 844 | return at91_pmc_init(main_clock); |
| 845 | } |
| 846 | #endif |
| 847 | |
| 848 | int __init at91_clock_init(unsigned long main_clock) |
| 849 | { |
| 850 | at91_pmc_base = ioremap(AT91_PMC, 256); |
| 851 | if (!at91_pmc_base) |
| 852 | panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC); |
| 853 | |
| 854 | return at91_pmc_init(main_clock); |
| 855 | } |
| 856 | |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 857 | /* |
| 858 | * Several unused clocks may be active. Turn them off. |
| 859 | */ |
| 860 | static int __init at91_clock_reset(void) |
| 861 | { |
| 862 | unsigned long pcdr = 0; |
| 863 | unsigned long scdr = 0; |
| 864 | struct clk *clk; |
| 865 | |
| 866 | list_for_each_entry(clk, &clocks, node) { |
| 867 | if (clk->users > 0) |
| 868 | continue; |
| 869 | |
| 870 | if (clk->mode == pmc_periph_mode) |
| 871 | pcdr |= clk->pmc_mask; |
| 872 | |
| 873 | if (clk->mode == pmc_sys_mode) |
| 874 | scdr |= clk->pmc_mask; |
| 875 | |
| 876 | pr_debug("Clocks: disable unused %s\n", clk->name); |
| 877 | } |
| 878 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 879 | at91_pmc_write(AT91_PMC_PCDR, pcdr); |
| 880 | at91_pmc_write(AT91_PMC_SCDR, scdr); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 881 | |
| 882 | return 0; |
| 883 | } |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 884 | late_initcall(at91_clock_reset); |
Jean-Christophe PLAGNIOL-VILLARD | 0d78171 | 2012-02-05 20:25:32 +0800 | [diff] [blame] | 885 | |
| 886 | void at91sam9_idle(void) |
| 887 | { |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 888 | at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK); |
Jean-Christophe PLAGNIOL-VILLARD | 0d78171 | 2012-02-05 20:25:32 +0800 | [diff] [blame] | 889 | cpu_do_idle(); |
| 890 | } |