blob: 0c2ba03a1d49bdec157f2ac8d41e17eade883043 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * include/asm-ppc/ibm44x.h
3 *
4 * PPC44x definitions
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 *
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_IBM44x_H__
18#define __ASM_IBM44x_H__
19
20#include <linux/config.h>
21
22#ifndef NR_BOARD_IRQS
23#define NR_BOARD_IRQS 0
24#endif
25
26#define _IO_BASE isa_io_base
27#define _ISA_MEM_BASE isa_mem_base
28#define PCI_DRAM_OFFSET pci_dram_offset
29
30/* TLB entry offset/size used for pinning kernel lowmem */
31#define PPC44x_PIN_SHIFT 28
32#define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT)
33
34/* Lowest TLB slot consumed by the default pinned TLBs */
35#define PPC44x_LOW_SLOT 63
36
Roland Dreierfcc188e2005-11-07 00:58:11 -080037/*
38 * Least significant 32-bits and extended real page number (ERPN) of
39 * UART0 physical address location for early serial text debug
40 */
Matt Porterc9cf73a2005-07-31 22:34:52 -070041#if defined(CONFIG_440SP)
Roland Dreierfcc188e2005-11-07 00:58:11 -080042#define UART0_PHYS_ERPN 1
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#define UART0_PHYS_IO_BASE 0xf0000200
Matt Porterc9cf73a2005-07-31 22:34:52 -070044#elif defined(CONFIG_440EP)
45#define UART0_PHYS_IO_BASE 0xe0000000
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#else
Roland Dreierfcc188e2005-11-07 00:58:11 -080047#define UART0_PHYS_ERPN 1
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#define UART0_PHYS_IO_BASE 0x40000200
49#endif
50
51/*
52 * XXX This 36-bit trap stuff will move somewhere in syslib/
53 * when we rework/abstract the PPC44x PCI-X handling -mdp
54 */
55
56/*
57 * Standard 4GB "page" definitions
58 */
Matt Porterc9cf73a2005-07-31 22:34:52 -070059#if defined(CONFIG_440SP)
Linus Torvalds1da177e2005-04-16 15:20:36 -070060#define PPC44x_IO_PAGE 0x0000000100000000ULL
61#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
62#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
63#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
Matt Porterc9cf73a2005-07-31 22:34:52 -070064#elif defined(CONFIG_440EP)
65#define PPC44x_IO_PAGE 0x0000000000000000ULL
66#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
67#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
68#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
Linus Torvalds1da177e2005-04-16 15:20:36 -070069#else
70#define PPC44x_IO_PAGE 0x0000000100000000ULL
71#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
72#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
73#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL
74#endif
75
76/*
77 * 36-bit trap ranges
78 */
Matt Porterc9cf73a2005-07-31 22:34:52 -070079#if defined(CONFIG_440SP)
Linus Torvalds1da177e2005-04-16 15:20:36 -070080#define PPC44x_IO_LO 0xf0000000UL
81#define PPC44x_IO_HI 0xf0000fffUL
82#define PPC44x_PCI0CFG_LO 0x0ec00000UL
83#define PPC44x_PCI0CFG_HI 0x0ec00007UL
84#define PPC44x_PCI1CFG_LO 0x1ec00000UL
85#define PPC44x_PCI1CFG_HI 0x1ec00007UL
86#define PPC44x_PCI2CFG_LO 0x2ec00000UL
87#define PPC44x_PCI2CFG_HI 0x2ec00007UL
88#define PPC44x_PCIMEM_LO 0x80000000UL
89#define PPC44x_PCIMEM_HI 0xdfffffffUL
Matt Porterc9cf73a2005-07-31 22:34:52 -070090#elif defined(CONFIG_440EP)
91#define PPC44x_IO_LO 0xef500000UL
92#define PPC44x_IO_HI 0xefffffffUL
93#define PPC44x_PCI0CFG_LO 0xeec00000UL
94#define PPC44x_PCI0CFG_HI 0xeecfffffUL
95#define PPC44x_PCIMEM_LO 0xa0000000UL
96#define PPC44x_PCIMEM_HI 0xdfffffffUL
Linus Torvalds1da177e2005-04-16 15:20:36 -070097#else
98#define PPC44x_IO_LO 0x40000000UL
99#define PPC44x_IO_HI 0x40000fffUL
100#define PPC44x_PCI0CFG_LO 0x0ec00000UL
101#define PPC44x_PCI0CFG_HI 0x0ec00007UL
102#define PPC44x_PCIMEM_LO 0x80002000UL
103#define PPC44x_PCIMEM_HI 0xffffffffUL
104#endif
105
106/*
107 * The "residual" board information structure the boot loader passes
108 * into the kernel.
109 */
110#ifndef __ASSEMBLY__
111
112/*
113 * DCRN definitions
114 */
115
116
117/* CPRs (440GX and 440SP) */
118#define DCRN_CPR_CONFIG_ADDR 0xc
119#define DCRN_CPR_CONFIG_DATA 0xd
120
121#define DCRN_CPR_CLKUPD 0x0020
122#define DCRN_CPR_PLLC 0x0040
123#define DCRN_CPR_PLLD 0x0060
124#define DCRN_CPR_PRIMAD 0x0080
125#define DCRN_CPR_PRIMBD 0x00a0
126#define DCRN_CPR_OPBD 0x00c0
127#define DCRN_CPR_PERD 0x00e0
128#define DCRN_CPR_MALD 0x0100
129
130/* CPRs read/write helper macros */
131#define CPR_READ(offset) ({\
132 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
133 mfdcr(DCRN_CPR_CONFIG_DATA);})
134#define CPR_WRITE(offset, data) ({\
135 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
136 mtdcr(DCRN_CPR_CONFIG_DATA, data);})
137
138/* SDRs (440GX and 440SP) */
139#define DCRN_SDR_CONFIG_ADDR 0xe
140#define DCRN_SDR_CONFIG_DATA 0xf
141#define DCRN_SDR_PFC0 0x4100
142#define DCRN_SDR_PFC1 0x4101
143#define DCRN_SDR_PFC1_EPS 0x1c00000
144#define DCRN_SDR_PFC1_EPS_SHIFT 22
145#define DCRN_SDR_PFC1_RMII 0x02000000
146#define DCRN_SDR_MFR 0x4300
147#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
148#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
149#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
150#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */
151#define DCRN_SDR_MFR_T0TXFL 0x00080000
152#define DCRN_SDR_MFR_T0TXFH 0x00040000
153#define DCRN_SDR_MFR_T1TXFL 0x00020000
154#define DCRN_SDR_MFR_T1TXFH 0x00010000
155#define DCRN_SDR_MFR_E0TXFL 0x00008000
156#define DCRN_SDR_MFR_E0TXFH 0x00004000
157#define DCRN_SDR_MFR_E0RXFL 0x00002000
158#define DCRN_SDR_MFR_E0RXFH 0x00001000
159#define DCRN_SDR_MFR_E1TXFL 0x00000800
160#define DCRN_SDR_MFR_E1TXFH 0x00000400
161#define DCRN_SDR_MFR_E1RXFL 0x00000200
162#define DCRN_SDR_MFR_E1RXFH 0x00000100
163#define DCRN_SDR_MFR_E2TXFL 0x00000080
164#define DCRN_SDR_MFR_E2TXFH 0x00000040
165#define DCRN_SDR_MFR_E2RXFL 0x00000020
166#define DCRN_SDR_MFR_E2RXFH 0x00000010
167#define DCRN_SDR_MFR_E3TXFL 0x00000008
168#define DCRN_SDR_MFR_E3TXFH 0x00000004
169#define DCRN_SDR_MFR_E3RXFL 0x00000002
170#define DCRN_SDR_MFR_E3RXFH 0x00000001
171#define DCRN_SDR_UART0 0x0120
172#define DCRN_SDR_UART1 0x0121
173
Matt Porterc9cf73a2005-07-31 22:34:52 -0700174#ifdef CONFIG_440EP
175#define DCRN_SDR_UART2 0x0122
176#define DCRN_SDR_UART3 0x0123
177#define DCRN_SDR_CUST0 0x4000
178#endif
179
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180/* SDR read/write helper macros */
181#define SDR_READ(offset) ({\
182 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
183 mfdcr(DCRN_SDR_CONFIG_DATA);})
184#define SDR_WRITE(offset, data) ({\
185 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
186 mtdcr(DCRN_SDR_CONFIG_DATA,data);})
187
188/* DMA (excluding 440SP) */
189#define DCRN_DMA0_BASE 0x100
190#define DCRN_DMA1_BASE 0x108
191#define DCRN_DMA2_BASE 0x110
192#define DCRN_DMA3_BASE 0x118
193#define DCRN_DMASR_BASE 0x120
194#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
195#define DCRN_MAL_BASE 0x180
196
Matt Porterc9cf73a2005-07-31 22:34:52 -0700197#ifdef CONFIG_440EP
198#define DCRN_DMA2P40_BASE 0x300
199#define DCRN_DMA2P41_BASE 0x308
200#define DCRN_DMA2P42_BASE 0x310
201#define DCRN_DMA2P43_BASE 0x318
202#define DCRN_DMA2P4SR_BASE 0x320
203#endif
204
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205/* UIC */
206#define DCRN_UIC0_BASE 0xc0
207#define DCRN_UIC1_BASE 0xd0
208#define DCRN_UIC2_BASE 0x210
209#define DCRN_UICB_BASE 0x200
210#define UIC0 DCRN_UIC0_BASE
211#define UIC1 DCRN_UIC1_BASE
212#define UIC2 DCRN_UIC2_BASE
213#define UICB DCRN_UICB_BASE
214
215#define DCRN_UIC_SR(base) (base + 0x0)
216#define DCRN_UIC_ER(base) (base + 0x2)
217#define DCRN_UIC_CR(base) (base + 0x3)
218#define DCRN_UIC_PR(base) (base + 0x4)
219#define DCRN_UIC_TR(base) (base + 0x5)
220#define DCRN_UIC_MSR(base) (base + 0x6)
221#define DCRN_UIC_VR(base) (base + 0x7)
222#define DCRN_UIC_VCR(base) (base + 0x8)
223
224#define UIC0_UIC1NC 0x00000002
225
226#define UICB_UIC0NC 0x40000000
227#define UICB_UIC1NC 0x10000000
228#define UICB_UIC2NC 0x04000000
229
230/* 440 MAL DCRs */
231#define DCRN_MALCR(base) (base + 0x0) /* Configuration */
232#define DCRN_MALESR(base) (base + 0x1) /* Error Status */
233#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */
234#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */
235#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */
236#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */
237#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */
238#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */
239#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */
240#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */
241#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */
242#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
243#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */
244#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */
245#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */
246#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
247#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
248#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
249#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
250
251/* Compatibility DCRN's */
252#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
253#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
254#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
255#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
256#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
257#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
258#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
259#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
260
261#define MALCR_MMSR 0x80000000 /* MAL Software reset */
262#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
263#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
264#define MALCR_PLBP_3 0x00C00000 /* highest */
265#define MALCR_GA 0x00200000 /* Guarded Active Bit */
266#define MALCR_OA 0x00100000 /* Ordered Active Bit */
267#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
268#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
269#define MALCR_PLBLT_2 0x00020000
270#define MALCR_PLBLT_3 0x00010000
271#define MALCR_PLBLT_4 0x00008000
272#ifdef CONFIG_440GP
273#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */
274#else
275#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */
276#endif
277#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
278#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
279#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
280#define MALCR_LEA 0x00000002 /* Locked Error Active */
281#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
282/* DCRN_MALESR */
283#define MALESR_EVB 0x80000000 /* Error Valid Bit */
284#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
285#define MALESR_DE 0x00100000 /* Descriptor Error */
286#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
287#define MALESR_OTE 0x00040000 /* OPB Timeout Error */
288#define MALESR_OSE 0x00020000 /* OPB Slave Error */
289#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
290#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
291#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
292#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
293#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
294#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
295/* DCRN_MALIER */
296#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
297#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
298#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
299#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
300#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
301/* DCRN_MALTXEOBISR */
302#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
303#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
304
Roland Dreier41aace42005-11-07 00:58:12 -0800305#if defined(CONFIG_440SP)
306/* 440SP PLB Arbiter DCRs */
307#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */
308#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */
309
310#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */
311#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */
312#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */
313#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */
314#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */
315
316#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */
317#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */
318#define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */
319#define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */
320#define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */
321#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322/* 440GP/GX PLB Arbiter DCRs */
323#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
324#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
325#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */
326#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
327#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
328#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
Roland Dreier41aace42005-11-07 00:58:12 -0800329#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330
331/* 440GP/GX PLB to OPB bridge DCRs */
332#define DCRN_POB0_BESR0 0x090
333#define DCRN_POB0_BESR1 0x094
334#define DCRN_POB0_BEARL 0x092
335#define DCRN_POB0_BEARH 0x093
336
337/* 440GP/GX OPB to PLB bridge DCRs */
338#define DCRN_OPB0_BSTAT 0x0a9
339#define DCRN_OPB0_BEARL 0x0aa
340#define DCRN_OPB0_BEARH 0x0ab
341
342/* 440GP Clock, PM, chip control */
343#define DCRN_CPC0_SR 0x0b0
344#define DCRN_CPC0_ER 0x0b1
345#define DCRN_CPC0_FR 0x0b2
346#define DCRN_CPC0_SYS0 0x0e0
347#define DCRN_CPC0_SYS1 0x0e1
348#define DCRN_CPC0_CUST0 0x0e2
349#define DCRN_CPC0_CUST1 0x0e3
350#define DCRN_CPC0_STRP0 0x0e4
351#define DCRN_CPC0_STRP1 0x0e5
352#define DCRN_CPC0_STRP2 0x0e6
353#define DCRN_CPC0_STRP3 0x0e7
354#define DCRN_CPC0_GPIO 0x0e8
355#define DCRN_CPC0_PLB 0x0e9
356#define DCRN_CPC0_CR1 0x0ea
357#define DCRN_CPC0_CR0 0x0eb
358#define DCRN_CPC0_MIRQ0 0x0ec
359#define DCRN_CPC0_MIRQ1 0x0ed
360#define DCRN_CPC0_JTAGID 0x0ef
361
362/* 440GP DMA controller DCRs */
363#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */
364#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */
365#define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */
366#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */
367#define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */
368#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */
369#define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */
370#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
371
372#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */
373#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */
374#define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */
375#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */
376#define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */
377#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */
378#define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */
379#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
380
381#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */
382#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */
383#define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */
384#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */
385#define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */
386#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */
387#define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */
388#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
389
390#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */
391#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */
392#define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */
393#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */
394#define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */
395#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */
396#define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */
397#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
398
399#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
400#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
401#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
402#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
403
404/* 440GP/440GX SDRAM controller DCRs */
405#define DCRN_SDRAM0_CFGADDR 0x010
406#define DCRN_SDRAM0_CFGDATA 0x011
407
408#define SDRAM0_B0CR 0x40
409#define SDRAM0_B1CR 0x44
410#define SDRAM0_B2CR 0x48
411#define SDRAM0_B3CR 0x4c
412
413#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
414#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
415#define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
416#define SDRAM_CONFIG_SIZE_8M 0x00000001
417#define SDRAM_CONFIG_SIZE_16M 0x00000002
418#define SDRAM_CONFIG_SIZE_32M 0x00000003
419#define SDRAM_CONFIG_SIZE_64M 0x00000004
420#define SDRAM_CONFIG_SIZE_128M 0x00000005
421#define SDRAM_CONFIG_SIZE_256M 0x00000006
422#define SDRAM_CONFIG_SIZE_512M 0x00000007
423#define PPC44x_MEM_SIZE_8M 0x00800000
424#define PPC44x_MEM_SIZE_16M 0x01000000
425#define PPC44x_MEM_SIZE_32M 0x02000000
426#define PPC44x_MEM_SIZE_64M 0x04000000
427#define PPC44x_MEM_SIZE_128M 0x08000000
428#define PPC44x_MEM_SIZE_256M 0x10000000
429#define PPC44x_MEM_SIZE_512M 0x20000000
430#define PPC44x_MEM_SIZE_1G 0x40000000
431#define PPC44x_MEM_SIZE_2G 0x80000000
432
433/* 440SP memory controller DCRs */
434#define DCRN_MQ0_BS0BAS 0x40
435#define DCRN_MQ0_BS1BAS 0x41
436
437#define MQ0_CONFIG_SIZE_MASK 0x0000fff0
438#define MQ0_CONFIG_SIZE_8M 0x0000ffc0
439#define MQ0_CONFIG_SIZE_16M 0x0000ff80
440#define MQ0_CONFIG_SIZE_32M 0x0000ff00
441#define MQ0_CONFIG_SIZE_64M 0x0000fe00
442#define MQ0_CONFIG_SIZE_128M 0x0000fc00
443#define MQ0_CONFIG_SIZE_256M 0x0000f800
444#define MQ0_CONFIG_SIZE_512M 0x0000f000
445#define MQ0_CONFIG_SIZE_1G 0x0000e000
446#define MQ0_CONFIG_SIZE_2G 0x0000c000
447
448/* Internal SRAM Controller 440GX/440SP */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449#define DCRN_SRAM0_BASE 0x000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450
451#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
452#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021)
453#define DCRN_SRAM0_SB2CR (DCRN_SRAM0_BASE + 0x022)
454#define DCRN_SRAM0_SB3CR (DCRN_SRAM0_BASE + 0x023)
455#define SRAM_SBCR_BAS0 0x80000000
456#define SRAM_SBCR_BAS1 0x80010000
457#define SRAM_SBCR_BAS2 0x80020000
458#define SRAM_SBCR_BAS3 0x80030000
459#define SRAM_SBCR_BU_MASK 0x00000180
460#define SRAM_SBCR_BS_64KB 0x00000800
461#define SRAM_SBCR_BU_RO 0x00000080
462#define SRAM_SBCR_BU_RW 0x00000180
463#define DCRN_SRAM0_BEAR (DCRN_SRAM0_BASE + 0x024)
464#define DCRN_SRAM0_BESR0 (DCRN_SRAM0_BASE + 0x025)
465#define DCRN_SRAM0_BESR1 (DCRN_SRAM0_BASE + 0x026)
466#define DCRN_SRAM0_PMEG (DCRN_SRAM0_BASE + 0x027)
467#define DCRN_SRAM0_CID (DCRN_SRAM0_BASE + 0x028)
468#define DCRN_SRAM0_REVID (DCRN_SRAM0_BASE + 0x029)
469#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a)
470#define SRAM_DPC_ENABLE 0x80000000
471
472/* L2 Cache Controller 440GX/440SP */
473#define DCRN_L2C0_CFG 0x030
474#define L2C_CFG_L2M 0x80000000
475#define L2C_CFG_ICU 0x40000000
476#define L2C_CFG_DCU 0x20000000
477#define L2C_CFG_DCW_MASK 0x1e000000
478#define L2C_CFG_TPC 0x01000000
479#define L2C_CFG_CPC 0x00800000
480#define L2C_CFG_FRAN 0x00200000
481#define L2C_CFG_SS_MASK 0x00180000
482#define L2C_CFG_SS_256 0x00000000
483#define L2C_CFG_CPIM 0x00040000
484#define L2C_CFG_TPIM 0x00020000
485#define L2C_CFG_LIM 0x00010000
486#define L2C_CFG_PMUX_MASK 0x00007000
487#define L2C_CFG_PMUX_SNP 0x00000000
488#define L2C_CFG_PMUX_IF 0x00001000
489#define L2C_CFG_PMUX_DF 0x00002000
490#define L2C_CFG_PMUX_DS 0x00003000
491#define L2C_CFG_PMIM 0x00000800
492#define L2C_CFG_TPEI 0x00000400
493#define L2C_CFG_CPEI 0x00000200
494#define L2C_CFG_NAM 0x00000100
495#define L2C_CFG_SMCM 0x00000080
496#define L2C_CFG_NBRM 0x00000040
497#define DCRN_L2C0_CMD 0x031
498#define L2C_CMD_CLR 0x80000000
499#define L2C_CMD_DIAG 0x40000000
500#define L2C_CMD_INV 0x20000000
501#define L2C_CMD_CCP 0x10000000
502#define L2C_CMD_CTE 0x08000000
503#define L2C_CMD_STRC 0x04000000
504#define L2C_CMD_STPC 0x02000000
505#define L2C_CMD_RPMC 0x01000000
506#define L2C_CMD_HCC 0x00800000
507#define DCRN_L2C0_ADDR 0x032
508#define DCRN_L2C0_DATA 0x033
509#define DCRN_L2C0_SR 0x034
510#define L2C_SR_CC 0x80000000
511#define L2C_SR_CPE 0x40000000
512#define L2C_SR_TPE 0x20000000
513#define L2C_SR_LRU 0x10000000
514#define L2C_SR_PCS 0x08000000
515#define DCRN_L2C0_REVID 0x035
516#define DCRN_L2C0_SNP0 0x036
517#define DCRN_L2C0_SNP1 0x037
518#define L2C_SNP_BA_MASK 0xffff0000
519#define L2C_SNP_SSR_MASK 0x0000f000
520#define L2C_SNP_SSR_32G 0x0000f000
521#define L2C_SNP_ESR 0x00000800
522
523/*
524 * PCI-X definitions
525 */
526#define PCIX0_CFGA 0x0ec00000UL
527#define PCIX1_CFGA 0x1ec00000UL
528#define PCIX2_CFGA 0x2ec00000UL
529#define PCIX0_CFGD 0x0ec00004UL
530#define PCIX1_CFGD 0x1ec00004UL
531#define PCIX2_CFGD 0x2ec00004UL
532
533#define PCIX0_IO_BASE 0x0000000908000000ULL
534#define PCIX1_IO_BASE 0x0000000908000000ULL
535#define PCIX2_IO_BASE 0x0000000908000000ULL
536#define PCIX_IO_SIZE 0x00010000
537
538#ifdef CONFIG_440SP
539#define PCIX0_REG_BASE 0x000000090ec80000ULL
540#else
541#define PCIX0_REG_BASE 0x000000020ec80000ULL
542#endif
543#define PCIX_REG_OFFSET 0x10000000
544#define PCIX_REG_SIZE 0x200
545
546#define PCIX0_VENDID 0x000
547#define PCIX0_DEVID 0x002
548#define PCIX0_COMMAND 0x004
549#define PCIX0_STATUS 0x006
550#define PCIX0_REVID 0x008
551#define PCIX0_CLS 0x009
552#define PCIX0_CACHELS 0x00c
553#define PCIX0_LATTIM 0x00d
554#define PCIX0_HDTYPE 0x00e
555#define PCIX0_BIST 0x00f
556#define PCIX0_BAR0L 0x010
557#define PCIX0_BAR0H 0x014
558#define PCIX0_BAR1 0x018
559#define PCIX0_BAR2L 0x01c
560#define PCIX0_BAR2H 0x020
561#define PCIX0_BAR3 0x024
562#define PCIX0_CISPTR 0x028
563#define PCIX0_SBSYSVID 0x02c
564#define PCIX0_SBSYSID 0x02e
565#define PCIX0_EROMBA 0x030
566#define PCIX0_CAP 0x034
567#define PCIX0_RES0 0x035
568#define PCIX0_RES1 0x036
569#define PCIX0_RES2 0x038
570#define PCIX0_INTLN 0x03c
571#define PCIX0_INTPN 0x03d
572#define PCIX0_MINGNT 0x03e
573#define PCIX0_MAXLTNCY 0x03f
574#define PCIX0_BRDGOPT1 0x040
575#define PCIX0_BRDGOPT2 0x044
576#define PCIX0_ERREN 0x050
577#define PCIX0_ERRSTS 0x054
578#define PCIX0_PLBBESR 0x058
579#define PCIX0_PLBBEARL 0x05c
580#define PCIX0_PLBBEARH 0x060
581#define PCIX0_POM0LAL 0x068
582#define PCIX0_POM0LAH 0x06c
583#define PCIX0_POM0SA 0x070
584#define PCIX0_POM0PCIAL 0x074
585#define PCIX0_POM0PCIAH 0x078
586#define PCIX0_POM1LAL 0x07c
587#define PCIX0_POM1LAH 0x080
588#define PCIX0_POM1SA 0x084
589#define PCIX0_POM1PCIAL 0x088
590#define PCIX0_POM1PCIAH 0x08c
591#define PCIX0_POM2SA 0x090
592#define PCIX0_PIM0SAL 0x098
593#define PCIX0_PIM0SA PCIX0_PIM0SAL
594#define PCIX0_PIM0LAL 0x09c
595#define PCIX0_PIM0LAH 0x0a0
596#define PCIX0_PIM1SA 0x0a4
597#define PCIX0_PIM1LAL 0x0a8
598#define PCIX0_PIM1LAH 0x0ac
599#define PCIX0_PIM2SAL 0x0b0
600#define PCIX0_PIM2SA PCIX0_PIM2SAL
601#define PCIX0_PIM2LAL 0x0b4
602#define PCIX0_PIM2LAH 0x0b8
603#define PCIX0_OMCAPID 0x0c0
604#define PCIX0_OMNIPTR 0x0c1
605#define PCIX0_OMMC 0x0c2
606#define PCIX0_OMMA 0x0c4
607#define PCIX0_OMMUA 0x0c8
608#define PCIX0_OMMDATA 0x0cc
609#define PCIX0_OMMEOI 0x0ce
610#define PCIX0_PMCAPID 0x0d0
611#define PCIX0_PMNIPTR 0x0d1
612#define PCIX0_PMC 0x0d2
613#define PCIX0_PMCSR 0x0d4
614#define PCIX0_PMCSRBSE 0x0d6
615#define PCIX0_PMDATA 0x0d7
616#define PCIX0_PMSCRR 0x0d8
617#define PCIX0_CAPID 0x0dc
618#define PCIX0_NIPTR 0x0dd
619#define PCIX0_CMD 0x0de
620#define PCIX0_STS 0x0e0
621#define PCIX0_IDR 0x0e4
622#define PCIX0_CID 0x0e8
623#define PCIX0_RID 0x0ec
624#define PCIX0_PIM0SAH 0x0f8
625#define PCIX0_PIM2SAH 0x0fc
626#define PCIX0_MSGIL 0x100
627#define PCIX0_MSGIH 0x104
628#define PCIX0_MSGOL 0x108
629#define PCIX0_MSGOH 0x10c
630#define PCIX0_IM 0x1f8
631
632#define IIC_OWN 0x55
633#define IIC_CLOCK 50
634
635#undef NR_UICS
636#ifdef CONFIG_440GX
637#define NR_UICS 3
638#else
639#define NR_UICS 2
640#endif
641
642#include <asm/ibm4xx.h>
643
644#endif /* __ASSEMBLY__ */
645#endif /* __ASM_IBM44x_H__ */
646#endif /* __KERNEL__ */