Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 1 | /* |
| 2 | * drivers/net/ethernet/rocker/rocker.h - Rocker switch device driver |
| 3 | * Copyright (c) 2014 Jiri Pirko <jiri@resnulli.us> |
| 4 | * Copyright (c) 2014 Scott Feldman <sfeldma@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | #ifndef _ROCKER_H |
| 13 | #define _ROCKER_H |
| 14 | |
| 15 | #include <linux/types.h> |
| 16 | |
Scott Feldman | 7eb344f | 2015-02-25 20:15:36 -0800 | [diff] [blame] | 17 | /* Return codes */ |
| 18 | enum { |
| 19 | ROCKER_OK = 0, |
| 20 | ROCKER_ENOENT = 2, |
| 21 | ROCKER_ENXIO = 6, |
| 22 | ROCKER_ENOMEM = 12, |
| 23 | ROCKER_EEXIST = 17, |
| 24 | ROCKER_EINVAL = 22, |
| 25 | ROCKER_EMSGSIZE = 90, |
| 26 | ROCKER_ENOTSUP = 95, |
| 27 | ROCKER_ENOBUFS = 105, |
| 28 | }; |
| 29 | |
Scott Feldman | 1b5ef07 | 2015-03-06 15:54:52 -0800 | [diff] [blame] | 30 | #define ROCKER_FP_PORTS_MAX 62 |
| 31 | |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 32 | #define PCI_VENDOR_ID_REDHAT 0x1b36 |
| 33 | #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 |
| 34 | |
| 35 | #define ROCKER_PCI_BAR0_SIZE 0x2000 |
| 36 | |
| 37 | /* MSI-X vectors */ |
| 38 | enum { |
| 39 | ROCKER_MSIX_VEC_CMD, |
| 40 | ROCKER_MSIX_VEC_EVENT, |
| 41 | ROCKER_MSIX_VEC_TEST, |
| 42 | ROCKER_MSIX_VEC_RESERVED0, |
| 43 | __ROCKER_MSIX_VEC_TX, |
| 44 | __ROCKER_MSIX_VEC_RX, |
| 45 | #define ROCKER_MSIX_VEC_TX(port) \ |
| 46 | (__ROCKER_MSIX_VEC_TX + ((port) * 2)) |
| 47 | #define ROCKER_MSIX_VEC_RX(port) \ |
| 48 | (__ROCKER_MSIX_VEC_RX + ((port) * 2)) |
| 49 | #define ROCKER_MSIX_VEC_COUNT(portcnt) \ |
| 50 | (ROCKER_MSIX_VEC_RX((portcnt - 1)) + 1) |
| 51 | }; |
| 52 | |
| 53 | /* Rocker bogus registers */ |
| 54 | #define ROCKER_BOGUS_REG0 0x0000 |
| 55 | #define ROCKER_BOGUS_REG1 0x0004 |
| 56 | #define ROCKER_BOGUS_REG2 0x0008 |
| 57 | #define ROCKER_BOGUS_REG3 0x000c |
| 58 | |
| 59 | /* Rocker test registers */ |
| 60 | #define ROCKER_TEST_REG 0x0010 |
| 61 | #define ROCKER_TEST_REG64 0x0018 /* 8-byte */ |
| 62 | #define ROCKER_TEST_IRQ 0x0020 |
| 63 | #define ROCKER_TEST_DMA_ADDR 0x0028 /* 8-byte */ |
| 64 | #define ROCKER_TEST_DMA_SIZE 0x0030 |
| 65 | #define ROCKER_TEST_DMA_CTRL 0x0034 |
| 66 | |
| 67 | /* Rocker test register ctrl */ |
Scott Feldman | 4725ceb | 2015-05-10 09:48:08 -0700 | [diff] [blame] | 68 | #define ROCKER_TEST_DMA_CTRL_CLEAR BIT(0) |
| 69 | #define ROCKER_TEST_DMA_CTRL_FILL BIT(1) |
| 70 | #define ROCKER_TEST_DMA_CTRL_INVERT BIT(2) |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 71 | |
| 72 | /* Rocker DMA ring register offsets */ |
| 73 | #define ROCKER_DMA_DESC_ADDR(x) (0x1000 + (x) * 32) /* 8-byte */ |
| 74 | #define ROCKER_DMA_DESC_SIZE(x) (0x1008 + (x) * 32) |
| 75 | #define ROCKER_DMA_DESC_HEAD(x) (0x100c + (x) * 32) |
| 76 | #define ROCKER_DMA_DESC_TAIL(x) (0x1010 + (x) * 32) |
| 77 | #define ROCKER_DMA_DESC_CTRL(x) (0x1014 + (x) * 32) |
| 78 | #define ROCKER_DMA_DESC_CREDITS(x) (0x1018 + (x) * 32) |
| 79 | #define ROCKER_DMA_DESC_RES1(x) (0x101c + (x) * 32) |
| 80 | |
| 81 | /* Rocker dma ctrl register bits */ |
Scott Feldman | 4725ceb | 2015-05-10 09:48:08 -0700 | [diff] [blame] | 82 | #define ROCKER_DMA_DESC_CTRL_RESET BIT(0) |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 83 | |
| 84 | /* Rocker DMA ring types */ |
| 85 | enum rocker_dma_type { |
| 86 | ROCKER_DMA_CMD, |
| 87 | ROCKER_DMA_EVENT, |
| 88 | __ROCKER_DMA_TX, |
| 89 | __ROCKER_DMA_RX, |
| 90 | #define ROCKER_DMA_TX(port) (__ROCKER_DMA_TX + (port) * 2) |
| 91 | #define ROCKER_DMA_RX(port) (__ROCKER_DMA_RX + (port) * 2) |
| 92 | }; |
| 93 | |
| 94 | /* Rocker DMA ring size limits and default sizes */ |
| 95 | #define ROCKER_DMA_SIZE_MIN 2ul |
| 96 | #define ROCKER_DMA_SIZE_MAX 65536ul |
| 97 | #define ROCKER_DMA_CMD_DEFAULT_SIZE 32ul |
| 98 | #define ROCKER_DMA_EVENT_DEFAULT_SIZE 32ul |
| 99 | #define ROCKER_DMA_TX_DEFAULT_SIZE 64ul |
| 100 | #define ROCKER_DMA_TX_DESC_SIZE 256 |
| 101 | #define ROCKER_DMA_RX_DEFAULT_SIZE 64ul |
| 102 | #define ROCKER_DMA_RX_DESC_SIZE 256 |
| 103 | |
| 104 | /* Rocker DMA descriptor struct */ |
| 105 | struct rocker_desc { |
| 106 | u64 buf_addr; |
| 107 | u64 cookie; |
| 108 | u16 buf_size; |
| 109 | u16 tlv_size; |
| 110 | u16 resv[5]; |
| 111 | u16 comp_err; |
| 112 | }; |
| 113 | |
Scott Feldman | 4725ceb | 2015-05-10 09:48:08 -0700 | [diff] [blame] | 114 | #define ROCKER_DMA_DESC_COMP_ERR_GEN BIT(15) |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 115 | |
| 116 | /* Rocker DMA TLV struct */ |
| 117 | struct rocker_tlv { |
| 118 | u32 type; |
| 119 | u16 len; |
| 120 | }; |
| 121 | |
| 122 | /* TLVs */ |
| 123 | enum { |
| 124 | ROCKER_TLV_CMD_UNSPEC, |
| 125 | ROCKER_TLV_CMD_TYPE, /* u16 */ |
| 126 | ROCKER_TLV_CMD_INFO, /* nest */ |
| 127 | |
| 128 | __ROCKER_TLV_CMD_MAX, |
| 129 | ROCKER_TLV_CMD_MAX = __ROCKER_TLV_CMD_MAX - 1, |
| 130 | }; |
| 131 | |
| 132 | enum { |
| 133 | ROCKER_TLV_CMD_TYPE_UNSPEC, |
| 134 | ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS, |
| 135 | ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS, |
| 136 | ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD, |
| 137 | ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD, |
| 138 | ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL, |
| 139 | ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS, |
| 140 | ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD, |
| 141 | ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD, |
| 142 | ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL, |
| 143 | ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS, |
| 144 | |
David Ahern | 9766e97 | 2015-01-29 20:59:33 -0700 | [diff] [blame] | 145 | ROCKER_TLV_CMD_TYPE_CLEAR_PORT_STATS, |
| 146 | ROCKER_TLV_CMD_TYPE_GET_PORT_STATS, |
| 147 | |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 148 | __ROCKER_TLV_CMD_TYPE_MAX, |
| 149 | ROCKER_TLV_CMD_TYPE_MAX = __ROCKER_TLV_CMD_TYPE_MAX - 1, |
| 150 | }; |
| 151 | |
| 152 | enum { |
| 153 | ROCKER_TLV_CMD_PORT_SETTINGS_UNSPEC, |
Scott Feldman | 4a6bb6d | 2015-02-25 20:15:37 -0800 | [diff] [blame] | 154 | ROCKER_TLV_CMD_PORT_SETTINGS_PPORT, /* u32 */ |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 155 | ROCKER_TLV_CMD_PORT_SETTINGS_SPEED, /* u32 */ |
| 156 | ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX, /* u8 */ |
| 157 | ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG, /* u8 */ |
| 158 | ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR, /* binary */ |
| 159 | ROCKER_TLV_CMD_PORT_SETTINGS_MODE, /* u8 */ |
Scott Feldman | 5111f80 | 2014-11-28 14:34:30 +0100 | [diff] [blame] | 160 | ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING, /* u8 */ |
David Ahern | db19170 | 2015-03-17 20:23:16 -0600 | [diff] [blame] | 161 | ROCKER_TLV_CMD_PORT_SETTINGS_PHYS_NAME, /* binary */ |
Scott Feldman | 77a58c7 | 2015-07-08 16:06:47 -0700 | [diff] [blame] | 162 | ROCKER_TLV_CMD_PORT_SETTINGS_MTU, /* u16 */ |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 163 | |
| 164 | __ROCKER_TLV_CMD_PORT_SETTINGS_MAX, |
| 165 | ROCKER_TLV_CMD_PORT_SETTINGS_MAX = |
| 166 | __ROCKER_TLV_CMD_PORT_SETTINGS_MAX - 1, |
| 167 | }; |
| 168 | |
David Ahern | 9766e97 | 2015-01-29 20:59:33 -0700 | [diff] [blame] | 169 | enum { |
| 170 | ROCKER_TLV_CMD_PORT_STATS_UNSPEC, |
Scott Feldman | 4a6bb6d | 2015-02-25 20:15:37 -0800 | [diff] [blame] | 171 | ROCKER_TLV_CMD_PORT_STATS_PPORT, /* u32 */ |
David Ahern | 9766e97 | 2015-01-29 20:59:33 -0700 | [diff] [blame] | 172 | |
| 173 | ROCKER_TLV_CMD_PORT_STATS_RX_PKTS, /* u64 */ |
| 174 | ROCKER_TLV_CMD_PORT_STATS_RX_BYTES, /* u64 */ |
| 175 | ROCKER_TLV_CMD_PORT_STATS_RX_DROPPED, /* u64 */ |
| 176 | ROCKER_TLV_CMD_PORT_STATS_RX_ERRORS, /* u64 */ |
| 177 | |
| 178 | ROCKER_TLV_CMD_PORT_STATS_TX_PKTS, /* u64 */ |
| 179 | ROCKER_TLV_CMD_PORT_STATS_TX_BYTES, /* u64 */ |
| 180 | ROCKER_TLV_CMD_PORT_STATS_TX_DROPPED, /* u64 */ |
| 181 | ROCKER_TLV_CMD_PORT_STATS_TX_ERRORS, /* u64 */ |
| 182 | |
| 183 | __ROCKER_TLV_CMD_PORT_STATS_MAX, |
| 184 | ROCKER_TLV_CMD_PORT_STATS_MAX = __ROCKER_TLV_CMD_PORT_STATS_MAX - 1, |
| 185 | }; |
| 186 | |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 187 | enum rocker_port_mode { |
| 188 | ROCKER_PORT_MODE_OF_DPA, |
| 189 | }; |
| 190 | |
| 191 | enum { |
| 192 | ROCKER_TLV_EVENT_UNSPEC, |
| 193 | ROCKER_TLV_EVENT_TYPE, /* u16 */ |
| 194 | ROCKER_TLV_EVENT_INFO, /* nest */ |
| 195 | |
| 196 | __ROCKER_TLV_EVENT_MAX, |
| 197 | ROCKER_TLV_EVENT_MAX = __ROCKER_TLV_EVENT_MAX - 1, |
| 198 | }; |
| 199 | |
| 200 | enum { |
| 201 | ROCKER_TLV_EVENT_TYPE_UNSPEC, |
| 202 | ROCKER_TLV_EVENT_TYPE_LINK_CHANGED, |
| 203 | ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN, |
| 204 | |
| 205 | __ROCKER_TLV_EVENT_TYPE_MAX, |
| 206 | ROCKER_TLV_EVENT_TYPE_MAX = __ROCKER_TLV_EVENT_TYPE_MAX - 1, |
| 207 | }; |
| 208 | |
| 209 | enum { |
| 210 | ROCKER_TLV_EVENT_LINK_CHANGED_UNSPEC, |
Scott Feldman | 4a6bb6d | 2015-02-25 20:15:37 -0800 | [diff] [blame] | 211 | ROCKER_TLV_EVENT_LINK_CHANGED_PPORT, /* u32 */ |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 212 | ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP, /* u8 */ |
| 213 | |
| 214 | __ROCKER_TLV_EVENT_LINK_CHANGED_MAX, |
| 215 | ROCKER_TLV_EVENT_LINK_CHANGED_MAX = |
| 216 | __ROCKER_TLV_EVENT_LINK_CHANGED_MAX - 1, |
| 217 | }; |
| 218 | |
| 219 | enum { |
| 220 | ROCKER_TLV_EVENT_MAC_VLAN_UNSPEC, |
Scott Feldman | 4a6bb6d | 2015-02-25 20:15:37 -0800 | [diff] [blame] | 221 | ROCKER_TLV_EVENT_MAC_VLAN_PPORT, /* u32 */ |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 222 | ROCKER_TLV_EVENT_MAC_VLAN_MAC, /* binary */ |
| 223 | ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID, /* __be16 */ |
| 224 | |
| 225 | __ROCKER_TLV_EVENT_MAC_VLAN_MAX, |
| 226 | ROCKER_TLV_EVENT_MAC_VLAN_MAX = __ROCKER_TLV_EVENT_MAC_VLAN_MAX - 1, |
| 227 | }; |
| 228 | |
| 229 | enum { |
| 230 | ROCKER_TLV_RX_UNSPEC, |
| 231 | ROCKER_TLV_RX_FLAGS, /* u16, see ROCKER_RX_FLAGS_ */ |
| 232 | ROCKER_TLV_RX_CSUM, /* u16 */ |
| 233 | ROCKER_TLV_RX_FRAG_ADDR, /* u64 */ |
| 234 | ROCKER_TLV_RX_FRAG_MAX_LEN, /* u16 */ |
| 235 | ROCKER_TLV_RX_FRAG_LEN, /* u16 */ |
| 236 | |
| 237 | __ROCKER_TLV_RX_MAX, |
| 238 | ROCKER_TLV_RX_MAX = __ROCKER_TLV_RX_MAX - 1, |
| 239 | }; |
| 240 | |
Scott Feldman | 4725ceb | 2015-05-10 09:48:08 -0700 | [diff] [blame] | 241 | #define ROCKER_RX_FLAGS_IPV4 BIT(0) |
| 242 | #define ROCKER_RX_FLAGS_IPV6 BIT(1) |
| 243 | #define ROCKER_RX_FLAGS_CSUM_CALC BIT(2) |
| 244 | #define ROCKER_RX_FLAGS_IPV4_CSUM_GOOD BIT(3) |
| 245 | #define ROCKER_RX_FLAGS_IP_FRAG BIT(4) |
| 246 | #define ROCKER_RX_FLAGS_TCP BIT(5) |
| 247 | #define ROCKER_RX_FLAGS_UDP BIT(6) |
| 248 | #define ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD BIT(7) |
Scott Feldman | 3f98a8e | 2015-07-18 18:24:51 -0700 | [diff] [blame] | 249 | #define ROCKER_RX_FLAGS_FWD_OFFLOAD BIT(8) |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 250 | |
| 251 | enum { |
| 252 | ROCKER_TLV_TX_UNSPEC, |
| 253 | ROCKER_TLV_TX_OFFLOAD, /* u8, see ROCKER_TX_OFFLOAD_ */ |
| 254 | ROCKER_TLV_TX_L3_CSUM_OFF, /* u16 */ |
| 255 | ROCKER_TLV_TX_TSO_MSS, /* u16 */ |
| 256 | ROCKER_TLV_TX_TSO_HDR_LEN, /* u16 */ |
| 257 | ROCKER_TLV_TX_FRAGS, /* array */ |
| 258 | |
| 259 | __ROCKER_TLV_TX_MAX, |
| 260 | ROCKER_TLV_TX_MAX = __ROCKER_TLV_TX_MAX - 1, |
| 261 | }; |
| 262 | |
| 263 | #define ROCKER_TX_OFFLOAD_NONE 0 |
| 264 | #define ROCKER_TX_OFFLOAD_IP_CSUM 1 |
| 265 | #define ROCKER_TX_OFFLOAD_TCP_UDP_CSUM 2 |
| 266 | #define ROCKER_TX_OFFLOAD_L3_CSUM 3 |
| 267 | #define ROCKER_TX_OFFLOAD_TSO 4 |
| 268 | |
| 269 | #define ROCKER_TX_FRAGS_MAX 16 |
| 270 | |
| 271 | enum { |
| 272 | ROCKER_TLV_TX_FRAG_UNSPEC, |
| 273 | ROCKER_TLV_TX_FRAG, /* nest */ |
| 274 | |
| 275 | __ROCKER_TLV_TX_FRAG_MAX, |
| 276 | ROCKER_TLV_TX_FRAG_MAX = __ROCKER_TLV_TX_FRAG_MAX - 1, |
| 277 | }; |
| 278 | |
| 279 | enum { |
| 280 | ROCKER_TLV_TX_FRAG_ATTR_UNSPEC, |
| 281 | ROCKER_TLV_TX_FRAG_ATTR_ADDR, /* u64 */ |
| 282 | ROCKER_TLV_TX_FRAG_ATTR_LEN, /* u16 */ |
| 283 | |
| 284 | __ROCKER_TLV_TX_FRAG_ATTR_MAX, |
| 285 | ROCKER_TLV_TX_FRAG_ATTR_MAX = __ROCKER_TLV_TX_FRAG_ATTR_MAX - 1, |
| 286 | }; |
| 287 | |
| 288 | /* cmd info nested for OF-DPA msgs */ |
| 289 | enum { |
| 290 | ROCKER_TLV_OF_DPA_UNSPEC, |
| 291 | ROCKER_TLV_OF_DPA_TABLE_ID, /* u16 */ |
| 292 | ROCKER_TLV_OF_DPA_PRIORITY, /* u32 */ |
| 293 | ROCKER_TLV_OF_DPA_HARDTIME, /* u32 */ |
| 294 | ROCKER_TLV_OF_DPA_IDLETIME, /* u32 */ |
| 295 | ROCKER_TLV_OF_DPA_COOKIE, /* u64 */ |
Scott Feldman | 4a6bb6d | 2015-02-25 20:15:37 -0800 | [diff] [blame] | 296 | ROCKER_TLV_OF_DPA_IN_PPORT, /* u32 */ |
| 297 | ROCKER_TLV_OF_DPA_IN_PPORT_MASK, /* u32 */ |
| 298 | ROCKER_TLV_OF_DPA_OUT_PPORT, /* u32 */ |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 299 | ROCKER_TLV_OF_DPA_GOTO_TABLE_ID, /* u16 */ |
| 300 | ROCKER_TLV_OF_DPA_GROUP_ID, /* u32 */ |
| 301 | ROCKER_TLV_OF_DPA_GROUP_ID_LOWER, /* u32 */ |
| 302 | ROCKER_TLV_OF_DPA_GROUP_COUNT, /* u16 */ |
| 303 | ROCKER_TLV_OF_DPA_GROUP_IDS, /* u32 array */ |
| 304 | ROCKER_TLV_OF_DPA_VLAN_ID, /* __be16 */ |
| 305 | ROCKER_TLV_OF_DPA_VLAN_ID_MASK, /* __be16 */ |
| 306 | ROCKER_TLV_OF_DPA_VLAN_PCP, /* __be16 */ |
| 307 | ROCKER_TLV_OF_DPA_VLAN_PCP_MASK, /* __be16 */ |
| 308 | ROCKER_TLV_OF_DPA_VLAN_PCP_ACTION, /* u8 */ |
| 309 | ROCKER_TLV_OF_DPA_NEW_VLAN_ID, /* __be16 */ |
| 310 | ROCKER_TLV_OF_DPA_NEW_VLAN_PCP, /* u8 */ |
| 311 | ROCKER_TLV_OF_DPA_TUNNEL_ID, /* u32 */ |
Scott Feldman | 4a6bb6d | 2015-02-25 20:15:37 -0800 | [diff] [blame] | 312 | ROCKER_TLV_OF_DPA_TUNNEL_LPORT, /* u32 */ |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 313 | ROCKER_TLV_OF_DPA_ETHERTYPE, /* __be16 */ |
| 314 | ROCKER_TLV_OF_DPA_DST_MAC, /* binary */ |
| 315 | ROCKER_TLV_OF_DPA_DST_MAC_MASK, /* binary */ |
| 316 | ROCKER_TLV_OF_DPA_SRC_MAC, /* binary */ |
| 317 | ROCKER_TLV_OF_DPA_SRC_MAC_MASK, /* binary */ |
| 318 | ROCKER_TLV_OF_DPA_IP_PROTO, /* u8 */ |
| 319 | ROCKER_TLV_OF_DPA_IP_PROTO_MASK, /* u8 */ |
| 320 | ROCKER_TLV_OF_DPA_IP_DSCP, /* u8 */ |
| 321 | ROCKER_TLV_OF_DPA_IP_DSCP_MASK, /* u8 */ |
| 322 | ROCKER_TLV_OF_DPA_IP_DSCP_ACTION, /* u8 */ |
| 323 | ROCKER_TLV_OF_DPA_NEW_IP_DSCP, /* u8 */ |
| 324 | ROCKER_TLV_OF_DPA_IP_ECN, /* u8 */ |
| 325 | ROCKER_TLV_OF_DPA_IP_ECN_MASK, /* u8 */ |
| 326 | ROCKER_TLV_OF_DPA_DST_IP, /* __be32 */ |
| 327 | ROCKER_TLV_OF_DPA_DST_IP_MASK, /* __be32 */ |
| 328 | ROCKER_TLV_OF_DPA_SRC_IP, /* __be32 */ |
| 329 | ROCKER_TLV_OF_DPA_SRC_IP_MASK, /* __be32 */ |
| 330 | ROCKER_TLV_OF_DPA_DST_IPV6, /* binary */ |
| 331 | ROCKER_TLV_OF_DPA_DST_IPV6_MASK, /* binary */ |
| 332 | ROCKER_TLV_OF_DPA_SRC_IPV6, /* binary */ |
| 333 | ROCKER_TLV_OF_DPA_SRC_IPV6_MASK, /* binary */ |
| 334 | ROCKER_TLV_OF_DPA_SRC_ARP_IP, /* __be32 */ |
| 335 | ROCKER_TLV_OF_DPA_SRC_ARP_IP_MASK, /* __be32 */ |
| 336 | ROCKER_TLV_OF_DPA_L4_DST_PORT, /* __be16 */ |
| 337 | ROCKER_TLV_OF_DPA_L4_DST_PORT_MASK, /* __be16 */ |
| 338 | ROCKER_TLV_OF_DPA_L4_SRC_PORT, /* __be16 */ |
| 339 | ROCKER_TLV_OF_DPA_L4_SRC_PORT_MASK, /* __be16 */ |
| 340 | ROCKER_TLV_OF_DPA_ICMP_TYPE, /* u8 */ |
| 341 | ROCKER_TLV_OF_DPA_ICMP_TYPE_MASK, /* u8 */ |
| 342 | ROCKER_TLV_OF_DPA_ICMP_CODE, /* u8 */ |
| 343 | ROCKER_TLV_OF_DPA_ICMP_CODE_MASK, /* u8 */ |
| 344 | ROCKER_TLV_OF_DPA_IPV6_LABEL, /* __be32 */ |
| 345 | ROCKER_TLV_OF_DPA_IPV6_LABEL_MASK, /* __be32 */ |
| 346 | ROCKER_TLV_OF_DPA_QUEUE_ID_ACTION, /* u8 */ |
| 347 | ROCKER_TLV_OF_DPA_NEW_QUEUE_ID, /* u8 */ |
| 348 | ROCKER_TLV_OF_DPA_CLEAR_ACTIONS, /* u32 */ |
| 349 | ROCKER_TLV_OF_DPA_POP_VLAN, /* u8 */ |
| 350 | ROCKER_TLV_OF_DPA_TTL_CHECK, /* u8 */ |
| 351 | ROCKER_TLV_OF_DPA_COPY_CPU_ACTION, /* u8 */ |
| 352 | |
| 353 | __ROCKER_TLV_OF_DPA_MAX, |
| 354 | ROCKER_TLV_OF_DPA_MAX = __ROCKER_TLV_OF_DPA_MAX - 1, |
| 355 | }; |
| 356 | |
| 357 | /* OF-DPA table IDs */ |
| 358 | |
| 359 | enum rocker_of_dpa_table_id { |
| 360 | ROCKER_OF_DPA_TABLE_ID_INGRESS_PORT = 0, |
| 361 | ROCKER_OF_DPA_TABLE_ID_VLAN = 10, |
| 362 | ROCKER_OF_DPA_TABLE_ID_TERMINATION_MAC = 20, |
| 363 | ROCKER_OF_DPA_TABLE_ID_UNICAST_ROUTING = 30, |
| 364 | ROCKER_OF_DPA_TABLE_ID_MULTICAST_ROUTING = 40, |
| 365 | ROCKER_OF_DPA_TABLE_ID_BRIDGING = 50, |
| 366 | ROCKER_OF_DPA_TABLE_ID_ACL_POLICY = 60, |
| 367 | }; |
| 368 | |
| 369 | /* OF-DPA flow stats */ |
| 370 | enum { |
| 371 | ROCKER_TLV_OF_DPA_FLOW_STAT_UNSPEC, |
| 372 | ROCKER_TLV_OF_DPA_FLOW_STAT_DURATION, /* u32 */ |
| 373 | ROCKER_TLV_OF_DPA_FLOW_STAT_RX_PKTS, /* u64 */ |
| 374 | ROCKER_TLV_OF_DPA_FLOW_STAT_TX_PKTS, /* u64 */ |
| 375 | |
| 376 | __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX, |
| 377 | ROCKER_TLV_OF_DPA_FLOW_STAT_MAX = __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX - 1, |
| 378 | }; |
| 379 | |
| 380 | /* OF-DPA group types */ |
| 381 | enum rocker_of_dpa_group_type { |
| 382 | ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE = 0, |
| 383 | ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE, |
| 384 | ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST, |
| 385 | ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST, |
| 386 | ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD, |
| 387 | ROCKER_OF_DPA_GROUP_TYPE_L3_INTERFACE, |
| 388 | ROCKER_OF_DPA_GROUP_TYPE_L3_MCAST, |
| 389 | ROCKER_OF_DPA_GROUP_TYPE_L3_ECMP, |
| 390 | ROCKER_OF_DPA_GROUP_TYPE_L2_OVERLAY, |
| 391 | }; |
| 392 | |
| 393 | /* OF-DPA group L2 overlay types */ |
| 394 | enum rocker_of_dpa_overlay_type { |
| 395 | ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_UCAST = 0, |
| 396 | ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_MCAST, |
| 397 | ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_UCAST, |
| 398 | ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_MCAST, |
| 399 | }; |
| 400 | |
| 401 | /* OF-DPA group ID encoding */ |
| 402 | #define ROCKER_GROUP_TYPE_SHIFT 28 |
| 403 | #define ROCKER_GROUP_TYPE_MASK 0xf0000000 |
| 404 | #define ROCKER_GROUP_VLAN_SHIFT 16 |
| 405 | #define ROCKER_GROUP_VLAN_MASK 0x0fff0000 |
| 406 | #define ROCKER_GROUP_PORT_SHIFT 0 |
| 407 | #define ROCKER_GROUP_PORT_MASK 0x0000ffff |
| 408 | #define ROCKER_GROUP_TUNNEL_ID_SHIFT 12 |
| 409 | #define ROCKER_GROUP_TUNNEL_ID_MASK 0x0ffff000 |
| 410 | #define ROCKER_GROUP_SUBTYPE_SHIFT 10 |
| 411 | #define ROCKER_GROUP_SUBTYPE_MASK 0x00000c00 |
| 412 | #define ROCKER_GROUP_INDEX_SHIFT 0 |
| 413 | #define ROCKER_GROUP_INDEX_MASK 0x0000ffff |
| 414 | #define ROCKER_GROUP_INDEX_LONG_SHIFT 0 |
| 415 | #define ROCKER_GROUP_INDEX_LONG_MASK 0x0fffffff |
| 416 | |
| 417 | #define ROCKER_GROUP_TYPE_GET(group_id) \ |
| 418 | (((group_id) & ROCKER_GROUP_TYPE_MASK) >> ROCKER_GROUP_TYPE_SHIFT) |
| 419 | #define ROCKER_GROUP_TYPE_SET(type) \ |
| 420 | (((type) << ROCKER_GROUP_TYPE_SHIFT) & ROCKER_GROUP_TYPE_MASK) |
| 421 | #define ROCKER_GROUP_VLAN_GET(group_id) \ |
| 422 | (((group_id) & ROCKER_GROUP_VLAN_ID_MASK) >> ROCKER_GROUP_VLAN_ID_SHIFT) |
| 423 | #define ROCKER_GROUP_VLAN_SET(vlan_id) \ |
| 424 | (((vlan_id) << ROCKER_GROUP_VLAN_SHIFT) & ROCKER_GROUP_VLAN_MASK) |
| 425 | #define ROCKER_GROUP_PORT_GET(group_id) \ |
| 426 | (((group_id) & ROCKER_GROUP_PORT_MASK) >> ROCKER_GROUP_PORT_SHIFT) |
| 427 | #define ROCKER_GROUP_PORT_SET(port) \ |
| 428 | (((port) << ROCKER_GROUP_PORT_SHIFT) & ROCKER_GROUP_PORT_MASK) |
| 429 | #define ROCKER_GROUP_INDEX_GET(group_id) \ |
| 430 | (((group_id) & ROCKER_GROUP_INDEX_MASK) >> ROCKER_GROUP_INDEX_SHIFT) |
| 431 | #define ROCKER_GROUP_INDEX_SET(index) \ |
| 432 | (((index) << ROCKER_GROUP_INDEX_SHIFT) & ROCKER_GROUP_INDEX_MASK) |
| 433 | #define ROCKER_GROUP_INDEX_LONG_GET(group_id) \ |
| 434 | (((group_id) & ROCKER_GROUP_INDEX_LONG_MASK) >> \ |
| 435 | ROCKER_GROUP_INDEX_LONG_SHIFT) |
| 436 | #define ROCKER_GROUP_INDEX_LONG_SET(index) \ |
| 437 | (((index) << ROCKER_GROUP_INDEX_LONG_SHIFT) & \ |
| 438 | ROCKER_GROUP_INDEX_LONG_MASK) |
| 439 | |
| 440 | #define ROCKER_GROUP_NONE 0 |
| 441 | #define ROCKER_GROUP_L2_INTERFACE(vlan_id, port) \ |
| 442 | (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE) |\ |
| 443 | ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_PORT_SET(port)) |
| 444 | #define ROCKER_GROUP_L2_REWRITE(index) \ |
| 445 | (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE) |\ |
| 446 | ROCKER_GROUP_INDEX_LONG_SET(index)) |
| 447 | #define ROCKER_GROUP_L2_MCAST(vlan_id, index) \ |
| 448 | (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST) |\ |
| 449 | ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index)) |
| 450 | #define ROCKER_GROUP_L2_FLOOD(vlan_id, index) \ |
| 451 | (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD) |\ |
| 452 | ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index)) |
| 453 | #define ROCKER_GROUP_L3_UNICAST(index) \ |
| 454 | (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST) |\ |
| 455 | ROCKER_GROUP_INDEX_LONG_SET(index)) |
| 456 | |
| 457 | /* Rocker general purpose registers */ |
| 458 | #define ROCKER_CONTROL 0x0300 |
| 459 | #define ROCKER_PORT_PHYS_COUNT 0x0304 |
| 460 | #define ROCKER_PORT_PHYS_LINK_STATUS 0x0310 /* 8-byte */ |
| 461 | #define ROCKER_PORT_PHYS_ENABLE 0x0318 /* 8-byte */ |
| 462 | #define ROCKER_SWITCH_ID 0x0320 /* 8-byte */ |
| 463 | |
| 464 | /* Rocker control bits */ |
Scott Feldman | 4725ceb | 2015-05-10 09:48:08 -0700 | [diff] [blame] | 465 | #define ROCKER_CONTROL_RESET BIT(0) |
Jiri Pirko | 4b8ac96 | 2014-11-28 14:34:26 +0100 | [diff] [blame] | 466 | |
| 467 | #endif |