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Saeed Bisharaedabd382009-08-06 15:12:43 +03001/*
2 * arch/arm/mach-dove/include/mach/bridge-regs.h
3 *
4 * Mbus-L to Mbus Bridge Registers
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_BRIDGE_REGS_H
12#define __ASM_ARCH_BRIDGE_REGS_H
13
14#include <mach/dove.h>
15
16#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000)
17
18#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
19#define CPU_CTRL_PCIE0_LINK 0x00000001
20#define CPU_RESET 0x00000002
21#define CPU_CTRL_PCIE1_LINK 0x00000008
22
23#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
24#define SOFT_RESET_OUT_EN 0x00000004
25
26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
27#define SOFT_RESET 0x00000001
28
29#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
30#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
31#define BRIDGE_INT_TIMER0 0x0002
32#define BRIDGE_INT_TIMER1 0x0004
33#define BRIDGE_INT_TIMER1_CLR (~0x0004)
34
35#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
36#define IRQ_CAUSE_LOW_OFF 0x0000
37#define IRQ_MASK_LOW_OFF 0x0004
38#define FIQ_MASK_LOW_OFF 0x0008
39#define ENDPOINT_MASK_LOW_OFF 0x000c
40#define IRQ_CAUSE_HIGH_OFF 0x0010
41#define IRQ_MASK_HIGH_OFF 0x0014
42#define FIQ_MASK_HIGH_OFF 0x0018
43#define ENDPOINT_MASK_HIGH_OFF 0x001c
44#define PCIE_INTERRUPT_MASK_OFF 0x0020
45
46#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
47#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
48#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
49#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
50#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
51#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
52#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
53
54#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c)
55
56#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
57
58#endif