Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* irq.c: FRV IRQ handling |
| 2 | * |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 3 | * Copyright (C) 2003, 2004, 2006 Red Hat, Inc. All Rights Reserved. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Written by David Howells (dhowells@redhat.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
| 11 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <linux/ptrace.h> |
| 13 | #include <linux/errno.h> |
| 14 | #include <linux/signal.h> |
| 15 | #include <linux/sched.h> |
| 16 | #include <linux/ioport.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/timex.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <linux/random.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <linux/init.h> |
| 21 | #include <linux/kernel_stat.h> |
| 22 | #include <linux/irq.h> |
| 23 | #include <linux/proc_fs.h> |
| 24 | #include <linux/seq_file.h> |
David Howells | 4023440 | 2006-01-08 01:01:19 -0800 | [diff] [blame] | 25 | #include <linux/module.h> |
Jiri Slaby | 1977f03 | 2007-10-18 23:40:25 -0700 | [diff] [blame] | 26 | #include <linux/bitops.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 27 | |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 28 | #include <linux/atomic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | #include <asm/io.h> |
| 30 | #include <asm/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | #include <asm/uaccess.h> |
| 32 | #include <asm/pgalloc.h> |
| 33 | #include <asm/delay.h> |
| 34 | #include <asm/irq.h> |
| 35 | #include <asm/irc-regs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include <asm/gdb-stub.h> |
| 37 | |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 38 | #define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16)) |
| 39 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | extern void __init fpga_init(void); |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 41 | #ifdef CONFIG_FUJITSU_MB93493 |
| 42 | extern void __init mb93493_init(void); |
| 43 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 45 | #define __reg16(ADDR) (*(volatile unsigned short *)(ADDR)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | |
| 47 | atomic_t irq_err_count; |
| 48 | |
Thomas Gleixner | a120017 | 2011-03-24 18:48:36 +0100 | [diff] [blame] | 49 | int arch_show_interrupts(struct seq_file *p, int prec) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | { |
Thomas Gleixner | a120017 | 2011-03-24 18:48:36 +0100 | [diff] [blame] | 51 | seq_printf(p, "%*s: ", prec, "ERR"); |
| 52 | seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | return 0; |
| 54 | } |
| 55 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | /* |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 57 | * on-CPU PIC operations |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | */ |
Thomas Gleixner | 380e311 | 2011-02-06 20:20:38 +0100 | [diff] [blame] | 59 | static void frv_cpupic_ack(struct irq_data *d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | { |
Thomas Gleixner | 380e311 | 2011-02-06 20:20:38 +0100 | [diff] [blame] | 61 | __clr_RC(d->irq); |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 62 | __clr_IRL(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | } |
| 64 | |
Thomas Gleixner | 380e311 | 2011-02-06 20:20:38 +0100 | [diff] [blame] | 65 | static void frv_cpupic_mask(struct irq_data *d) |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 66 | { |
Thomas Gleixner | 380e311 | 2011-02-06 20:20:38 +0100 | [diff] [blame] | 67 | __set_MASK(d->irq); |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 68 | } |
David Howells | 4023440 | 2006-01-08 01:01:19 -0800 | [diff] [blame] | 69 | |
Thomas Gleixner | 380e311 | 2011-02-06 20:20:38 +0100 | [diff] [blame] | 70 | static void frv_cpupic_mask_ack(struct irq_data *d) |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 71 | { |
Thomas Gleixner | 380e311 | 2011-02-06 20:20:38 +0100 | [diff] [blame] | 72 | __set_MASK(d->irq); |
| 73 | __clr_RC(d->irq); |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 74 | __clr_IRL(); |
| 75 | } |
| 76 | |
Thomas Gleixner | 380e311 | 2011-02-06 20:20:38 +0100 | [diff] [blame] | 77 | static void frv_cpupic_unmask(struct irq_data *d) |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 78 | { |
Thomas Gleixner | 380e311 | 2011-02-06 20:20:38 +0100 | [diff] [blame] | 79 | __clr_MASK(d->irq); |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 80 | } |
| 81 | |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 82 | static struct irq_chip frv_cpu_pic = { |
| 83 | .name = "cpu", |
Thomas Gleixner | 380e311 | 2011-02-06 20:20:38 +0100 | [diff] [blame] | 84 | .irq_ack = frv_cpupic_ack, |
| 85 | .irq_mask = frv_cpupic_mask, |
| 86 | .irq_mask_ack = frv_cpupic_mask_ack, |
| 87 | .irq_unmask = frv_cpupic_unmask, |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 88 | }; |
| 89 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | /* |
Simon Arlott | 761a7e3 | 2007-10-20 01:09:42 +0200 | [diff] [blame] | 91 | * handles all normal device IRQs |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | * - registers are referred to by the __frame variable (GR28) |
| 93 | * - IRQ distribution is complicated in this arch because of the many PICs, the |
| 94 | * way they work and the way they cascade |
| 95 | */ |
| 96 | asmlinkage void do_IRQ(void) |
| 97 | { |
David Howells | 28baeba | 2006-02-14 13:53:20 -0800 | [diff] [blame] | 98 | irq_enter(); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 99 | generic_handle_irq(__get_IRL()); |
David Howells | 28baeba | 2006-02-14 13:53:20 -0800 | [diff] [blame] | 100 | irq_exit(); |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 101 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | /* |
| 104 | * handles all NMIs when not co-opted by the debugger |
| 105 | * - registers are referred to by the __frame variable (GR28) |
| 106 | */ |
| 107 | asmlinkage void do_NMI(void) |
| 108 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | } |
| 110 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | /* |
| 112 | * initialise the interrupt system |
| 113 | */ |
| 114 | void __init init_IRQ(void) |
| 115 | { |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 116 | int level; |
| 117 | |
| 118 | for (level = 1; level <= 14; level++) |
Thomas Gleixner | de2e95a | 2011-03-24 16:38:49 +0100 | [diff] [blame] | 119 | irq_set_chip_and_handler(level, &frv_cpu_pic, |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 120 | handle_level_irq); |
| 121 | |
Thomas Gleixner | de2e95a | 2011-03-24 16:38:49 +0100 | [diff] [blame] | 122 | irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq); |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 123 | |
| 124 | /* set the trigger levels for internal interrupt sources |
| 125 | * - timers all falling-edge |
| 126 | * - ERR0 is rising-edge |
| 127 | * - all others are high-level |
| 128 | */ |
| 129 | __set_IITMR(0, 0x003f0000); /* DMA0-3, TIMER0-2 */ |
| 130 | __set_IITMR(1, 0x20000000); /* ERR0-1, UART0-1, DMA4-7 */ |
| 131 | |
| 132 | /* route internal interrupts */ |
| 133 | set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL, |
| 134 | IRQ_DMA0_LEVEL); |
| 135 | set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL); |
| 136 | set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL, |
| 137 | IRQ_UART1_LEVEL, IRQ_UART0_LEVEL); |
| 138 | set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL, |
| 139 | IRQ_DMA4_LEVEL); |
| 140 | |
| 141 | /* route external interrupts */ |
| 142 | set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL, |
| 143 | IRQ_XIRQ4_LEVEL); |
| 144 | set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL, |
| 145 | IRQ_XIRQ0_LEVEL); |
| 146 | |
| 147 | #if defined(CONFIG_MB93091_VDK) |
| 148 | __set_TM1(0x55550000); /* XIRQ7-0 all active low */ |
| 149 | #elif defined(CONFIG_MB93093_PDK) |
| 150 | __set_TM1(0x15550000); /* XIRQ7 active high, 6-0 all active low */ |
| 151 | #else |
| 152 | #error dont know external IRQ trigger levels for this setup |
| 153 | #endif |
| 154 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | fpga_init(); |
| 156 | #ifdef CONFIG_FUJITSU_MB93493 |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 157 | mb93493_init(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | #endif |
David Howells | 1bcbba3 | 2006-09-25 23:32:04 -0700 | [diff] [blame] | 159 | } |