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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* irq.c: FRV IRQ handling
2 *
David Howells1bcbba32006-09-25 23:32:04 -07003 * Copyright (C) 2003, 2004, 2006 Red Hat, Inc. All Rights Reserved.
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/ptrace.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/ioport.h>
17#include <linux/interrupt.h>
18#include <linux/timex.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/random.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/init.h>
21#include <linux/kernel_stat.h>
22#include <linux/irq.h>
23#include <linux/proc_fs.h>
24#include <linux/seq_file.h>
David Howells40234402006-01-08 01:01:19 -080025#include <linux/module.h>
Jiri Slaby1977f032007-10-18 23:40:25 -070026#include <linux/bitops.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
Arun Sharma600634972011-07-26 16:09:06 -070028#include <linux/atomic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <asm/io.h>
30#include <asm/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#include <asm/uaccess.h>
32#include <asm/pgalloc.h>
33#include <asm/delay.h>
34#include <asm/irq.h>
35#include <asm/irc-regs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <asm/gdb-stub.h>
37
David Howells1bcbba32006-09-25 23:32:04 -070038#define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16))
39
Linus Torvalds1da177e2005-04-16 15:20:36 -070040extern void __init fpga_init(void);
David Howells1bcbba32006-09-25 23:32:04 -070041#ifdef CONFIG_FUJITSU_MB93493
42extern void __init mb93493_init(void);
43#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070044
David Howells1bcbba32006-09-25 23:32:04 -070045#define __reg16(ADDR) (*(volatile unsigned short *)(ADDR))
Linus Torvalds1da177e2005-04-16 15:20:36 -070046
47atomic_t irq_err_count;
48
Thomas Gleixnera1200172011-03-24 18:48:36 +010049int arch_show_interrupts(struct seq_file *p, int prec)
Linus Torvalds1da177e2005-04-16 15:20:36 -070050{
Thomas Gleixnera1200172011-03-24 18:48:36 +010051 seq_printf(p, "%*s: ", prec, "ERR");
52 seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
Linus Torvalds1da177e2005-04-16 15:20:36 -070053 return 0;
54}
55
Linus Torvalds1da177e2005-04-16 15:20:36 -070056/*
David Howells1bcbba32006-09-25 23:32:04 -070057 * on-CPU PIC operations
Linus Torvalds1da177e2005-04-16 15:20:36 -070058 */
Thomas Gleixner380e3112011-02-06 20:20:38 +010059static void frv_cpupic_ack(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070060{
Thomas Gleixner380e3112011-02-06 20:20:38 +010061 __clr_RC(d->irq);
David Howells1bcbba32006-09-25 23:32:04 -070062 __clr_IRL();
Linus Torvalds1da177e2005-04-16 15:20:36 -070063}
64
Thomas Gleixner380e3112011-02-06 20:20:38 +010065static void frv_cpupic_mask(struct irq_data *d)
David Howells1bcbba32006-09-25 23:32:04 -070066{
Thomas Gleixner380e3112011-02-06 20:20:38 +010067 __set_MASK(d->irq);
David Howells1bcbba32006-09-25 23:32:04 -070068}
David Howells40234402006-01-08 01:01:19 -080069
Thomas Gleixner380e3112011-02-06 20:20:38 +010070static void frv_cpupic_mask_ack(struct irq_data *d)
David Howells1bcbba32006-09-25 23:32:04 -070071{
Thomas Gleixner380e3112011-02-06 20:20:38 +010072 __set_MASK(d->irq);
73 __clr_RC(d->irq);
David Howells1bcbba32006-09-25 23:32:04 -070074 __clr_IRL();
75}
76
Thomas Gleixner380e3112011-02-06 20:20:38 +010077static void frv_cpupic_unmask(struct irq_data *d)
David Howells1bcbba32006-09-25 23:32:04 -070078{
Thomas Gleixner380e3112011-02-06 20:20:38 +010079 __clr_MASK(d->irq);
David Howells1bcbba32006-09-25 23:32:04 -070080}
81
David Howells1bcbba32006-09-25 23:32:04 -070082static struct irq_chip frv_cpu_pic = {
83 .name = "cpu",
Thomas Gleixner380e3112011-02-06 20:20:38 +010084 .irq_ack = frv_cpupic_ack,
85 .irq_mask = frv_cpupic_mask,
86 .irq_mask_ack = frv_cpupic_mask_ack,
87 .irq_unmask = frv_cpupic_unmask,
David Howells1bcbba32006-09-25 23:32:04 -070088};
89
Linus Torvalds1da177e2005-04-16 15:20:36 -070090/*
Simon Arlott761a7e32007-10-20 01:09:42 +020091 * handles all normal device IRQs
Linus Torvalds1da177e2005-04-16 15:20:36 -070092 * - registers are referred to by the __frame variable (GR28)
93 * - IRQ distribution is complicated in this arch because of the many PICs, the
94 * way they work and the way they cascade
95 */
96asmlinkage void do_IRQ(void)
97{
David Howells28baeba2006-02-14 13:53:20 -080098 irq_enter();
David Howells7d12e782006-10-05 14:55:46 +010099 generic_handle_irq(__get_IRL());
David Howells28baeba2006-02-14 13:53:20 -0800100 irq_exit();
David Howells1bcbba32006-09-25 23:32:04 -0700101}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103/*
104 * handles all NMIs when not co-opted by the debugger
105 * - registers are referred to by the __frame variable (GR28)
106 */
107asmlinkage void do_NMI(void)
108{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109}
110
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111/*
112 * initialise the interrupt system
113 */
114void __init init_IRQ(void)
115{
David Howells1bcbba32006-09-25 23:32:04 -0700116 int level;
117
118 for (level = 1; level <= 14; level++)
Thomas Gleixnerde2e95a2011-03-24 16:38:49 +0100119 irq_set_chip_and_handler(level, &frv_cpu_pic,
David Howells1bcbba32006-09-25 23:32:04 -0700120 handle_level_irq);
121
Thomas Gleixnerde2e95a2011-03-24 16:38:49 +0100122 irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq);
David Howells1bcbba32006-09-25 23:32:04 -0700123
124 /* set the trigger levels for internal interrupt sources
125 * - timers all falling-edge
126 * - ERR0 is rising-edge
127 * - all others are high-level
128 */
129 __set_IITMR(0, 0x003f0000); /* DMA0-3, TIMER0-2 */
130 __set_IITMR(1, 0x20000000); /* ERR0-1, UART0-1, DMA4-7 */
131
132 /* route internal interrupts */
133 set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL,
134 IRQ_DMA0_LEVEL);
135 set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL);
136 set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL,
137 IRQ_UART1_LEVEL, IRQ_UART0_LEVEL);
138 set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL,
139 IRQ_DMA4_LEVEL);
140
141 /* route external interrupts */
142 set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL,
143 IRQ_XIRQ4_LEVEL);
144 set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL,
145 IRQ_XIRQ0_LEVEL);
146
147#if defined(CONFIG_MB93091_VDK)
148 __set_TM1(0x55550000); /* XIRQ7-0 all active low */
149#elif defined(CONFIG_MB93093_PDK)
150 __set_TM1(0x15550000); /* XIRQ7 active high, 6-0 all active low */
151#else
152#error dont know external IRQ trigger levels for this setup
153#endif
154
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155 fpga_init();
156#ifdef CONFIG_FUJITSU_MB93493
David Howells1bcbba32006-09-25 23:32:04 -0700157 mb93493_init();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158#endif
David Howells1bcbba32006-09-25 23:32:04 -0700159}