Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Maxime Jayat | 3f79410 | 2013-10-12 01:29:46 +0200 | [diff] [blame] | 2 | * Routines to identify caches on Intel CPU. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
Ingo Molnar | cdcf772 | 2008-07-28 16:20:08 +0200 | [diff] [blame] | 4 | * Changes: |
| 5 | * Venkatesh Pallipadi : Adding cache identification through cpuid(4) |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 6 | * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure. |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 7 | * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | */ |
| 9 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | #include <linux/slab.h> |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 11 | #include <linux/cacheinfo.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <linux/cpu.h> |
Tim Schmielau | 4e57b68 | 2005-10-30 15:03:48 -0800 | [diff] [blame] | 13 | #include <linux/sched.h> |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 14 | #include <linux/sysfs.h> |
Mark Langsdorf | a24e8d3 | 2008-07-22 13:06:02 -0500 | [diff] [blame] | 15 | #include <linux/pci.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
| 17 | #include <asm/processor.h> |
Andreas Herrmann | 23ac4ae | 2010-09-17 18:03:43 +0200 | [diff] [blame] | 18 | #include <asm/amd_nb.h> |
Borislav Petkov | dcf39da | 2010-01-22 16:01:05 +0100 | [diff] [blame] | 19 | #include <asm/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
| 21 | #define LVL_1_INST 1 |
| 22 | #define LVL_1_DATA 2 |
| 23 | #define LVL_2 3 |
| 24 | #define LVL_3 4 |
| 25 | #define LVL_TRACE 5 |
| 26 | |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 27 | struct _cache_table { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | unsigned char descriptor; |
| 29 | char cache_type; |
| 30 | short size; |
| 31 | }; |
| 32 | |
Dave Jones | 2ca49b2 | 2010-01-04 09:47:35 -0500 | [diff] [blame] | 33 | #define MB(x) ((x) * 1024) |
| 34 | |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 35 | /* All the cache descriptor types we care about (no TLB or |
| 36 | trace cache entries) */ |
| 37 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 38 | static const struct _cache_table cache_table[] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | { |
| 40 | { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */ |
| 41 | { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */ |
Dave Jones | 9a8ecae | 2009-01-31 20:12:14 -0500 | [diff] [blame] | 42 | { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */ |
| 44 | { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */ |
Dave Jones | 9a8ecae | 2009-01-31 20:12:14 -0500 | [diff] [blame] | 45 | { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */ |
Dave Jones | fb87ec3 | 2011-01-19 20:20:56 -0500 | [diff] [blame] | 46 | { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */ |
Dave Jones | 9a8ecae | 2009-01-31 20:12:14 -0500 | [diff] [blame] | 47 | { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */ |
Dave Jones | 2ca49b2 | 2010-01-04 09:47:35 -0500 | [diff] [blame] | 49 | { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */ |
| 50 | { 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */ |
| 51 | { 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */ |
| 53 | { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */ |
| 54 | { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */ |
Dave Jones | 6fe8f47 | 2006-01-26 22:40:40 -0800 | [diff] [blame] | 55 | { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */ |
| 57 | { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */ |
Dave Jones | 6fe8f47 | 2006-01-26 22:40:40 -0800 | [diff] [blame] | 58 | { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */ |
| 59 | { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */ |
Jason Gaston | 04fa11e | 2007-12-21 01:27:19 +0100 | [diff] [blame] | 60 | { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */ |
| 62 | { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */ |
| 63 | { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */ |
Dave Jones | 2ca49b2 | 2010-01-04 09:47:35 -0500 | [diff] [blame] | 64 | { 0x44, LVL_2, MB(1) }, /* 4-way set assoc, 32 byte line size */ |
| 65 | { 0x45, LVL_2, MB(2) }, /* 4-way set assoc, 32 byte line size */ |
| 66 | { 0x46, LVL_3, MB(4) }, /* 4-way set assoc, 64 byte line size */ |
| 67 | { 0x47, LVL_3, MB(8) }, /* 8-way set assoc, 64 byte line size */ |
Dave Jones | fb87ec3 | 2011-01-19 20:20:56 -0500 | [diff] [blame] | 68 | { 0x48, LVL_2, MB(3) }, /* 12-way set assoc, 64 byte line size */ |
Dave Jones | 2ca49b2 | 2010-01-04 09:47:35 -0500 | [diff] [blame] | 69 | { 0x49, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */ |
| 70 | { 0x4a, LVL_3, MB(6) }, /* 12-way set assoc, 64 byte line size */ |
| 71 | { 0x4b, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */ |
| 72 | { 0x4c, LVL_3, MB(12) }, /* 12-way set assoc, 64 byte line size */ |
| 73 | { 0x4d, LVL_3, MB(16) }, /* 16-way set assoc, 64 byte line size */ |
| 74 | { 0x4e, LVL_2, MB(6) }, /* 24-way set assoc, 64 byte line size */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */ |
| 76 | { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */ |
| 77 | { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */ |
| 78 | { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */ |
| 79 | { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */ |
| 80 | { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */ |
| 81 | { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */ |
Dave Jones | 6fe8f47 | 2006-01-26 22:40:40 -0800 | [diff] [blame] | 82 | { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */ |
Dave Jones | 2ca49b2 | 2010-01-04 09:47:35 -0500 | [diff] [blame] | 83 | { 0x78, LVL_2, MB(1) }, /* 4-way set assoc, 64 byte line size */ |
| 84 | { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */ |
| 85 | { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */ |
| 86 | { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */ |
| 87 | { 0x7c, LVL_2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */ |
| 88 | { 0x7d, LVL_2, MB(2) }, /* 8-way set assoc, 64 byte line size */ |
| 89 | { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */ |
Dave Jones | fb87ec3 | 2011-01-19 20:20:56 -0500 | [diff] [blame] | 90 | { 0x80, LVL_2, 512 }, /* 8-way set assoc, 64 byte line size */ |
Dave Jones | 2ca49b2 | 2010-01-04 09:47:35 -0500 | [diff] [blame] | 91 | { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */ |
| 92 | { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */ |
| 93 | { 0x84, LVL_2, MB(1) }, /* 8-way set assoc, 32 byte line size */ |
| 94 | { 0x85, LVL_2, MB(2) }, /* 8-way set assoc, 32 byte line size */ |
| 95 | { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */ |
| 96 | { 0x87, LVL_2, MB(1) }, /* 8-way set assoc, 64 byte line size */ |
| 97 | { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */ |
| 98 | { 0xd1, LVL_3, MB(1) }, /* 4-way set assoc, 64 byte line size */ |
| 99 | { 0xd2, LVL_3, MB(2) }, /* 4-way set assoc, 64 byte line size */ |
| 100 | { 0xd6, LVL_3, MB(1) }, /* 8-way set assoc, 64 byte line size */ |
| 101 | { 0xd7, LVL_3, MB(2) }, /* 8-way set assoc, 64 byte line size */ |
| 102 | { 0xd8, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */ |
| 103 | { 0xdc, LVL_3, MB(2) }, /* 12-way set assoc, 64 byte line size */ |
| 104 | { 0xdd, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */ |
| 105 | { 0xde, LVL_3, MB(8) }, /* 12-way set assoc, 64 byte line size */ |
| 106 | { 0xe2, LVL_3, MB(2) }, /* 16-way set assoc, 64 byte line size */ |
| 107 | { 0xe3, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */ |
| 108 | { 0xe4, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */ |
| 109 | { 0xea, LVL_3, MB(12) }, /* 24-way set assoc, 64 byte line size */ |
| 110 | { 0xeb, LVL_3, MB(18) }, /* 24-way set assoc, 64 byte line size */ |
| 111 | { 0xec, LVL_3, MB(24) }, /* 24-way set assoc, 64 byte line size */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | { 0x00, 0, 0} |
| 113 | }; |
| 114 | |
| 115 | |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 116 | enum _cache_type { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 117 | CTYPE_NULL = 0, |
| 118 | CTYPE_DATA = 1, |
| 119 | CTYPE_INST = 2, |
| 120 | CTYPE_UNIFIED = 3 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 | }; |
| 122 | |
| 123 | union _cpuid4_leaf_eax { |
| 124 | struct { |
| 125 | enum _cache_type type:5; |
| 126 | unsigned int level:3; |
| 127 | unsigned int is_self_initializing:1; |
| 128 | unsigned int is_fully_associative:1; |
| 129 | unsigned int reserved:4; |
| 130 | unsigned int num_threads_sharing:12; |
| 131 | unsigned int num_cores_on_die:6; |
| 132 | } split; |
| 133 | u32 full; |
| 134 | }; |
| 135 | |
| 136 | union _cpuid4_leaf_ebx { |
| 137 | struct { |
| 138 | unsigned int coherency_line_size:12; |
| 139 | unsigned int physical_line_partition:10; |
| 140 | unsigned int ways_of_associativity:10; |
| 141 | } split; |
| 142 | u32 full; |
| 143 | }; |
| 144 | |
| 145 | union _cpuid4_leaf_ecx { |
| 146 | struct { |
| 147 | unsigned int number_of_sets:32; |
| 148 | } split; |
| 149 | u32 full; |
| 150 | }; |
| 151 | |
Mike Travis | f9b9056 | 2009-01-10 21:58:10 -0800 | [diff] [blame] | 152 | struct _cpuid4_info_regs { |
| 153 | union _cpuid4_leaf_eax eax; |
| 154 | union _cpuid4_leaf_ebx ebx; |
| 155 | union _cpuid4_leaf_ecx ecx; |
| 156 | unsigned long size; |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 157 | struct amd_northbridge *nb; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | }; |
| 159 | |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 160 | unsigned short num_cache_leaves; |
| 161 | |
| 162 | /* AMD doesn't have CPUID4. Emulate it here to report the same |
| 163 | information to the user. This makes some assumptions about the machine: |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 164 | L2 not shared, no SMT etc. that is currently true on AMD CPUs. |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 165 | |
| 166 | In theory the TLBs could be reported as fake type (they are in "dummy"). |
| 167 | Maybe later */ |
| 168 | union l1_cache { |
| 169 | struct { |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 170 | unsigned line_size:8; |
| 171 | unsigned lines_per_tag:8; |
| 172 | unsigned assoc:8; |
| 173 | unsigned size_in_kb:8; |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 174 | }; |
| 175 | unsigned val; |
| 176 | }; |
| 177 | |
| 178 | union l2_cache { |
| 179 | struct { |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 180 | unsigned line_size:8; |
| 181 | unsigned lines_per_tag:4; |
| 182 | unsigned assoc:4; |
| 183 | unsigned size_in_kb:16; |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 184 | }; |
| 185 | unsigned val; |
| 186 | }; |
| 187 | |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 188 | union l3_cache { |
| 189 | struct { |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 190 | unsigned line_size:8; |
| 191 | unsigned lines_per_tag:4; |
| 192 | unsigned assoc:4; |
| 193 | unsigned res:2; |
| 194 | unsigned size_encoded:14; |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 195 | }; |
| 196 | unsigned val; |
| 197 | }; |
| 198 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 199 | static const unsigned short assocs[] = { |
Andreas Herrmann | 6265ff1 | 2009-04-09 15:47:10 +0200 | [diff] [blame] | 200 | [1] = 1, |
| 201 | [2] = 2, |
| 202 | [4] = 4, |
| 203 | [6] = 8, |
| 204 | [8] = 16, |
| 205 | [0xa] = 32, |
| 206 | [0xb] = 48, |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 207 | [0xc] = 64, |
Andreas Herrmann | 6265ff1 | 2009-04-09 15:47:10 +0200 | [diff] [blame] | 208 | [0xd] = 96, |
| 209 | [0xe] = 128, |
| 210 | [0xf] = 0xffff /* fully associative - no way to show this currently */ |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 211 | }; |
| 212 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 213 | static const unsigned char levels[] = { 1, 1, 2, 3 }; |
| 214 | static const unsigned char types[] = { 1, 2, 3, 3 }; |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 215 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 216 | static const enum cache_type cache_type_map[] = { |
| 217 | [CTYPE_NULL] = CACHE_TYPE_NOCACHE, |
| 218 | [CTYPE_DATA] = CACHE_TYPE_DATA, |
| 219 | [CTYPE_INST] = CACHE_TYPE_INST, |
| 220 | [CTYPE_UNIFIED] = CACHE_TYPE_UNIFIED, |
| 221 | }; |
| 222 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 223 | static void |
Ingo Molnar | cdcf772 | 2008-07-28 16:20:08 +0200 | [diff] [blame] | 224 | amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, |
| 225 | union _cpuid4_leaf_ebx *ebx, |
| 226 | union _cpuid4_leaf_ecx *ecx) |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 227 | { |
| 228 | unsigned dummy; |
| 229 | unsigned line_size, lines_per_tag, assoc, size_in_kb; |
| 230 | union l1_cache l1i, l1d; |
| 231 | union l2_cache l2; |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 232 | union l3_cache l3; |
| 233 | union l1_cache *l1 = &l1d; |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 234 | |
| 235 | eax->full = 0; |
| 236 | ebx->full = 0; |
| 237 | ecx->full = 0; |
| 238 | |
| 239 | cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val); |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 240 | cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 241 | |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 242 | switch (leaf) { |
| 243 | case 1: |
| 244 | l1 = &l1i; |
| 245 | case 0: |
| 246 | if (!l1->val) |
| 247 | return; |
Andreas Herrmann | a326e94 | 2009-09-03 09:41:19 +0200 | [diff] [blame] | 248 | assoc = assocs[l1->assoc]; |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 249 | line_size = l1->line_size; |
| 250 | lines_per_tag = l1->lines_per_tag; |
| 251 | size_in_kb = l1->size_in_kb; |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 252 | break; |
| 253 | case 2: |
| 254 | if (!l2.val) |
| 255 | return; |
Andreas Herrmann | a326e94 | 2009-09-03 09:41:19 +0200 | [diff] [blame] | 256 | assoc = assocs[l2.assoc]; |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 257 | line_size = l2.line_size; |
| 258 | lines_per_tag = l2.lines_per_tag; |
| 259 | /* cpu_data has errata corrections for K7 applied */ |
Tejun Heo | 7b543a5 | 2010-12-18 16:30:05 +0100 | [diff] [blame] | 260 | size_in_kb = __this_cpu_read(cpu_info.x86_cache_size); |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 261 | break; |
| 262 | case 3: |
| 263 | if (!l3.val) |
| 264 | return; |
Andreas Herrmann | a326e94 | 2009-09-03 09:41:19 +0200 | [diff] [blame] | 265 | assoc = assocs[l3.assoc]; |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 266 | line_size = l3.line_size; |
| 267 | lines_per_tag = l3.lines_per_tag; |
| 268 | size_in_kb = l3.size_encoded * 512; |
Andreas Herrmann | a326e94 | 2009-09-03 09:41:19 +0200 | [diff] [blame] | 269 | if (boot_cpu_has(X86_FEATURE_AMD_DCM)) { |
| 270 | size_in_kb = size_in_kb >> 1; |
| 271 | assoc = assoc >> 1; |
| 272 | } |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 273 | break; |
| 274 | default: |
| 275 | return; |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 276 | } |
| 277 | |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 278 | eax->split.is_self_initializing = 1; |
| 279 | eax->split.type = types[leaf]; |
| 280 | eax->split.level = levels[leaf]; |
Andreas Herrmann | a326e94 | 2009-09-03 09:41:19 +0200 | [diff] [blame] | 281 | eax->split.num_threads_sharing = 0; |
Tejun Heo | 7b543a5 | 2010-12-18 16:30:05 +0100 | [diff] [blame] | 282 | eax->split.num_cores_on_die = __this_cpu_read(cpu_info.x86_max_cores) - 1; |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 283 | |
| 284 | |
Andreas Herrmann | a326e94 | 2009-09-03 09:41:19 +0200 | [diff] [blame] | 285 | if (assoc == 0xffff) |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 286 | eax->split.is_fully_associative = 1; |
| 287 | ebx->split.coherency_line_size = line_size - 1; |
Andreas Herrmann | a326e94 | 2009-09-03 09:41:19 +0200 | [diff] [blame] | 288 | ebx->split.ways_of_associativity = assoc - 1; |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 289 | ebx->split.physical_line_partition = lines_per_tag - 1; |
| 290 | ecx->split.number_of_sets = (size_in_kb * 1024) / line_size / |
| 291 | (ebx->split.ways_of_associativity + 1) - 1; |
| 292 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | |
Borislav Petkov | f76e39c | 2013-02-04 10:13:15 +0100 | [diff] [blame] | 294 | #if defined(CONFIG_AMD_NB) && defined(CONFIG_SYSFS) |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 295 | |
Borislav Petkov | ba06edb | 2010-04-22 16:07:01 +0200 | [diff] [blame] | 296 | /* |
| 297 | * L3 cache descriptors |
| 298 | */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 299 | static void amd_calc_l3_indices(struct amd_northbridge *nb) |
Borislav Petkov | 048a877 | 2010-01-22 16:01:07 +0100 | [diff] [blame] | 300 | { |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 301 | struct amd_l3_cache *l3 = &nb->l3_cache; |
Borislav Petkov | 048a877 | 2010-01-22 16:01:07 +0100 | [diff] [blame] | 302 | unsigned int sc0, sc1, sc2, sc3; |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 303 | u32 val = 0; |
Borislav Petkov | 048a877 | 2010-01-22 16:01:07 +0100 | [diff] [blame] | 304 | |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 305 | pci_read_config_dword(nb->misc, 0x1C4, &val); |
Borislav Petkov | 048a877 | 2010-01-22 16:01:07 +0100 | [diff] [blame] | 306 | |
| 307 | /* calculate subcache sizes */ |
Borislav Petkov | 9350f98 | 2010-04-22 16:07:00 +0200 | [diff] [blame] | 308 | l3->subcaches[0] = sc0 = !(val & BIT(0)); |
| 309 | l3->subcaches[1] = sc1 = !(val & BIT(4)); |
Frank Arnold | 77e75fc | 2011-05-18 11:32:10 +0200 | [diff] [blame] | 310 | |
| 311 | if (boot_cpu_data.x86 == 0x15) { |
| 312 | l3->subcaches[0] = sc0 += !(val & BIT(1)); |
| 313 | l3->subcaches[1] = sc1 += !(val & BIT(5)); |
| 314 | } |
| 315 | |
Borislav Petkov | 9350f98 | 2010-04-22 16:07:00 +0200 | [diff] [blame] | 316 | l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9)); |
| 317 | l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13)); |
Borislav Petkov | 048a877 | 2010-01-22 16:01:07 +0100 | [diff] [blame] | 318 | |
Hagen Paul Pfeifer | 732eacc | 2010-10-26 14:22:23 -0700 | [diff] [blame] | 319 | l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1; |
Borislav Petkov | ba06edb | 2010-04-22 16:07:01 +0200 | [diff] [blame] | 320 | } |
| 321 | |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 322 | /* |
| 323 | * check whether a slot used for disabling an L3 index is occupied. |
| 324 | * @l3: L3 cache descriptor |
| 325 | * @slot: slot number (0..1) |
| 326 | * |
| 327 | * @returns: the disabled index if used or negative value if slot free. |
| 328 | */ |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 329 | int amd_get_l3_disable_slot(struct amd_northbridge *nb, unsigned slot) |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 330 | { |
| 331 | unsigned int reg = 0; |
| 332 | |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 333 | pci_read_config_dword(nb->misc, 0x1BC + slot * 4, ®); |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 334 | |
| 335 | /* check whether this slot is activated already */ |
| 336 | if (reg & (3UL << 30)) |
| 337 | return reg & 0xfff; |
| 338 | |
| 339 | return -1; |
| 340 | } |
| 341 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 342 | static ssize_t show_cache_disable(struct cacheinfo *this_leaf, char *buf, |
Borislav Petkov | 59d3b38 | 2010-04-22 16:07:02 +0200 | [diff] [blame] | 343 | unsigned int slot) |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 344 | { |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 345 | int index; |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 346 | struct amd_northbridge *nb = this_leaf->priv; |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 347 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 348 | index = amd_get_l3_disable_slot(nb, slot); |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 349 | if (index >= 0) |
| 350 | return sprintf(buf, "%d\n", index); |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 351 | |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 352 | return sprintf(buf, "FREE\n"); |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 353 | } |
| 354 | |
Borislav Petkov | 59d3b38 | 2010-04-22 16:07:02 +0200 | [diff] [blame] | 355 | #define SHOW_CACHE_DISABLE(slot) \ |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 356 | static ssize_t \ |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 357 | cache_disable_##slot##_show(struct device *dev, \ |
| 358 | struct device_attribute *attr, char *buf) \ |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 359 | { \ |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 360 | struct cacheinfo *this_leaf = dev_get_drvdata(dev); \ |
Borislav Petkov | 59d3b38 | 2010-04-22 16:07:02 +0200 | [diff] [blame] | 361 | return show_cache_disable(this_leaf, buf, slot); \ |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 362 | } |
| 363 | SHOW_CACHE_DISABLE(0) |
| 364 | SHOW_CACHE_DISABLE(1) |
| 365 | |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 366 | static void amd_l3_disable_index(struct amd_northbridge *nb, int cpu, |
Borislav Petkov | 59d3b38 | 2010-04-22 16:07:02 +0200 | [diff] [blame] | 367 | unsigned slot, unsigned long idx) |
| 368 | { |
| 369 | int i; |
| 370 | |
| 371 | idx |= BIT(30); |
| 372 | |
| 373 | /* |
| 374 | * disable index in all 4 subcaches |
| 375 | */ |
| 376 | for (i = 0; i < 4; i++) { |
| 377 | u32 reg = idx | (i << 20); |
| 378 | |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 379 | if (!nb->l3_cache.subcaches[i]) |
Borislav Petkov | 59d3b38 | 2010-04-22 16:07:02 +0200 | [diff] [blame] | 380 | continue; |
| 381 | |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 382 | pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg); |
Borislav Petkov | 59d3b38 | 2010-04-22 16:07:02 +0200 | [diff] [blame] | 383 | |
| 384 | /* |
| 385 | * We need to WBINVD on a core on the node containing the L3 |
| 386 | * cache which indices we disable therefore a simple wbinvd() |
| 387 | * is not sufficient. |
| 388 | */ |
| 389 | wbinvd_on_cpu(cpu); |
| 390 | |
| 391 | reg |= BIT(31); |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 392 | pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg); |
Borislav Petkov | 59d3b38 | 2010-04-22 16:07:02 +0200 | [diff] [blame] | 393 | } |
| 394 | } |
| 395 | |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 396 | /* |
| 397 | * disable a L3 cache index by using a disable-slot |
| 398 | * |
| 399 | * @l3: L3 cache descriptor |
| 400 | * @cpu: A CPU on the node containing the L3 cache |
| 401 | * @slot: slot number (0..1) |
| 402 | * @index: index to disable |
| 403 | * |
| 404 | * @return: 0 on success, error status on failure |
| 405 | */ |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 406 | int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot, |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 407 | unsigned long index) |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 408 | { |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 409 | int ret = 0; |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 410 | |
Frank Arnold | 42be450 | 2011-05-16 15:39:47 +0200 | [diff] [blame] | 411 | /* check if @slot is already used or the index is already disabled */ |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 412 | ret = amd_get_l3_disable_slot(nb, slot); |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 413 | if (ret >= 0) |
Srivatsa S. Bhat | a720b2d | 2012-04-19 12:35:08 +0200 | [diff] [blame] | 414 | return -EEXIST; |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 415 | |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 416 | if (index > nb->l3_cache.indices) |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 417 | return -EINVAL; |
| 418 | |
Frank Arnold | 42be450 | 2011-05-16 15:39:47 +0200 | [diff] [blame] | 419 | /* check whether the other slot has disabled the same index already */ |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 420 | if (index == amd_get_l3_disable_slot(nb, !slot)) |
Srivatsa S. Bhat | a720b2d | 2012-04-19 12:35:08 +0200 | [diff] [blame] | 421 | return -EEXIST; |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 422 | |
Thomas Gleixner | d294604 | 2011-07-24 09:46:09 +0000 | [diff] [blame] | 423 | amd_l3_disable_index(nb, cpu, slot, index); |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 424 | |
| 425 | return 0; |
| 426 | } |
| 427 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 428 | static ssize_t store_cache_disable(struct cacheinfo *this_leaf, |
| 429 | const char *buf, size_t count, |
| 430 | unsigned int slot) |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 431 | { |
| 432 | unsigned long val = 0; |
| 433 | int cpu, err = 0; |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 434 | struct amd_northbridge *nb = this_leaf->priv; |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 435 | |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 436 | if (!capable(CAP_SYS_ADMIN)) |
| 437 | return -EPERM; |
| 438 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 439 | cpu = cpumask_first(&this_leaf->shared_cpu_map); |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 440 | |
Daniel Walter | 164109e | 2014-08-08 14:24:03 -0700 | [diff] [blame] | 441 | if (kstrtoul(buf, 10, &val) < 0) |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 442 | return -EINVAL; |
| 443 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 444 | err = amd_set_l3_disable_slot(nb, cpu, slot, val); |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 445 | if (err) { |
| 446 | if (err == -EEXIST) |
Srivatsa S. Bhat | a720b2d | 2012-04-19 12:35:08 +0200 | [diff] [blame] | 447 | pr_warning("L3 slot %d in use/index already disabled!\n", |
| 448 | slot); |
Borislav Petkov | 8cc1176 | 2010-06-02 18:18:40 +0200 | [diff] [blame] | 449 | return err; |
| 450 | } |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 451 | return count; |
| 452 | } |
| 453 | |
Borislav Petkov | 59d3b38 | 2010-04-22 16:07:02 +0200 | [diff] [blame] | 454 | #define STORE_CACHE_DISABLE(slot) \ |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 455 | static ssize_t \ |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 456 | cache_disable_##slot##_store(struct device *dev, \ |
| 457 | struct device_attribute *attr, \ |
| 458 | const char *buf, size_t count) \ |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 459 | { \ |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 460 | struct cacheinfo *this_leaf = dev_get_drvdata(dev); \ |
Borislav Petkov | 59d3b38 | 2010-04-22 16:07:02 +0200 | [diff] [blame] | 461 | return store_cache_disable(this_leaf, buf, count, slot); \ |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 462 | } |
| 463 | STORE_CACHE_DISABLE(0) |
| 464 | STORE_CACHE_DISABLE(1) |
| 465 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 466 | static ssize_t subcaches_show(struct device *dev, |
| 467 | struct device_attribute *attr, char *buf) |
Hans Rosenfeld | cabb5bd | 2011-02-07 18:10:39 +0100 | [diff] [blame] | 468 | { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 469 | struct cacheinfo *this_leaf = dev_get_drvdata(dev); |
| 470 | int cpu = cpumask_first(&this_leaf->shared_cpu_map); |
Hans Rosenfeld | cabb5bd | 2011-02-07 18:10:39 +0100 | [diff] [blame] | 471 | |
| 472 | return sprintf(buf, "%x\n", amd_get_subcaches(cpu)); |
| 473 | } |
| 474 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 475 | static ssize_t subcaches_store(struct device *dev, |
| 476 | struct device_attribute *attr, |
| 477 | const char *buf, size_t count) |
Hans Rosenfeld | cabb5bd | 2011-02-07 18:10:39 +0100 | [diff] [blame] | 478 | { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 479 | struct cacheinfo *this_leaf = dev_get_drvdata(dev); |
| 480 | int cpu = cpumask_first(&this_leaf->shared_cpu_map); |
Hans Rosenfeld | cabb5bd | 2011-02-07 18:10:39 +0100 | [diff] [blame] | 481 | unsigned long val; |
| 482 | |
| 483 | if (!capable(CAP_SYS_ADMIN)) |
| 484 | return -EPERM; |
| 485 | |
Daniel Walter | 164109e | 2014-08-08 14:24:03 -0700 | [diff] [blame] | 486 | if (kstrtoul(buf, 16, &val) < 0) |
Hans Rosenfeld | cabb5bd | 2011-02-07 18:10:39 +0100 | [diff] [blame] | 487 | return -EINVAL; |
| 488 | |
| 489 | if (amd_set_subcaches(cpu, val)) |
| 490 | return -EINVAL; |
| 491 | |
| 492 | return count; |
| 493 | } |
| 494 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 495 | static DEVICE_ATTR_RW(cache_disable_0); |
| 496 | static DEVICE_ATTR_RW(cache_disable_1); |
| 497 | static DEVICE_ATTR_RW(subcaches); |
Hans Rosenfeld | cabb5bd | 2011-02-07 18:10:39 +0100 | [diff] [blame] | 498 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 499 | static umode_t |
| 500 | cache_private_attrs_is_visible(struct kobject *kobj, |
| 501 | struct attribute *attr, int unused) |
| 502 | { |
| 503 | struct device *dev = kobj_to_dev(kobj); |
| 504 | struct cacheinfo *this_leaf = dev_get_drvdata(dev); |
| 505 | umode_t mode = attr->mode; |
| 506 | |
| 507 | if (!this_leaf->priv) |
| 508 | return 0; |
| 509 | |
| 510 | if ((attr == &dev_attr_subcaches.attr) && |
| 511 | amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) |
| 512 | return mode; |
| 513 | |
| 514 | if ((attr == &dev_attr_cache_disable_0.attr || |
| 515 | attr == &dev_attr_cache_disable_1.attr) && |
| 516 | amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) |
| 517 | return mode; |
| 518 | |
| 519 | return 0; |
| 520 | } |
| 521 | |
| 522 | static struct attribute_group cache_private_group = { |
| 523 | .is_visible = cache_private_attrs_is_visible, |
| 524 | }; |
| 525 | |
| 526 | static void init_amd_l3_attrs(void) |
| 527 | { |
| 528 | int n = 1; |
| 529 | static struct attribute **amd_l3_attrs; |
| 530 | |
| 531 | if (amd_l3_attrs) /* already initialized */ |
| 532 | return; |
| 533 | |
| 534 | if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) |
| 535 | n += 2; |
| 536 | if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) |
| 537 | n += 1; |
| 538 | |
| 539 | amd_l3_attrs = kcalloc(n, sizeof(*amd_l3_attrs), GFP_KERNEL); |
| 540 | if (!amd_l3_attrs) |
| 541 | return; |
| 542 | |
| 543 | n = 0; |
| 544 | if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) { |
| 545 | amd_l3_attrs[n++] = &dev_attr_cache_disable_0.attr; |
| 546 | amd_l3_attrs[n++] = &dev_attr_cache_disable_1.attr; |
| 547 | } |
| 548 | if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) |
| 549 | amd_l3_attrs[n++] = &dev_attr_subcaches.attr; |
| 550 | |
| 551 | cache_private_group.attrs = amd_l3_attrs; |
| 552 | } |
| 553 | |
| 554 | const struct attribute_group * |
| 555 | cache_get_priv_group(struct cacheinfo *this_leaf) |
| 556 | { |
| 557 | struct amd_northbridge *nb = this_leaf->priv; |
| 558 | |
Sudeep Holla | 37dea8c | 2015-03-11 11:54:29 +0100 | [diff] [blame] | 559 | if (this_leaf->level < 3 || !nb) |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 560 | return NULL; |
| 561 | |
| 562 | if (nb && nb->l3_cache.indices) |
| 563 | init_amd_l3_attrs(); |
| 564 | |
| 565 | return &cache_private_group; |
| 566 | } |
| 567 | |
| 568 | static void amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf, int index) |
| 569 | { |
| 570 | int node; |
| 571 | |
| 572 | /* only for L3, and not in virtualized environments */ |
| 573 | if (index < 3) |
| 574 | return; |
| 575 | |
| 576 | node = amd_get_nb_id(smp_processor_id()); |
| 577 | this_leaf->nb = node_to_amd_nb(node); |
| 578 | if (this_leaf->nb && !this_leaf->nb->l3_cache.indices) |
| 579 | amd_calc_l3_indices(this_leaf->nb); |
| 580 | } |
Borislav Petkov | f76e39c | 2013-02-04 10:13:15 +0100 | [diff] [blame] | 581 | #else |
Hans Rosenfeld | f658bcf | 2010-10-29 17:14:32 +0200 | [diff] [blame] | 582 | #define amd_init_l3_cache(x, y) |
Borislav Petkov | f76e39c | 2013-02-04 10:13:15 +0100 | [diff] [blame] | 583 | #endif /* CONFIG_AMD_NB && CONFIG_SYSFS */ |
Borislav Petkov | cb19060 | 2010-02-18 19:37:14 +0100 | [diff] [blame] | 584 | |
Ingo Molnar | 7a4983b | 2008-07-21 13:34:21 +0200 | [diff] [blame] | 585 | static int |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 586 | cpuid4_cache_lookup_regs(int index, struct _cpuid4_info_regs *this_leaf) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 587 | { |
Hans Rosenfeld | cabb5bd | 2011-02-07 18:10:39 +0100 | [diff] [blame] | 588 | union _cpuid4_leaf_eax eax; |
| 589 | union _cpuid4_leaf_ebx ebx; |
| 590 | union _cpuid4_leaf_ecx ecx; |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 591 | unsigned edx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 592 | |
Mark Langsdorf | 8cb22bc | 2008-07-18 16:03:52 -0500 | [diff] [blame] | 593 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { |
Andreas Herrmann | 2e8458d | 2012-10-19 11:00:49 +0200 | [diff] [blame] | 594 | if (cpu_has_topoext) |
| 595 | cpuid_count(0x8000001d, index, &eax.full, |
| 596 | &ebx.full, &ecx.full, &edx); |
| 597 | else |
| 598 | amd_cpuid4(index, &eax, &ebx, &ecx); |
Hans Rosenfeld | f658bcf | 2010-10-29 17:14:32 +0200 | [diff] [blame] | 599 | amd_init_l3_cache(this_leaf, index); |
Ingo Molnar | 7a4983b | 2008-07-21 13:34:21 +0200 | [diff] [blame] | 600 | } else { |
| 601 | cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx); |
| 602 | } |
| 603 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 604 | if (eax.split.type == CTYPE_NULL) |
Andi Kleen | e2cac78 | 2005-07-28 21:15:46 -0700 | [diff] [blame] | 605 | return -EIO; /* better error ? */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 606 | |
Andi Kleen | 240cd6a80 | 2006-06-26 13:56:13 +0200 | [diff] [blame] | 607 | this_leaf->eax = eax; |
| 608 | this_leaf->ebx = ebx; |
| 609 | this_leaf->ecx = ecx; |
Ingo Molnar | 7a4983b | 2008-07-21 13:34:21 +0200 | [diff] [blame] | 610 | this_leaf->size = (ecx.split.number_of_sets + 1) * |
| 611 | (ebx.split.coherency_line_size + 1) * |
| 612 | (ebx.split.physical_line_partition + 1) * |
| 613 | (ebx.split.ways_of_associativity + 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | return 0; |
| 615 | } |
| 616 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 617 | static int find_num_cache_leaves(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | { |
Andreas Herrmann | 04a1541 | 2012-10-19 10:59:33 +0200 | [diff] [blame] | 619 | unsigned int eax, ebx, ecx, edx, op; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | union _cpuid4_leaf_eax cache_eax; |
Siddha, Suresh B | d16aafff | 2005-10-30 14:59:30 -0800 | [diff] [blame] | 621 | int i = -1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | |
Andreas Herrmann | 04a1541 | 2012-10-19 10:59:33 +0200 | [diff] [blame] | 623 | if (c->x86_vendor == X86_VENDOR_AMD) |
| 624 | op = 0x8000001d; |
| 625 | else |
| 626 | op = 4; |
| 627 | |
Siddha, Suresh B | d16aafff | 2005-10-30 14:59:30 -0800 | [diff] [blame] | 628 | do { |
| 629 | ++i; |
Andreas Herrmann | 04a1541 | 2012-10-19 10:59:33 +0200 | [diff] [blame] | 630 | /* Do cpuid(op) loop to find out num_cache_leaves */ |
| 631 | cpuid_count(op, i, &eax, &ebx, &ecx, &edx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 632 | cache_eax.full = eax; |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 633 | } while (cache_eax.split.type != CTYPE_NULL); |
Siddha, Suresh B | d16aafff | 2005-10-30 14:59:30 -0800 | [diff] [blame] | 634 | return i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 635 | } |
| 636 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 637 | void init_amd_cacheinfo(struct cpuinfo_x86 *c) |
Andreas Herrmann | 04a1541 | 2012-10-19 10:59:33 +0200 | [diff] [blame] | 638 | { |
| 639 | |
| 640 | if (cpu_has_topoext) { |
| 641 | num_cache_leaves = find_num_cache_leaves(c); |
| 642 | } else if (c->extended_cpuid_level >= 0x80000006) { |
| 643 | if (cpuid_edx(0x80000006) & 0xf000) |
| 644 | num_cache_leaves = 4; |
| 645 | else |
| 646 | num_cache_leaves = 3; |
| 647 | } |
| 648 | } |
| 649 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 650 | unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 651 | { |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 652 | /* Cache sizes */ |
| 653 | unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */ |
| 655 | unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */ |
Siddha, Suresh B | 1e9f28f | 2006-03-27 01:15:22 -0800 | [diff] [blame] | 656 | unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb; |
James Bottomley | 96c5274 | 2006-06-27 02:53:49 -0700 | [diff] [blame] | 657 | #ifdef CONFIG_X86_HT |
Mike Travis | 92cb761 | 2007-10-19 20:35:04 +0200 | [diff] [blame] | 658 | unsigned int cpu = c->cpu_index; |
Siddha, Suresh B | 1e9f28f | 2006-03-27 01:15:22 -0800 | [diff] [blame] | 659 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | |
Shaohua Li | f2d0d26 | 2006-03-23 02:59:52 -0800 | [diff] [blame] | 661 | if (c->cpuid_level > 3) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | static int is_initialized; |
| 663 | |
| 664 | if (is_initialized == 0) { |
| 665 | /* Init num_cache_leaves from boot CPU */ |
Andreas Herrmann | 04a1541 | 2012-10-19 10:59:33 +0200 | [diff] [blame] | 666 | num_cache_leaves = find_num_cache_leaves(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 667 | is_initialized++; |
| 668 | } |
| 669 | |
| 670 | /* |
| 671 | * Whenever possible use cpuid(4), deterministic cache |
| 672 | * parameters cpuid leaf to find the cache details |
| 673 | */ |
| 674 | for (i = 0; i < num_cache_leaves; i++) { |
Borislav Petkov | 719038d | 2013-06-08 18:48:15 +0200 | [diff] [blame] | 675 | struct _cpuid4_info_regs this_leaf = {}; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 676 | int retval; |
| 677 | |
Mike Travis | f9b9056 | 2009-01-10 21:58:10 -0800 | [diff] [blame] | 678 | retval = cpuid4_cache_lookup_regs(i, &this_leaf); |
Borislav Petkov | 719038d | 2013-06-08 18:48:15 +0200 | [diff] [blame] | 679 | if (retval < 0) |
| 680 | continue; |
| 681 | |
| 682 | switch (this_leaf.eax.split.level) { |
| 683 | case 1: |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 684 | if (this_leaf.eax.split.type == CTYPE_DATA) |
Borislav Petkov | 719038d | 2013-06-08 18:48:15 +0200 | [diff] [blame] | 685 | new_l1d = this_leaf.size/1024; |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 686 | else if (this_leaf.eax.split.type == CTYPE_INST) |
Borislav Petkov | 719038d | 2013-06-08 18:48:15 +0200 | [diff] [blame] | 687 | new_l1i = this_leaf.size/1024; |
| 688 | break; |
| 689 | case 2: |
| 690 | new_l2 = this_leaf.size/1024; |
| 691 | num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing; |
| 692 | index_msb = get_count_order(num_threads_sharing); |
| 693 | l2_id = c->apicid & ~((1 << index_msb) - 1); |
| 694 | break; |
| 695 | case 3: |
| 696 | new_l3 = this_leaf.size/1024; |
| 697 | num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing; |
| 698 | index_msb = get_count_order(num_threads_sharing); |
| 699 | l3_id = c->apicid & ~((1 << index_msb) - 1); |
| 700 | break; |
| 701 | default: |
| 702 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 703 | } |
| 704 | } |
| 705 | } |
Shaohua Li | b06be912 | 2006-03-27 01:15:24 -0800 | [diff] [blame] | 706 | /* |
| 707 | * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for |
| 708 | * trace cache |
| 709 | */ |
| 710 | if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 711 | /* supports eax=2 call */ |
Harvey Harrison | c1666e6 | 2008-01-31 22:05:43 +0100 | [diff] [blame] | 712 | int j, n; |
| 713 | unsigned int regs[4]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 714 | unsigned char *dp = (unsigned char *)regs; |
Shaohua Li | b06be912 | 2006-03-27 01:15:24 -0800 | [diff] [blame] | 715 | int only_trace = 0; |
| 716 | |
| 717 | if (num_cache_leaves != 0 && c->x86 == 15) |
| 718 | only_trace = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 719 | |
| 720 | /* Number of times to iterate */ |
| 721 | n = cpuid_eax(2) & 0xFF; |
| 722 | |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 723 | for (i = 0 ; i < n ; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); |
| 725 | |
| 726 | /* If bit 31 is set, this is an unknown format */ |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 727 | for (j = 0 ; j < 3 ; j++) |
| 728 | if (regs[j] & (1 << 31)) |
| 729 | regs[j] = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 730 | |
| 731 | /* Byte 0 is level count, not a descriptor */ |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 732 | for (j = 1 ; j < 16 ; j++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 733 | unsigned char des = dp[j]; |
| 734 | unsigned char k = 0; |
| 735 | |
| 736 | /* look up this descriptor in the table */ |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 737 | while (cache_table[k].descriptor != 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 738 | if (cache_table[k].descriptor == des) { |
Shaohua Li | b06be912 | 2006-03-27 01:15:24 -0800 | [diff] [blame] | 739 | if (only_trace && cache_table[k].cache_type != LVL_TRACE) |
| 740 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 741 | switch (cache_table[k].cache_type) { |
| 742 | case LVL_1_INST: |
| 743 | l1i += cache_table[k].size; |
| 744 | break; |
| 745 | case LVL_1_DATA: |
| 746 | l1d += cache_table[k].size; |
| 747 | break; |
| 748 | case LVL_2: |
| 749 | l2 += cache_table[k].size; |
| 750 | break; |
| 751 | case LVL_3: |
| 752 | l3 += cache_table[k].size; |
| 753 | break; |
| 754 | case LVL_TRACE: |
| 755 | trace += cache_table[k].size; |
| 756 | break; |
| 757 | } |
| 758 | |
| 759 | break; |
| 760 | } |
| 761 | |
| 762 | k++; |
| 763 | } |
| 764 | } |
| 765 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 766 | } |
| 767 | |
Shaohua Li | b06be912 | 2006-03-27 01:15:24 -0800 | [diff] [blame] | 768 | if (new_l1d) |
| 769 | l1d = new_l1d; |
| 770 | |
| 771 | if (new_l1i) |
| 772 | l1i = new_l1i; |
| 773 | |
| 774 | if (new_l2) { |
| 775 | l2 = new_l2; |
James Bottomley | 96c5274 | 2006-06-27 02:53:49 -0700 | [diff] [blame] | 776 | #ifdef CONFIG_X86_HT |
Mike Travis | b627847 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 777 | per_cpu(cpu_llc_id, cpu) = l2_id; |
Shaohua Li | b06be912 | 2006-03-27 01:15:24 -0800 | [diff] [blame] | 778 | #endif |
| 779 | } |
| 780 | |
| 781 | if (new_l3) { |
| 782 | l3 = new_l3; |
James Bottomley | 96c5274 | 2006-06-27 02:53:49 -0700 | [diff] [blame] | 783 | #ifdef CONFIG_X86_HT |
Mike Travis | b627847 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 784 | per_cpu(cpu_llc_id, cpu) = l3_id; |
Shaohua Li | b06be912 | 2006-03-27 01:15:24 -0800 | [diff] [blame] | 785 | #endif |
| 786 | } |
| 787 | |
Peter Zijlstra | 2a22615 | 2014-07-22 15:35:14 +0200 | [diff] [blame] | 788 | #ifdef CONFIG_X86_HT |
| 789 | /* |
| 790 | * If cpu_llc_id is not yet set, this means cpuid_level < 4 which in |
| 791 | * turns means that the only possibility is SMT (as indicated in |
| 792 | * cpuid1). Since cpuid2 doesn't specify shared caches, and we know |
| 793 | * that SMT shares all caches, we can unconditionally set cpu_llc_id to |
| 794 | * c->phys_proc_id. |
| 795 | */ |
| 796 | if (per_cpu(cpu_llc_id, cpu) == BAD_APICID) |
| 797 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; |
| 798 | #endif |
| 799 | |
Shaohua Li | b06be912 | 2006-03-27 01:15:24 -0800 | [diff] [blame] | 800 | c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); |
| 801 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 802 | return l2; |
| 803 | } |
| 804 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 805 | static int __cache_amd_cpumap_setup(unsigned int cpu, int index, |
| 806 | struct _cpuid4_info_regs *base) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 807 | { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 808 | struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); |
| 809 | struct cacheinfo *this_leaf; |
Andreas Herrmann | 27d3a8a26 | 2012-10-19 11:02:09 +0200 | [diff] [blame] | 810 | int i, sibling; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | |
Andreas Herrmann | 27d3a8a26 | 2012-10-19 11:02:09 +0200 | [diff] [blame] | 812 | if (cpu_has_topoext) { |
| 813 | unsigned int apicid, nshared, first, last; |
| 814 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 815 | this_leaf = this_cpu_ci->info_list + index; |
| 816 | nshared = base->eax.split.num_threads_sharing + 1; |
Andreas Herrmann | 27d3a8a26 | 2012-10-19 11:02:09 +0200 | [diff] [blame] | 817 | apicid = cpu_data(cpu).apicid; |
| 818 | first = apicid - (apicid % nshared); |
| 819 | last = first + nshared - 1; |
| 820 | |
| 821 | for_each_online_cpu(i) { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 822 | this_cpu_ci = get_cpu_cacheinfo(i); |
| 823 | if (!this_cpu_ci->info_list) |
| 824 | continue; |
| 825 | |
Andreas Herrmann | 27d3a8a26 | 2012-10-19 11:02:09 +0200 | [diff] [blame] | 826 | apicid = cpu_data(i).apicid; |
| 827 | if ((apicid < first) || (apicid > last)) |
| 828 | continue; |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 829 | |
| 830 | this_leaf = this_cpu_ci->info_list + index; |
Andreas Herrmann | 27d3a8a26 | 2012-10-19 11:02:09 +0200 | [diff] [blame] | 831 | |
| 832 | for_each_online_cpu(sibling) { |
| 833 | apicid = cpu_data(sibling).apicid; |
| 834 | if ((apicid < first) || (apicid > last)) |
| 835 | continue; |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 836 | cpumask_set_cpu(sibling, |
| 837 | &this_leaf->shared_cpu_map); |
Andreas Herrmann | 27d3a8a26 | 2012-10-19 11:02:09 +0200 | [diff] [blame] | 838 | } |
| 839 | } |
| 840 | } else if (index == 3) { |
Yinghai Lu | b3d7336 | 2011-01-21 15:29:44 -0800 | [diff] [blame] | 841 | for_each_cpu(i, cpu_llc_shared_mask(cpu)) { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 842 | this_cpu_ci = get_cpu_cacheinfo(i); |
| 843 | if (!this_cpu_ci->info_list) |
Andreas Herrmann | a326e94 | 2009-09-03 09:41:19 +0200 | [diff] [blame] | 844 | continue; |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 845 | this_leaf = this_cpu_ci->info_list + index; |
Yinghai Lu | b3d7336 | 2011-01-21 15:29:44 -0800 | [diff] [blame] | 846 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) { |
Prarit Bhargava | ebb682f | 2009-12-09 13:36:45 -0500 | [diff] [blame] | 847 | if (!cpu_online(sibling)) |
| 848 | continue; |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 849 | cpumask_set_cpu(sibling, |
| 850 | &this_leaf->shared_cpu_map); |
Prarit Bhargava | ebb682f | 2009-12-09 13:36:45 -0500 | [diff] [blame] | 851 | } |
Andreas Herrmann | a326e94 | 2009-09-03 09:41:19 +0200 | [diff] [blame] | 852 | } |
Andreas Herrmann | 27d3a8a26 | 2012-10-19 11:02:09 +0200 | [diff] [blame] | 853 | } else |
| 854 | return 0; |
Andreas Herrmann | 32c3233 | 2012-02-08 20:52:29 +0100 | [diff] [blame] | 855 | |
Andreas Herrmann | 27d3a8a26 | 2012-10-19 11:02:09 +0200 | [diff] [blame] | 856 | return 1; |
Andreas Herrmann | 32c3233 | 2012-02-08 20:52:29 +0100 | [diff] [blame] | 857 | } |
| 858 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 859 | static void __cache_cpumap_setup(unsigned int cpu, int index, |
| 860 | struct _cpuid4_info_regs *base) |
Andreas Herrmann | 32c3233 | 2012-02-08 20:52:29 +0100 | [diff] [blame] | 861 | { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 862 | struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); |
| 863 | struct cacheinfo *this_leaf, *sibling_leaf; |
Andreas Herrmann | 32c3233 | 2012-02-08 20:52:29 +0100 | [diff] [blame] | 864 | unsigned long num_threads_sharing; |
| 865 | int index_msb, i; |
| 866 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
| 867 | |
| 868 | if (c->x86_vendor == X86_VENDOR_AMD) { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 869 | if (__cache_amd_cpumap_setup(cpu, index, base)) |
Andreas Herrmann | 32c3233 | 2012-02-08 20:52:29 +0100 | [diff] [blame] | 870 | return; |
| 871 | } |
| 872 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 873 | this_leaf = this_cpu_ci->info_list + index; |
| 874 | num_threads_sharing = 1 + base->eax.split.num_threads_sharing; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 875 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 876 | cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 877 | if (num_threads_sharing == 1) |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 878 | return; |
Siddha, Suresh B | 2b09187 | 2005-11-05 17:25:54 +0100 | [diff] [blame] | 879 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 880 | index_msb = get_count_order(num_threads_sharing); |
| 881 | |
| 882 | for_each_online_cpu(i) |
| 883 | if (cpu_data(i).apicid >> index_msb == c->apicid >> index_msb) { |
| 884 | struct cpu_cacheinfo *sib_cpu_ci = get_cpu_cacheinfo(i); |
| 885 | |
| 886 | if (i == cpu || !sib_cpu_ci->info_list) |
| 887 | continue;/* skip if itself or no cacheinfo */ |
| 888 | sibling_leaf = sib_cpu_ci->info_list + index; |
| 889 | cpumask_set_cpu(i, &this_leaf->shared_cpu_map); |
| 890 | cpumask_set_cpu(cpu, &sibling_leaf->shared_cpu_map); |
Siddha, Suresh B | 2b09187 | 2005-11-05 17:25:54 +0100 | [diff] [blame] | 891 | } |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 892 | } |
| 893 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 894 | static void ci_leaf_init(struct cacheinfo *this_leaf, |
| 895 | struct _cpuid4_info_regs *base) |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 896 | { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 897 | this_leaf->level = base->eax.split.level; |
| 898 | this_leaf->type = cache_type_map[base->eax.split.type]; |
| 899 | this_leaf->coherency_line_size = |
| 900 | base->ebx.split.coherency_line_size + 1; |
| 901 | this_leaf->ways_of_associativity = |
| 902 | base->ebx.split.ways_of_associativity + 1; |
| 903 | this_leaf->size = base->size; |
| 904 | this_leaf->number_of_sets = base->ecx.split.number_of_sets + 1; |
| 905 | this_leaf->physical_line_partition = |
| 906 | base->ebx.split.physical_line_partition + 1; |
| 907 | this_leaf->priv = base->nb; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 908 | } |
| 909 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 910 | static int __init_cache_level(unsigned int cpu) |
Mike Travis | b2bb855 | 2008-12-16 17:34:03 -0800 | [diff] [blame] | 911 | { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 912 | struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); |
Mike Travis | b2bb855 | 2008-12-16 17:34:03 -0800 | [diff] [blame] | 913 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 914 | if (!num_cache_leaves) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 915 | return -ENOENT; |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 916 | if (!this_cpu_ci) |
| 917 | return -EINVAL; |
| 918 | this_cpu_ci->num_levels = 3; |
| 919 | this_cpu_ci->num_leaves = num_cache_leaves; |
Akinobu Mita | 8b2b9c1 | 2008-07-15 17:09:03 +0900 | [diff] [blame] | 920 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 921 | } |
| 922 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 923 | static int __populate_cache_leaves(unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | { |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 925 | unsigned int idx, ret; |
| 926 | struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); |
| 927 | struct cacheinfo *this_leaf = this_cpu_ci->info_list; |
| 928 | struct _cpuid4_info_regs id4_regs = {}; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 929 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 930 | for (idx = 0; idx < this_cpu_ci->num_leaves; idx++) { |
| 931 | ret = cpuid4_cache_lookup_regs(idx, &id4_regs); |
| 932 | if (ret) |
| 933 | return ret; |
| 934 | ci_leaf_init(this_leaf++, &id4_regs); |
| 935 | __cache_cpumap_setup(cpu, idx, &id4_regs); |
Ashok Raj | 1aa1a9f | 2005-10-30 14:59:50 -0800 | [diff] [blame] | 936 | } |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 937 | return 0; |
Ashok Raj | 1aa1a9f | 2005-10-30 14:59:50 -0800 | [diff] [blame] | 938 | } |
| 939 | |
Sudeep Holla | 0d55ba4 | 2015-03-04 12:00:16 +0000 | [diff] [blame] | 940 | DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level) |
| 941 | DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves) |