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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Uwe Kleine-Königf890cef2015-02-24 11:17:08 +01002 * Driver for Motorola/Freescale IMX serial ports
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
Uwe Kleine-Königf890cef2015-02-24 11:17:08 +01004 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
Uwe Kleine-Königf890cef2015-02-24 11:17:08 +01006 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Linus Torvalds1da177e2005-04-16 15:20:36 -070018 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070019
20#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#include <linux/module.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010029#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
Sascha Hauer38a41fd2008-07-05 10:02:46 +020034#include <linux/clk.h>
Fabian Godehardtb6e49132009-06-11 14:53:18 +010035#include <linux/delay.h>
Oskar Schirmer534fca02009-06-11 14:52:23 +010036#include <linux/rational.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090037#include <linux/slab.h>
Shawn Guo22698aa2011-06-25 02:04:34 +080038#include <linux/of.h>
39#include <linux/of_device.h>
Sachin Kamate32a9f82013-01-07 10:25:03 +053040#include <linux/io.h>
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080041#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#include <asm/irq.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020044#include <linux/platform_data/serial-imx.h>
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080045#include <linux/platform_data/dma-imx.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046
Uwe Kleine-König58362d52015-12-13 11:30:03 +010047#include "serial_mctrl_gpio.h"
48
Sascha Hauerff4bfb22007-04-26 08:26:13 +010049/* Register definitions */
50#define URXD0 0x0 /* Receiver Register */
51#define URTX0 0x40 /* Transmitter Register */
52#define UCR1 0x80 /* Control Register 1 */
53#define UCR2 0x84 /* Control Register 2 */
54#define UCR3 0x88 /* Control Register 3 */
55#define UCR4 0x8c /* Control Register 4 */
56#define UFCR 0x90 /* FIFO Control Register */
57#define USR1 0x94 /* Status Register 1 */
58#define USR2 0x98 /* Status Register 2 */
59#define UESC 0x9c /* Escape Character Register */
60#define UTIM 0xa0 /* Escape Timer Register */
61#define UBIR 0xa4 /* BRM Incremental Register */
62#define UBMR 0xa8 /* BRM Modulator Register */
63#define UBRC 0xac /* Baud Rate Count Register */
Shawn Guofe6b5402011-06-25 02:04:33 +080064#define IMX21_ONEMS 0xb0 /* One Millisecond register */
65#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
66#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
Sascha Hauerff4bfb22007-04-26 08:26:13 +010067
68/* UART Control Register Bit Fields.*/
Jiada Wang55d86932014-12-09 18:11:22 +090069#define URXD_DUMMY_READ (1<<16)
Sachin Kamat82313e62013-01-07 10:25:02 +053070#define URXD_CHARRDY (1<<15)
71#define URXD_ERR (1<<14)
72#define URXD_OVRRUN (1<<13)
73#define URXD_FRMERR (1<<12)
74#define URXD_BRK (1<<11)
75#define URXD_PRERR (1<<10)
Dirk Behme26c47412014-09-03 12:33:53 +010076#define URXD_RX_DATA (0xFF<<0)
Sachin Kamat82313e62013-01-07 10:25:02 +053077#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
78#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
79#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
80#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080081#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
Sachin Kamat82313e62013-01-07 10:25:02 +053082#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +010083#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
Sachin Kamat82313e62013-01-07 10:25:02 +053084#define UCR1_IREN (1<<7) /* Infrared interface enable */
85#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
86#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
87#define UCR1_SNDBRK (1<<4) /* Send break */
88#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
89#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080090#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
Sachin Kamat82313e62013-01-07 10:25:02 +053091#define UCR1_DOZE (1<<1) /* Doze */
92#define UCR1_UARTEN (1<<0) /* UART enabled */
93#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
94#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
95#define UCR2_CTSC (1<<13) /* CTS pin control */
96#define UCR2_CTS (1<<12) /* Clear to send */
97#define UCR2_ESCEN (1<<11) /* Escape enable */
98#define UCR2_PREN (1<<8) /* Parity enable */
99#define UCR2_PROE (1<<7) /* Parity odd/even */
100#define UCR2_STPB (1<<6) /* Stop */
101#define UCR2_WS (1<<5) /* Word size */
102#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
103#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
104#define UCR2_TXEN (1<<2) /* Transmitter enabled */
105#define UCR2_RXEN (1<<1) /* Receiver enabled */
106#define UCR2_SRST (1<<0) /* SW reset */
107#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
108#define UCR3_PARERREN (1<<12) /* Parity enable */
109#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
110#define UCR3_DSR (1<<10) /* Data set ready */
111#define UCR3_DCD (1<<9) /* Data carrier detect */
112#define UCR3_RI (1<<8) /* Ring indicator */
Fabio Estevamb38cb7d2014-05-14 15:55:03 -0300113#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
Sachin Kamat82313e62013-01-07 10:25:02 +0530114#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
115#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
116#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
Uwe Kleine-König27e16502016-03-24 14:24:25 +0100117#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
Sachin Kamat82313e62013-01-07 10:25:02 +0530118#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
119#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
120#define UCR3_BPEN (1<<0) /* Preset registers enable */
121#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
122#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
123#define UCR4_INVR (1<<9) /* Inverted infrared reception */
124#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800127#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
Sachin Kamat82313e62013-01-07 10:25:02 +0530128#define UCR4_IRSC (1<<5) /* IR special case */
129#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
130#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
131#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
132#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
133#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
134#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
135#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
136#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
137#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
138#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
139#define USR1_RTSS (1<<14) /* RTS pin status */
140#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
141#define USR1_RTSD (1<<12) /* RTS delta */
142#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
143#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
144#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
Lucas Stach86a04ba2015-09-04 17:52:38 +0200145#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
Uwe Kleine-König27e16502016-03-24 14:24:25 +0100146#define USR1_DTRD (1<<7) /* DTR Delta */
Sachin Kamat82313e62013-01-07 10:25:02 +0530147#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
148#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
149#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
150#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
151#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
152#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
153#define USR2_IDLE (1<<12) /* Idle condition */
Uwe Kleine-König90ebc482015-10-18 21:34:46 +0200154#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
155#define USR2_RIIN (1<<9) /* Ring Indicator Input */
Sachin Kamat82313e62013-01-07 10:25:02 +0530156#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
157#define USR2_WAKE (1<<7) /* Wake */
Uwe Kleine-König90ebc482015-10-18 21:34:46 +0200158#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
Sachin Kamat82313e62013-01-07 10:25:02 +0530159#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
160#define USR2_TXDC (1<<3) /* Transmitter complete */
161#define USR2_BRCD (1<<2) /* Break condition */
162#define USR2_ORE (1<<1) /* Overrun error */
163#define USR2_RDR (1<<0) /* Recv data ready */
164#define UTS_FRCPERR (1<<13) /* Force parity error */
165#define UTS_LOOP (1<<12) /* Loop tx and rx */
166#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
167#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
168#define UTS_TXFULL (1<<4) /* TxFIFO full */
169#define UTS_RXFULL (1<<3) /* RxFIFO full */
170#define UTS_SOFTRST (1<<0) /* Software reset */
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100171
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172/* We've been assigned a range on the "Low-density serial ports" major */
Sachin Kamat82313e62013-01-07 10:25:02 +0530173#define SERIAL_IMX_MAJOR 207
174#define MINOR_START 16
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200175#define DEV_NAME "ttymxc"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178 * This determines how often we check the modem status signals
179 * for any change. They generally aren't connected to an IRQ
180 * so we have to poll them. We also check immediately before
181 * filling the TX fifo incase CTS has been dropped.
182 */
183#define MCTRL_TIMEOUT (250*HZ/1000)
184
185#define DRIVER_NAME "IMX-uart"
186
Sascha Hauerdbff4e92008-07-05 10:02:45 +0200187#define UART_NR 8
188
Uwe Kleine-Königf95661b2015-02-24 11:17:09 +0100189/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
Shawn Guofe6b5402011-06-25 02:04:33 +0800190enum imx_uart_type {
191 IMX1_UART,
192 IMX21_UART,
Martyn Welch1c06bde62016-09-01 11:30:46 +0200193 IMX53_UART,
Huang Shijiea496e622013-07-08 17:14:17 +0800194 IMX6Q_UART,
Shawn Guofe6b5402011-06-25 02:04:33 +0800195};
196
197/* device type dependent stuff */
198struct imx_uart_data {
199 unsigned uts_reg;
200 enum imx_uart_type devtype;
201};
202
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203struct imx_port {
204 struct uart_port port;
205 struct timer_list timer;
206 unsigned int old_status;
Daniel Glöckner26bbb3f2009-06-11 14:36:29 +0100207 unsigned int have_rtscts:1;
Fabio Estevam7b7e8e82017-01-07 19:29:13 -0200208 unsigned int have_rtsgpio:1;
Huang Shijie20ff2fe2013-05-30 14:07:12 +0800209 unsigned int dte_mode:1;
Sascha Hauer3a9465f2012-03-07 09:31:43 +0100210 struct clk *clk_ipg;
211 struct clk *clk_per;
Uwe Kleine-König7d0b0662012-05-21 21:57:39 +0200212 const struct imx_uart_data *devdata;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800213
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100214 struct mctrl_gpios *gpios;
215
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800216 /* DMA fields */
217 unsigned int dma_is_inited:1;
218 unsigned int dma_is_enabled:1;
219 unsigned int dma_is_rxing:1;
220 unsigned int dma_is_txing:1;
221 struct dma_chan *dma_chan_rx, *dma_chan_tx;
222 struct scatterlist rx_sgl, tx_sgl[2];
223 void *rx_buf;
Nandor Han9d297232016-08-08 15:38:27 +0300224 struct circ_buf rx_ring;
225 unsigned int rx_periods;
226 dma_cookie_t rx_cookie;
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800227 unsigned int tx_bytes;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800228 unsigned int dma_tx_nents;
Shenwei Wang90bb6bd2015-07-30 10:32:36 -0500229 unsigned int saved_reg[10];
Eduardo Valentinc868cbb2015-08-11 10:21:23 -0700230 bool context_saved;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231};
232
Dirk Behme0ad5a812011-12-22 09:57:52 +0100233struct imx_port_ucrs {
234 unsigned int ucr1;
235 unsigned int ucr2;
236 unsigned int ucr3;
237};
238
Shawn Guofe6b5402011-06-25 02:04:33 +0800239static struct imx_uart_data imx_uart_devdata[] = {
240 [IMX1_UART] = {
241 .uts_reg = IMX1_UTS,
242 .devtype = IMX1_UART,
243 },
244 [IMX21_UART] = {
245 .uts_reg = IMX21_UTS,
246 .devtype = IMX21_UART,
247 },
Martyn Welch1c06bde62016-09-01 11:30:46 +0200248 [IMX53_UART] = {
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX53_UART,
251 },
Huang Shijiea496e622013-07-08 17:14:17 +0800252 [IMX6Q_UART] = {
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX6Q_UART,
255 },
Shawn Guofe6b5402011-06-25 02:04:33 +0800256};
257
Krzysztof Kozlowski31ada042015-05-02 00:40:02 +0900258static const struct platform_device_id imx_uart_devtype[] = {
Shawn Guofe6b5402011-06-25 02:04:33 +0800259 {
260 .name = "imx1-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
262 }, {
263 .name = "imx21-uart",
264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
265 }, {
Martyn Welch1c06bde62016-09-01 11:30:46 +0200266 .name = "imx53-uart",
267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
268 }, {
Huang Shijiea496e622013-07-08 17:14:17 +0800269 .name = "imx6q-uart",
270 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
271 }, {
Shawn Guofe6b5402011-06-25 02:04:33 +0800272 /* sentinel */
273 }
274};
275MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
276
Sanjeev Sharmaad3d4fd2015-02-03 16:16:06 +0530277static const struct of_device_id imx_uart_dt_ids[] = {
Huang Shijiea496e622013-07-08 17:14:17 +0800278 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
Martyn Welch1c06bde62016-09-01 11:30:46 +0200279 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
Shawn Guo22698aa2011-06-25 02:04:34 +0800280 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
281 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
282 { /* sentinel */ }
283};
284MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
285
Shawn Guofe6b5402011-06-25 02:04:33 +0800286static inline unsigned uts_reg(struct imx_port *sport)
287{
288 return sport->devdata->uts_reg;
289}
290
291static inline int is_imx1_uart(struct imx_port *sport)
292{
293 return sport->devdata->devtype == IMX1_UART;
294}
295
296static inline int is_imx21_uart(struct imx_port *sport)
297{
298 return sport->devdata->devtype == IMX21_UART;
299}
300
Martyn Welch1c06bde62016-09-01 11:30:46 +0200301static inline int is_imx53_uart(struct imx_port *sport)
302{
303 return sport->devdata->devtype == IMX53_UART;
304}
305
Huang Shijiea496e622013-07-08 17:14:17 +0800306static inline int is_imx6q_uart(struct imx_port *sport)
307{
308 return sport->devdata->devtype == IMX6Q_UART;
309}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310/*
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200311 * Save and restore functions for UCR1, UCR2 and UCR3 registers
312 */
Fabio Estevam93d94b32014-11-12 15:55:07 -0200313#if defined(CONFIG_SERIAL_IMX_CONSOLE)
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200314static void imx_port_ucrs_save(struct uart_port *port,
315 struct imx_port_ucrs *ucr)
316{
317 /* save control registers */
318 ucr->ucr1 = readl(port->membase + UCR1);
319 ucr->ucr2 = readl(port->membase + UCR2);
320 ucr->ucr3 = readl(port->membase + UCR3);
321}
322
323static void imx_port_ucrs_restore(struct uart_port *port,
324 struct imx_port_ucrs *ucr)
325{
326 /* restore control registers */
327 writel(ucr->ucr1, port->membase + UCR1);
328 writel(ucr->ucr2, port->membase + UCR2);
329 writel(ucr->ucr3, port->membase + UCR3);
330}
Fabio Estevame8bfa762013-06-05 00:58:46 -0300331#endif
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200332
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100333static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
334{
Fabio Estevambc2be232017-01-30 09:12:12 -0200335 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100336
Ian Jamisonc25bec22017-09-21 10:13:12 +0200337 sport->port.mctrl |= TIOCM_RTS;
338 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100339}
340
341static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
342{
Fabio Estevambc2be232017-01-30 09:12:12 -0200343 *ucr2 &= ~UCR2_CTSC;
344 *ucr2 |= UCR2_CTS;
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100345
Ian Jamisonc25bec22017-09-21 10:13:12 +0200346 sport->port.mctrl &= ~TIOCM_RTS;
347 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100348}
349
350static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
351{
352 *ucr2 |= UCR2_CTSC;
353}
354
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200355/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 * interrupts disabled on entry
357 */
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +0100358static void imx_start_rx(struct uart_port *port)
359{
360 struct imx_port *sport = (struct imx_port *)port;
361 unsigned int ucr1, ucr2;
362
363 ucr1 = readl(port->membase + UCR1);
364 ucr2 = readl(port->membase + UCR2);
365
366 ucr2 |= UCR2_RXEN;
367
368 if (sport->dma_is_enabled) {
369 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
370 } else {
371 ucr1 |= UCR1_RRDYEN;
372 }
373
374 /* Write UCR2 first as it includes RXEN */
375 writel(ucr2, port->membase + UCR2);
376 writel(ucr1, port->membase + UCR1);
377}
378
379/*
380 * interrupts disabled on entry
381 */
Russell Kingb129a8c2005-08-31 10:12:14 +0100382static void imx_stop_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383{
384 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100385 unsigned long temp;
386
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700387 /*
388 * We are maybe in the SMP context, so if the DMA TX thread is running
389 * on other cpu, we have to wait for it to finish.
390 */
391 if (sport->dma_is_enabled && sport->dma_is_txing)
392 return;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800393
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +0100394 temp = readl(port->membase + UCR1);
395 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
396
397 /* in rs485 mode disable transmitter if shifter is empty */
398 if (port->rs485.flags & SER_RS485_ENABLED &&
399 readl(port->membase + USR2) & USR2_TXDC) {
400 temp = readl(port->membase + UCR2);
401 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100402 imx_port_rts_active(sport, &temp);
Fabio Estevam1a613622017-01-30 09:12:11 -0200403 else
404 imx_port_rts_inactive(sport, &temp);
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +0100405 writel(temp, port->membase + UCR2);
406
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +0100407 imx_start_rx(port);
408
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +0100409 temp = readl(port->membase + UCR4);
410 temp &= ~UCR4_TCEN;
411 writel(temp, port->membase + UCR4);
412 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413}
414
415/*
416 * interrupts disabled on entry
417 */
418static void imx_stop_rx(struct uart_port *port)
419{
420 struct imx_port *sport = (struct imx_port *)port;
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +0100421 unsigned long ucr1, ucr2;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100422
Huang Shijie45564a62014-09-19 15:33:12 +0800423 if (sport->dma_is_enabled && sport->dma_is_rxing) {
424 if (sport->port.suspended) {
425 dmaengine_terminate_all(sport->dma_chan_rx);
426 sport->dma_is_rxing = 0;
427 } else {
428 return;
429 }
430 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800431
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +0100432 ucr1 = readl(sport->port.membase + UCR1);
433 ucr2 = readl(sport->port.membase + UCR2);
Huang Shijie85878392014-05-23 12:32:54 +0800434
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +0100435 if (sport->dma_is_enabled) {
436 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
437 } else {
438 ucr1 &= ~UCR1_RRDYEN;
439 }
440 writel(ucr1, port->membase + UCR1);
441
442 ucr2 &= ~UCR2_RXEN;
443 writel(ucr2, port->membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444}
445
446/*
447 * Set the modem control timer to fire immediately.
448 */
449static void imx_enable_ms(struct uart_port *port)
450{
451 struct imx_port *sport = (struct imx_port *)port;
452
453 mod_timer(&sport->timer, jiffies);
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100454
455 mctrl_gpio_enable_ms(sport->gpios);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456}
457
Jiada Wang91a1a902014-12-09 18:11:36 +0900458static void imx_dma_tx(struct imx_port *sport);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459static inline void imx_transmit_buffer(struct imx_port *sport)
460{
Alan Coxebd2c8f2009-09-19 13:13:28 -0700461 struct circ_buf *xmit = &sport->port.state->xmit;
Jiada Wang91a1a902014-12-09 18:11:36 +0900462 unsigned long temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400464 if (sport->port.x_char) {
465 /* Send next char */
466 writel(sport->port.x_char, sport->port.membase + URTX0);
Jiada Wang7e2fb5a2014-12-09 18:11:35 +0900467 sport->port.icount.tx++;
468 sport->port.x_char = 0;
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400469 return;
470 }
471
472 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
473 imx_stop_tx(&sport->port);
474 return;
475 }
476
Jiada Wang91a1a902014-12-09 18:11:36 +0900477 if (sport->dma_is_enabled) {
478 /*
479 * We've just sent a X-char Ensure the TX DMA is enabled
480 * and the TX IRQ is disabled.
481 **/
482 temp = readl(sport->port.membase + UCR1);
483 temp &= ~UCR1_TXMPTYEN;
484 if (sport->dma_is_txing) {
485 temp |= UCR1_TDMAEN;
486 writel(temp, sport->port.membase + UCR1);
487 } else {
488 writel(temp, sport->port.membase + UCR1);
489 imx_dma_tx(sport);
490 }
491 }
492
Ian Jamison5aabd3b2017-08-28 09:02:29 +0100493 if (sport->dma_is_txing)
494 return;
495
496 while (!uart_circ_empty(xmit) &&
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400497 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498 /* send xmit->buf[xmit->tail]
499 * out the port here */
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100500 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100501 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 sport->port.icount.tx++;
Sascha Hauer8c0b2542007-02-05 16:10:16 -0800503 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504
Fabian Godehardt977757312009-06-11 14:37:19 +0100505 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
506 uart_write_wakeup(&sport->port);
507
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 if (uart_circ_empty(xmit))
Russell Kingb129a8c2005-08-31 10:12:14 +0100509 imx_stop_tx(&sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510}
511
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800512static void dma_tx_callback(void *data)
513{
514 struct imx_port *sport = data;
515 struct scatterlist *sgl = &sport->tx_sgl[0];
516 struct circ_buf *xmit = &sport->port.state->xmit;
517 unsigned long flags;
Dirk Behmea2c718c2014-12-09 18:11:31 +0900518 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800519
Dirk Behme42f752b2014-12-09 18:11:28 +0900520 spin_lock_irqsave(&sport->port.lock, flags);
521
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800522 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
523
Dirk Behmea2c718c2014-12-09 18:11:31 +0900524 temp = readl(sport->port.membase + UCR1);
525 temp &= ~UCR1_TDMAEN;
526 writel(temp, sport->port.membase + UCR1);
527
Dirk Behme42f752b2014-12-09 18:11:28 +0900528 /* update the stat */
529 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
530 sport->port.icount.tx += sport->tx_bytes;
531
532 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
533
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800534 sport->dma_is_txing = 0;
535
Jiada Wangd64b8602014-12-09 18:11:29 +0900536 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
537 uart_write_wakeup(&sport->port);
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700538
Jiada Wang0bbc9b82014-12-09 18:11:30 +0900539 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
540 imx_dma_tx(sport);
Uwe Kleine-Königfcc388c2018-03-02 11:07:28 +0100541 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
542 temp = readl(sport->port.membase + UCR4);
543 temp |= UCR4_TCEN;
544 writel(temp, sport->port.membase + UCR4);
545 }
Uwe Kleine-König64432a82017-07-18 14:01:52 +0200546
Jiada Wang0bbc9b82014-12-09 18:11:30 +0900547 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800548}
549
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800550static void imx_dma_tx(struct imx_port *sport)
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800551{
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800552 struct circ_buf *xmit = &sport->port.state->xmit;
553 struct scatterlist *sgl = sport->tx_sgl;
554 struct dma_async_tx_descriptor *desc;
555 struct dma_chan *chan = sport->dma_chan_tx;
556 struct device *dev = sport->port.dev;
Dirk Behmea2c718c2014-12-09 18:11:31 +0900557 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800558 int ret;
559
Dirk Behme42f752b2014-12-09 18:11:28 +0900560 if (sport->dma_is_txing)
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800561 return;
562
Uwe Kleine-Königfcc388c2018-03-02 11:07:28 +0100563 temp = readl(sport->port.membase + UCR4);
564 temp &= ~UCR4_TCEN;
565 writel(temp, sport->port.membase + UCR4);
566
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800567 sport->tx_bytes = uart_circ_chars_pending(xmit);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800568
Fugang Duan75ca0a8f2020-02-11 14:16:01 +0800569 if (xmit->tail < xmit->head || xmit->head == 0) {
Dirk Behme7942f852014-12-09 18:11:25 +0900570 sport->dma_tx_nents = 1;
571 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
572 } else {
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800573 sport->dma_tx_nents = 2;
574 sg_init_table(sgl, 2);
575 sg_set_buf(sgl, xmit->buf + xmit->tail,
576 UART_XMIT_SIZE - xmit->tail);
577 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800578 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800579
580 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
581 if (ret == 0) {
582 dev_err(dev, "DMA mapping error for TX.\n");
583 return;
584 }
Peng Fan9eee44f2019-11-07 06:42:53 +0000585 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800586 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
587 if (!desc) {
Dirk Behme24649822014-12-09 18:11:26 +0900588 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
589 DMA_TO_DEVICE);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800590 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
591 return;
592 }
593 desc->callback = dma_tx_callback;
594 desc->callback_param = sport;
595
596 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
597 uart_circ_chars_pending(xmit));
Dirk Behmea2c718c2014-12-09 18:11:31 +0900598
599 temp = readl(sport->port.membase + UCR1);
600 temp |= UCR1_TDMAEN;
601 writel(temp, sport->port.membase + UCR1);
602
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800603 /* fire it */
604 sport->dma_is_txing = 1;
605 dmaengine_submit(desc);
606 dma_async_issue_pending(chan);
607 return;
608}
609
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610/*
611 * interrupts disabled on entry
612 */
Russell Kingb129a8c2005-08-31 10:12:14 +0100613static void imx_start_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614{
615 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100616 unsigned long temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +0100618 if (port->rs485.flags & SER_RS485_ENABLED) {
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +0100619 temp = readl(port->membase + UCR2);
620 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100621 imx_port_rts_active(sport, &temp);
Fabio Estevam1a613622017-01-30 09:12:11 -0200622 else
623 imx_port_rts_inactive(sport, &temp);
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +0100624 writel(temp, port->membase + UCR2);
625
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +0100626 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
627 imx_stop_rx(port);
628
Uwe Kleine-Königfcc388c2018-03-02 11:07:28 +0100629 /*
630 * Enable transmitter and shifter empty irq only if DMA is off.
631 * In the DMA case this is done in the tx-callback.
632 */
633 if (!sport->dma_is_enabled) {
634 temp = readl(port->membase + UCR4);
635 temp |= UCR4_TCEN;
636 writel(temp, port->membase + UCR4);
637 }
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +0100638 }
639
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800640 if (!sport->dma_is_enabled) {
641 temp = readl(sport->port.membase + UCR1);
642 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
643 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800645 if (sport->dma_is_enabled) {
Jiada Wang91a1a902014-12-09 18:11:36 +0900646 if (sport->port.x_char) {
647 /* We have X-char to send, so enable TX IRQ and
648 * disable TX DMA to let TX interrupt to send X-char */
649 temp = readl(sport->port.membase + UCR1);
650 temp &= ~UCR1_TDMAEN;
651 temp |= UCR1_TXMPTYEN;
652 writel(temp, sport->port.membase + UCR1);
653 return;
654 }
655
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400656 if (!uart_circ_empty(&port->state->xmit) &&
657 !uart_tx_stopped(port))
658 imx_dma_tx(sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800659 return;
660 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661}
662
David Howells7d12e782006-10-05 14:55:46 +0100663static irqreturn_t imx_rtsint(int irq, void *dev_id)
Sascha Hauerceca6292005-10-12 19:58:08 +0100664{
Jeff Garzik15aafa22008-02-06 01:36:20 -0800665 struct imx_port *sport = dev_id;
Uwe Kleine-König5680e942011-04-11 10:59:09 +0200666 unsigned int val;
Sascha Hauerceca6292005-10-12 19:58:08 +0100667 unsigned long flags;
668
669 spin_lock_irqsave(&sport->port.lock, flags);
670
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100671 writel(USR1_RTSD, sport->port.membase + USR1);
Uwe Kleine-König5680e942011-04-11 10:59:09 +0200672 val = readl(sport->port.membase + USR1) & USR1_RTSS;
Sascha Hauerceca6292005-10-12 19:58:08 +0100673 uart_handle_cts_change(&sport->port, !!val);
Alan Coxbdc04e32009-09-19 13:13:31 -0700674 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
Sascha Hauerceca6292005-10-12 19:58:08 +0100675
676 spin_unlock_irqrestore(&sport->port.lock, flags);
677 return IRQ_HANDLED;
678}
679
David Howells7d12e782006-10-05 14:55:46 +0100680static irqreturn_t imx_txint(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681{
Jeff Garzik15aafa22008-02-06 01:36:20 -0800682 struct imx_port *sport = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 unsigned long flags;
684
Sachin Kamat82313e62013-01-07 10:25:02 +0530685 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686 imx_transmit_buffer(sport);
Sachin Kamat82313e62013-01-07 10:25:02 +0530687 spin_unlock_irqrestore(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 return IRQ_HANDLED;
689}
690
David Howells7d12e782006-10-05 14:55:46 +0100691static irqreturn_t imx_rxint(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692{
693 struct imx_port *sport = dev_id;
Sachin Kamat82313e62013-01-07 10:25:02 +0530694 unsigned int rx, flg, ignored = 0;
Jiri Slaby92a19f92013-01-03 15:53:03 +0100695 struct tty_port *port = &sport->port.state->port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100696 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697
Sachin Kamat82313e62013-01-07 10:25:02 +0530698 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699
Sascha Hauer0d3c3932008-04-17 08:43:14 +0100700 while (readl(sport->port.membase + USR2) & USR2_RDR) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701 flg = TTY_NORMAL;
702 sport->port.icount.rx++;
703
Sascha Hauer0d3c3932008-04-17 08:43:14 +0100704 rx = readl(sport->port.membase + URXD0);
705
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100706 temp = readl(sport->port.membase + USR2);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100707 if (temp & USR2_BRCD) {
Andy Green94d32f92010-02-01 13:28:54 +0100708 writel(USR2_BRCD, sport->port.membase + USR2);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100709 if (uart_handle_break(&sport->port))
710 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711 }
712
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100713 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
Sascha Hauer864eeed2008-04-17 08:39:22 +0100714 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715
Hui Wang019dc9e2011-08-24 17:41:47 +0800716 if (unlikely(rx & URXD_ERR)) {
717 if (rx & URXD_BRK)
718 sport->port.icount.brk++;
719 else if (rx & URXD_PRERR)
Sascha Hauer864eeed2008-04-17 08:39:22 +0100720 sport->port.icount.parity++;
721 else if (rx & URXD_FRMERR)
722 sport->port.icount.frame++;
723 if (rx & URXD_OVRRUN)
724 sport->port.icount.overrun++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725
Sascha Hauer864eeed2008-04-17 08:39:22 +0100726 if (rx & sport->port.ignore_status_mask) {
727 if (++ignored > 100)
728 goto out;
729 continue;
730 }
731
Eric Nelson8d267fd2014-12-18 12:37:13 -0700732 rx &= (sport->port.read_status_mask | 0xFF);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100733
Hui Wang019dc9e2011-08-24 17:41:47 +0800734 if (rx & URXD_BRK)
735 flg = TTY_BREAK;
736 else if (rx & URXD_PRERR)
Sascha Hauer864eeed2008-04-17 08:39:22 +0100737 flg = TTY_PARITY;
738 else if (rx & URXD_FRMERR)
739 flg = TTY_FRAME;
740 if (rx & URXD_OVRRUN)
741 flg = TTY_OVERRUN;
742
743#ifdef SUPPORT_SYSRQ
744 sport->port.sysrq = 0;
745#endif
746 }
747
Jiada Wang55d86932014-12-09 18:11:22 +0900748 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
749 goto out;
750
Manfred Schlaegl9b289932015-06-20 19:25:35 +0200751 if (tty_insert_flip_char(port, rx, flg) == 0)
752 sport->port.icount.buf_overrun++;
Sascha Hauer864eeed2008-04-17 08:39:22 +0100753 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754
755out:
Sachin Kamat82313e62013-01-07 10:25:02 +0530756 spin_unlock_irqrestore(&sport->port.lock, flags);
Jiri Slaby2e124b42013-01-03 15:53:06 +0100757 tty_flip_buffer_push(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758 return IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759}
760
Peter Senna Tschudin18a42082017-04-07 11:45:24 +0200761static void imx_disable_rx_int(struct imx_port *sport)
762{
763 unsigned long temp;
764
765 sport->dma_is_rxing = 1;
766
767 /* disable the receiver ready and aging timer interrupts */
768 temp = readl(sport->port.membase + UCR1);
769 temp &= ~(UCR1_RRDYEN);
770 writel(temp, sport->port.membase + UCR1);
771
772 temp = readl(sport->port.membase + UCR2);
773 temp &= ~(UCR2_ATEN);
774 writel(temp, sport->port.membase + UCR2);
775
776 /* disable the rx errors interrupts */
777 temp = readl(sport->port.membase + UCR4);
778 temp &= ~UCR4_OREN;
779 writel(temp, sport->port.membase + UCR4);
780}
781
Nandor Han41d98b52016-08-08 15:38:28 +0300782static void clear_rx_errors(struct imx_port *sport);
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800783static int start_rx_dma(struct imx_port *sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800784/*
785 * If the RXFIFO is filled with some data, and then we
786 * arise a DMA operation to receive them.
787 */
788static void imx_dma_rxint(struct imx_port *sport)
789{
790 unsigned long temp;
Jiada Wang73631812014-12-09 18:11:23 +0900791 unsigned long flags;
792
793 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800794
795 temp = readl(sport->port.membase + USR2);
796 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800797
Peter Senna Tschudin18a42082017-04-07 11:45:24 +0200798 imx_disable_rx_int(sport);
Nandor Han41d98b52016-08-08 15:38:28 +0300799
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800800 /* tell the DMA to receive the data. */
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800801 start_rx_dma(sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800802 }
Jiada Wang73631812014-12-09 18:11:23 +0900803
804 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800805}
806
Uwe Kleine-König66f95882016-03-24 14:24:24 +0100807/*
808 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
809 */
810static unsigned int imx_get_hwmctrl(struct imx_port *sport)
811{
812 unsigned int tmp = TIOCM_DSR;
813 unsigned usr1 = readl(sport->port.membase + USR1);
Sascha Hauer4b75f802016-09-26 15:55:31 +0200814 unsigned usr2 = readl(sport->port.membase + USR2);
Uwe Kleine-König66f95882016-03-24 14:24:24 +0100815
816 if (usr1 & USR1_RTSS)
817 tmp |= TIOCM_CTS;
818
819 /* in DCE mode DCDIN is always 0 */
Sascha Hauer4b75f802016-09-26 15:55:31 +0200820 if (!(usr2 & USR2_DCDIN))
Uwe Kleine-König66f95882016-03-24 14:24:24 +0100821 tmp |= TIOCM_CAR;
822
823 if (sport->dte_mode)
824 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
825 tmp |= TIOCM_RI;
826
827 return tmp;
828}
829
830/*
831 * Handle any change of modem status signal since we were last called.
832 */
833static void imx_mctrl_check(struct imx_port *sport)
834{
835 unsigned int status, changed;
836
837 status = imx_get_hwmctrl(sport);
838 changed = status ^ sport->old_status;
839
840 if (changed == 0)
841 return;
842
843 sport->old_status = status;
844
845 if (changed & TIOCM_RI && status & TIOCM_RI)
846 sport->port.icount.rng++;
847 if (changed & TIOCM_DSR)
848 sport->port.icount.dsr++;
849 if (changed & TIOCM_CAR)
850 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
851 if (changed & TIOCM_CTS)
852 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
853
854 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
855}
856
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200857static irqreturn_t imx_int(int irq, void *dev_id)
858{
859 struct imx_port *sport = dev_id;
Uwe Kleine-König55f5f2c2018-02-18 22:02:44 +0100860 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
Uwe Kleine-König4d845a62016-03-24 14:24:21 +0100861 irqreturn_t ret = IRQ_NONE;
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200862
Uwe Kleine-König55f5f2c2018-02-18 22:02:44 +0100863 usr1 = readl(sport->port.membase + USR1);
864 usr2 = readl(sport->port.membase + USR2);
865 ucr1 = readl(sport->port.membase + UCR1);
866 ucr2 = readl(sport->port.membase + UCR2);
867 ucr3 = readl(sport->port.membase + UCR3);
868 ucr4 = readl(sport->port.membase + UCR4);
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200869
Uwe Kleine-König55f5f2c2018-02-18 22:02:44 +0100870 /*
871 * Even if a condition is true that can trigger an irq only handle it if
872 * the respective irq source is enabled. This prevents some undesired
873 * actions, for example if a character that sits in the RX FIFO and that
874 * should be fetched via DMA is tried to be fetched using PIO. Or the
875 * receiver is currently off and so reading from URXD0 results in an
876 * exception. So just mask the (raw) status bits for disabled irqs.
877 */
878 if ((ucr1 & UCR1_RRDYEN) == 0)
879 usr1 &= ~USR1_RRDY;
880 if ((ucr2 & UCR2_ATEN) == 0)
881 usr1 &= ~USR1_AGTIM;
882 if ((ucr1 & UCR1_TXMPTYEN) == 0)
883 usr1 &= ~USR1_TRDY;
884 if ((ucr4 & UCR4_TCEN) == 0)
885 usr2 &= ~USR2_TXDC;
886 if ((ucr3 & UCR3_DTRDEN) == 0)
887 usr1 &= ~USR1_DTRD;
888 if ((ucr1 & UCR1_RTSDEN) == 0)
889 usr1 &= ~USR1_RTSD;
890 if ((ucr3 & UCR3_AWAKEN) == 0)
891 usr1 &= ~USR1_AWAKE;
892 if ((ucr4 & UCR4_OREN) == 0)
893 usr2 &= ~USR2_ORE;
894
895 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800896 if (sport->dma_is_enabled)
897 imx_dma_rxint(sport);
898 else
899 imx_rxint(irq, dev_id);
Uwe Kleine-König4d845a62016-03-24 14:24:21 +0100900 ret = IRQ_HANDLED;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800901 }
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200902
Uwe Kleine-König55f5f2c2018-02-18 22:02:44 +0100903 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200904 imx_txint(irq, dev_id);
Uwe Kleine-König4d845a62016-03-24 14:24:21 +0100905 ret = IRQ_HANDLED;
906 }
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200907
Uwe Kleine-König55f5f2c2018-02-18 22:02:44 +0100908 if (usr1 & USR1_DTRD) {
Uwe Kleine-König27e16502016-03-24 14:24:25 +0100909 unsigned long flags;
910
Uwe Kleine-König55f5f2c2018-02-18 22:02:44 +0100911 if (usr1 & USR1_DTRD)
Uwe Kleine-König27e16502016-03-24 14:24:25 +0100912 writel(USR1_DTRD, sport->port.membase + USR1);
913
914 spin_lock_irqsave(&sport->port.lock, flags);
915 imx_mctrl_check(sport);
916 spin_unlock_irqrestore(&sport->port.lock, flags);
917
918 ret = IRQ_HANDLED;
919 }
920
Uwe Kleine-König55f5f2c2018-02-18 22:02:44 +0100921 if (usr1 & USR1_RTSD) {
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200922 imx_rtsint(irq, dev_id);
Uwe Kleine-König4d845a62016-03-24 14:24:21 +0100923 ret = IRQ_HANDLED;
924 }
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200925
Uwe Kleine-König55f5f2c2018-02-18 22:02:44 +0100926 if (usr1 & USR1_AWAKE) {
Fabio Estevamdb1a9b52011-12-13 01:23:48 -0200927 writel(USR1_AWAKE, sport->port.membase + USR1);
Uwe Kleine-König4d845a62016-03-24 14:24:21 +0100928 ret = IRQ_HANDLED;
929 }
Fabio Estevamdb1a9b52011-12-13 01:23:48 -0200930
Uwe Kleine-König55f5f2c2018-02-18 22:02:44 +0100931 if (usr2 & USR2_ORE) {
Alexander Steinf1f836e2013-05-14 17:06:07 +0200932 sport->port.icount.overrun++;
Uwe Kleine-König91555ce2015-02-24 11:17:05 +0100933 writel(USR2_ORE, sport->port.membase + USR2);
Uwe Kleine-König4d845a62016-03-24 14:24:21 +0100934 ret = IRQ_HANDLED;
Alexander Steinf1f836e2013-05-14 17:06:07 +0200935 }
936
Uwe Kleine-König4d845a62016-03-24 14:24:21 +0100937 return ret;
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200938}
939
Linus Torvalds1da177e2005-04-16 15:20:36 -0700940/*
941 * Return TIOCSER_TEMT when transmitter is not busy.
942 */
943static unsigned int imx_tx_empty(struct uart_port *port)
944{
945 struct imx_port *sport = (struct imx_port *)port;
Huang Shijie1ce43e52013-10-11 18:30:59 +0800946 unsigned int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700947
Huang Shijie1ce43e52013-10-11 18:30:59 +0800948 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
949
950 /* If the TX DMA is working, return 0. */
951 if (sport->dma_is_enabled && sport->dma_is_txing)
952 ret = 0;
953
954 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955}
956
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100957static unsigned int imx_get_mctrl(struct uart_port *port)
958{
959 struct imx_port *sport = (struct imx_port *)port;
960 unsigned int ret = imx_get_hwmctrl(sport);
961
962 mctrl_gpio_get(sport->gpios, &ret);
963
964 return ret;
965}
966
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
968{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100969 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100970 unsigned long temp;
971
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +0100972 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
973 temp = readl(sport->port.membase + UCR2);
974 temp &= ~(UCR2_CTS | UCR2_CTSC);
975 if (mctrl & TIOCM_RTS)
976 temp |= UCR2_CTS | UCR2_CTSC;
977 writel(temp, sport->port.membase + UCR2);
978 }
Huang Shijie6b471a92013-11-29 17:29:24 +0800979
Uwe Kleine-König90ebc482015-10-18 21:34:46 +0200980 temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
981 if (!(mctrl & TIOCM_DTR))
982 temp |= UCR3_DSR;
983 writel(temp, sport->port.membase + UCR3);
984
Huang Shijie6b471a92013-11-29 17:29:24 +0800985 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
986 if (mctrl & TIOCM_LOOP)
987 temp |= UTS_LOOP;
988 writel(temp, sport->port.membase + uts_reg(sport));
Uwe Kleine-König58362d52015-12-13 11:30:03 +0100989
990 mctrl_gpio_set(sport->gpios, mctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991}
992
993/*
994 * Interrupts always disabled.
995 */
996static void imx_break_ctl(struct uart_port *port, int break_state)
997{
998 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100999 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000
1001 spin_lock_irqsave(&sport->port.lock, flags);
1002
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001003 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
1004
Sachin Kamat82313e62013-01-07 10:25:02 +05301005 if (break_state != 0)
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001006 temp |= UCR1_SNDBRK;
1007
1008 writel(temp, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009
1010 spin_unlock_irqrestore(&sport->port.lock, flags);
1011}
1012
Uwe Kleine-Königcc568842015-10-18 21:34:47 +02001013/*
Uwe Kleine-Königcc568842015-10-18 21:34:47 +02001014 * This is our per-port timeout handler, for checking the
1015 * modem status signals.
1016 */
1017static void imx_timeout(unsigned long data)
1018{
1019 struct imx_port *sport = (struct imx_port *)data;
1020 unsigned long flags;
1021
1022 if (sport->port.state) {
1023 spin_lock_irqsave(&sport->port.lock, flags);
1024 imx_mctrl_check(sport);
1025 spin_unlock_irqrestore(&sport->port.lock, flags);
1026
1027 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1028 }
1029}
1030
Greg Kroah-Hartman351ea502017-07-17 13:48:58 +02001031#define RX_BUF_SIZE (PAGE_SIZE)
1032
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001033/*
Lucas Stach905c0de2015-09-04 17:52:41 +02001034 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001035 * [1] the RX DMA buffer is full.
Lucas Stach905c0de2015-09-04 17:52:41 +02001036 * [2] the aging timer expires
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001037 *
Lucas Stach905c0de2015-09-04 17:52:41 +02001038 * Condition [2] is triggered when a character has been sitting in the FIFO
1039 * for at least 8 byte durations.
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001040 */
1041static void dma_rx_callback(void *data)
1042{
1043 struct imx_port *sport = data;
1044 struct dma_chan *chan = sport->dma_chan_rx;
1045 struct scatterlist *sgl = &sport->rx_sgl;
Huang Shijie7cb92fd2013-10-15 15:23:40 +08001046 struct tty_port *port = &sport->port.state->port;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001047 struct dma_tx_state state;
Nandor Han9d297232016-08-08 15:38:27 +03001048 struct circ_buf *rx_ring = &sport->rx_ring;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001049 enum dma_status status;
Nandor Han9d297232016-08-08 15:38:27 +03001050 unsigned int w_bytes = 0;
1051 unsigned int r_bytes;
1052 unsigned int bd_size;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001053
Huang Shijief0ef8832013-10-11 18:31:01 +08001054 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
Philipp Zabel392bcee2015-05-19 10:54:09 +02001055
Nandor Han9d297232016-08-08 15:38:27 +03001056 if (status == DMA_ERROR) {
1057 dev_err(sport->port.dev, "DMA transaction error.\n");
Nandor Han41d98b52016-08-08 15:38:28 +03001058 clear_rx_errors(sport);
Nandor Han9d297232016-08-08 15:38:27 +03001059 return;
Robin Gongee5e7c12014-12-09 18:11:33 +09001060 }
Lucas Stach976b39c2015-09-04 17:52:39 +02001061
Nandor Han9d297232016-08-08 15:38:27 +03001062 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1063
1064 /*
1065 * The state-residue variable represents the empty space
1066 * relative to the entire buffer. Taking this in consideration
1067 * the head is always calculated base on the buffer total
1068 * length - DMA transaction residue. The UART script from the
1069 * SDMA firmware will jump to the next buffer descriptor,
1070 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1071 * Taking this in consideration the tail is always at the
1072 * beginning of the buffer descriptor that contains the head.
1073 */
1074
1075 /* Calculate the head */
1076 rx_ring->head = sg_dma_len(sgl) - state.residue;
1077
1078 /* Calculate the tail. */
1079 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1080 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1081
1082 if (rx_ring->head <= sg_dma_len(sgl) &&
1083 rx_ring->head > rx_ring->tail) {
1084
1085 /* Move data from tail to head */
1086 r_bytes = rx_ring->head - rx_ring->tail;
1087
1088 /* CPU claims ownership of RX DMA buffer */
1089 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1090 DMA_FROM_DEVICE);
1091
1092 w_bytes = tty_insert_flip_string(port,
1093 sport->rx_buf + rx_ring->tail, r_bytes);
1094
1095 /* UART retrieves ownership of RX DMA buffer */
1096 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1097 DMA_FROM_DEVICE);
1098
1099 if (w_bytes != r_bytes)
1100 sport->port.icount.buf_overrun++;
1101
1102 sport->port.icount.rx += w_bytes;
1103 } else {
1104 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1105 WARN_ON(rx_ring->head <= rx_ring->tail);
1106 }
1107 }
1108
1109 if (w_bytes) {
1110 tty_flip_buffer_push(port);
1111 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1112 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001113}
1114
Greg Kroah-Hartman351ea502017-07-17 13:48:58 +02001115/* RX DMA buffer periods */
1116#define RX_DMA_PERIODS 4
1117
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001118static int start_rx_dma(struct imx_port *sport)
1119{
1120 struct scatterlist *sgl = &sport->rx_sgl;
1121 struct dma_chan *chan = sport->dma_chan_rx;
1122 struct device *dev = sport->port.dev;
1123 struct dma_async_tx_descriptor *desc;
1124 int ret;
1125
Nandor Han9d297232016-08-08 15:38:27 +03001126 sport->rx_ring.head = 0;
1127 sport->rx_ring.tail = 0;
Greg Kroah-Hartman351ea502017-07-17 13:48:58 +02001128 sport->rx_periods = RX_DMA_PERIODS;
Nandor Han9d297232016-08-08 15:38:27 +03001129
Greg Kroah-Hartman351ea502017-07-17 13:48:58 +02001130 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001131 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1132 if (ret == 0) {
1133 dev_err(dev, "DMA mapping error for RX.\n");
1134 return -EINVAL;
1135 }
Nandor Han9d297232016-08-08 15:38:27 +03001136
1137 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1138 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1139 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1140
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001141 if (!desc) {
Dirk Behme24649822014-12-09 18:11:26 +09001142 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001143 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1144 return -EINVAL;
1145 }
1146 desc->callback = dma_rx_callback;
1147 desc->callback_param = sport;
1148
1149 dev_dbg(dev, "RX: prepare for the DMA.\n");
Nandor Han9d297232016-08-08 15:38:27 +03001150 sport->rx_cookie = dmaengine_submit(desc);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001151 dma_async_issue_pending(chan);
1152 return 0;
1153}
1154
Nandor Han41d98b52016-08-08 15:38:28 +03001155static void clear_rx_errors(struct imx_port *sport)
1156{
1157 unsigned int status_usr1, status_usr2;
1158
1159 status_usr1 = readl(sport->port.membase + USR1);
1160 status_usr2 = readl(sport->port.membase + USR2);
1161
1162 if (status_usr2 & USR2_BRCD) {
1163 sport->port.icount.brk++;
1164 writel(USR2_BRCD, sport->port.membase + USR2);
1165 } else if (status_usr1 & USR1_FRAMERR) {
1166 sport->port.icount.frame++;
1167 writel(USR1_FRAMERR, sport->port.membase + USR1);
1168 } else if (status_usr1 & USR1_PARITYERR) {
1169 sport->port.icount.parity++;
1170 writel(USR1_PARITYERR, sport->port.membase + USR1);
1171 }
1172
1173 if (status_usr2 & USR2_ORE) {
1174 sport->port.icount.overrun++;
1175 writel(USR2_ORE, sport->port.membase + USR2);
1176 }
1177
1178}
1179
Lucas Stachcc323822015-09-04 17:52:37 +02001180#define TXTL_DEFAULT 2 /* reset default */
1181#define RXTL_DEFAULT 1 /* reset default */
Lucas Stach184bd702015-09-04 17:52:40 +02001182#define TXTL_DMA 8 /* DMA burst setting */
1183#define RXTL_DMA 9 /* DMA burst setting */
Lucas Stachcc323822015-09-04 17:52:37 +02001184
1185static void imx_setup_ufcr(struct imx_port *sport,
1186 unsigned char txwl, unsigned char rxwl)
1187{
1188 unsigned int val;
1189
1190 /* set receiver / transmitter trigger level */
1191 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1192 val |= txwl << UFCR_TXTL_SHF | rxwl;
1193 writel(val, sport->port.membase + UFCR);
1194}
1195
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001196static void imx_uart_dma_exit(struct imx_port *sport)
1197{
1198 if (sport->dma_chan_rx) {
Fabien Lahouderee5e89602016-09-13 10:17:05 +02001199 dmaengine_terminate_sync(sport->dma_chan_rx);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001200 dma_release_channel(sport->dma_chan_rx);
1201 sport->dma_chan_rx = NULL;
Nandor Han9d297232016-08-08 15:38:27 +03001202 sport->rx_cookie = -EINVAL;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001203 kfree(sport->rx_buf);
1204 sport->rx_buf = NULL;
1205 }
1206
1207 if (sport->dma_chan_tx) {
Fabien Lahouderee5e89602016-09-13 10:17:05 +02001208 dmaengine_terminate_sync(sport->dma_chan_tx);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001209 dma_release_channel(sport->dma_chan_tx);
1210 sport->dma_chan_tx = NULL;
1211 }
1212
1213 sport->dma_is_inited = 0;
1214}
1215
1216static int imx_uart_dma_init(struct imx_port *sport)
1217{
Huang Shijieb09c74a2013-08-29 16:29:25 +08001218 struct dma_slave_config slave_config = {};
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001219 struct device *dev = sport->port.dev;
1220 int ret;
1221
1222 /* Prepare for RX : */
1223 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1224 if (!sport->dma_chan_rx) {
1225 dev_dbg(dev, "cannot get the DMA channel.\n");
1226 ret = -EINVAL;
1227 goto err;
1228 }
1229
1230 slave_config.direction = DMA_DEV_TO_MEM;
1231 slave_config.src_addr = sport->port.mapbase + URXD0;
1232 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
Lucas Stach184bd702015-09-04 17:52:40 +02001233 /* one byte less than the watermark level to enable the aging timer */
1234 slave_config.src_maxburst = RXTL_DMA - 1;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001235 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1236 if (ret) {
1237 dev_err(dev, "error in RX dma configuration.\n");
1238 goto err;
1239 }
1240
Greg Kroah-Hartman351ea502017-07-17 13:48:58 +02001241 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001242 if (!sport->rx_buf) {
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001243 ret = -ENOMEM;
1244 goto err;
1245 }
Nandor Han9d297232016-08-08 15:38:27 +03001246 sport->rx_ring.buf = sport->rx_buf;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001247
1248 /* Prepare for TX : */
1249 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1250 if (!sport->dma_chan_tx) {
1251 dev_err(dev, "cannot get the TX DMA channel!\n");
1252 ret = -EINVAL;
1253 goto err;
1254 }
1255
1256 slave_config.direction = DMA_MEM_TO_DEV;
1257 slave_config.dst_addr = sport->port.mapbase + URTX0;
1258 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
Lucas Stach184bd702015-09-04 17:52:40 +02001259 slave_config.dst_maxburst = TXTL_DMA;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001260 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1261 if (ret) {
1262 dev_err(dev, "error in TX dma configuration.");
1263 goto err;
1264 }
1265
1266 sport->dma_is_inited = 1;
1267
1268 return 0;
1269err:
1270 imx_uart_dma_exit(sport);
1271 return ret;
1272}
1273
1274static void imx_enable_dma(struct imx_port *sport)
1275{
1276 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001277
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001278 /* set UCR1 */
1279 temp = readl(sport->port.membase + UCR1);
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +01001280 temp |= UCR1_RXDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001281 writel(temp, sport->port.membase + UCR1);
1282
Lucas Stach86a04ba2015-09-04 17:52:38 +02001283 temp = readl(sport->port.membase + UCR2);
1284 temp |= UCR2_ATEN;
1285 writel(temp, sport->port.membase + UCR2);
1286
Lucas Stach184bd702015-09-04 17:52:40 +02001287 imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1288
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001289 sport->dma_is_enabled = 1;
1290}
1291
1292static void imx_disable_dma(struct imx_port *sport)
1293{
1294 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001295
1296 /* clear UCR1 */
1297 temp = readl(sport->port.membase + UCR1);
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +01001298 temp &= ~(UCR1_RXDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001299 writel(temp, sport->port.membase + UCR1);
1300
1301 /* clear UCR2 */
1302 temp = readl(sport->port.membase + UCR2);
Lucas Stach86a04ba2015-09-04 17:52:38 +02001303 temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001304 writel(temp, sport->port.membase + UCR2);
1305
Lucas Stach184bd702015-09-04 17:52:40 +02001306 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1307
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001308 sport->dma_is_enabled = 0;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001309}
1310
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001311/* half the RX buffer size */
1312#define CTSTL 16
1313
Linus Torvalds1da177e2005-04-16 15:20:36 -07001314static int imx_startup(struct uart_port *port)
1315{
1316 struct imx_port *sport = (struct imx_port *)port;
Fabio Estevam458e2c82015-07-27 15:15:59 -03001317 int retval, i;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001318 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319
Huang Shijie1cf93e02013-06-28 13:39:42 +08001320 retval = clk_prepare_enable(sport->clk_per);
1321 if (retval)
Fabio Estevamcb0f0a52014-10-27 14:49:38 -02001322 return retval;
Huang Shijie1cf93e02013-06-28 13:39:42 +08001323 retval = clk_prepare_enable(sport->clk_ipg);
1324 if (retval) {
1325 clk_disable_unprepare(sport->clk_per);
Fabio Estevamcb0f0a52014-10-27 14:49:38 -02001326 return retval;
Huang Shijie0c375502013-06-09 10:01:19 +08001327 }
Huang Shijie28eb4272013-06-04 09:59:33 +08001328
Lucas Stachcc323822015-09-04 17:52:37 +02001329 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330
1331 /* disable the DREN bit (Data Ready interrupt enable) before
1332 * requesting IRQs
1333 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001334 temp = readl(sport->port.membase + UCR4);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001335
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001336 /* set the trigger level for CTS */
Sachin Kamat82313e62013-01-07 10:25:02 +05301337 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1338 temp |= CTSTL << UCR4_CTSTL_SHF;
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001339
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001340 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001341
Lucas Stach7e115772015-09-04 17:52:42 +02001342 /* Can we enable the DMA support? */
Martyn Welch1c06bde62016-09-01 11:30:46 +02001343 if (!uart_console(port) && !sport->dma_is_inited)
Lucas Stach7e115772015-09-04 17:52:42 +02001344 imx_uart_dma_init(sport);
1345
Jiada Wang53794182015-04-13 18:31:43 +09001346 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijie772f8992014-05-21 08:56:28 +08001347 /* Reset fifo's and state machines */
Fabio Estevam458e2c82015-07-27 15:15:59 -03001348 i = 100;
1349
1350 temp = readl(sport->port.membase + UCR2);
1351 temp &= ~UCR2_SRST;
1352 writel(temp, sport->port.membase + UCR2);
1353
1354 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1355 udelay(1);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001356
Linus Torvalds1da177e2005-04-16 15:20:36 -07001357 /*
1358 * Finally, clear and enable interrupts
1359 */
Uwe Kleine-König27e16502016-03-24 14:24:25 +01001360 writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1);
Uwe Kleine-König91555ce2015-02-24 11:17:05 +01001361 writel(USR2_ORE, sport->port.membase + USR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001363 temp = readl(sport->port.membase + UCR1);
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +01001364 temp &= ~UCR1_RRDYEN;
1365 temp |= UCR1_UARTEN;
Nandor Han6376cd32017-06-28 15:59:36 +02001366 if (sport->have_rtscts)
1367 temp |= UCR1_RTSDEN;
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001368
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001369 writel(temp, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370
Jiada Wang6f026d6b2014-12-09 18:11:34 +09001371 temp = readl(sport->port.membase + UCR4);
1372 temp |= UCR4_OREN;
1373 writel(temp, sport->port.membase + UCR4);
1374
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001375 temp = readl(sport->port.membase + UCR2);
1376 temp |= (UCR2_RXEN | UCR2_TXEN);
Lucas Stachbff09b02013-05-30 15:47:04 +02001377 if (!sport->have_rtscts)
1378 temp |= UCR2_IRTS;
Uwe Kleine-König16804d62016-03-24 14:24:22 +01001379 /*
1380 * make sure the edge sensitive RTS-irq is disabled,
1381 * we're using RTSD instead.
1382 */
1383 if (!is_imx1_uart(sport))
1384 temp &= ~UCR2_RTSEN;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001385 writel(temp, sport->port.membase + UCR2);
1386
Huang Shijiea496e622013-07-08 17:14:17 +08001387 if (!is_imx1_uart(sport)) {
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001388 temp = readl(sport->port.membase + UCR3);
Uwe Kleine-König16804d62016-03-24 14:24:22 +01001389
Uwe Kleine-Könige61c38d2017-04-04 11:18:51 +02001390 temp |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
Uwe Kleine-König16804d62016-03-24 14:24:22 +01001391
1392 if (sport->dte_mode)
Uwe Kleine-Könige61c38d2017-04-04 11:18:51 +02001393 /* disable broken interrupts */
Uwe Kleine-König16804d62016-03-24 14:24:22 +01001394 temp &= ~(UCR3_RI | UCR3_DCD);
1395
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001396 writel(temp, sport->port.membase + UCR3);
1397 }
Marc Kleine-Budde44118052008-07-28 12:10:34 +02001398
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399 /*
1400 * Enable modem status interrupts
1401 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402 imx_enable_ms(&sport->port);
Peter Senna Tschudin18a42082017-04-07 11:45:24 +02001403
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +01001404 if (sport->dma_is_inited) {
1405 imx_enable_dma(sport);
Peter Senna Tschudin4dec2f12017-05-14 14:35:15 +02001406 start_rx_dma(sport);
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +01001407 } else {
1408 temp = readl(sport->port.membase + UCR1);
1409 temp |= UCR1_RRDYEN;
1410 writel(temp, sport->port.membase + UCR1);
Peter Senna Tschudin18a42082017-04-07 11:45:24 +02001411 }
1412
Sachin Kamat82313e62013-01-07 10:25:02 +05301413 spin_unlock_irqrestore(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414
1415 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001416}
1417
1418static void imx_shutdown(struct uart_port *port)
1419{
1420 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001421 unsigned long temp;
Xinyu Chen9ec18822012-08-27 09:36:51 +02001422 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001423
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001424 if (sport->dma_is_enabled) {
Nandor Han9d297232016-08-08 15:38:27 +03001425 sport->dma_is_rxing = 0;
1426 sport->dma_is_txing = 0;
Fabien Lahouderee5e89602016-09-13 10:17:05 +02001427 dmaengine_terminate_sync(sport->dma_chan_tx);
1428 dmaengine_terminate_sync(sport->dma_chan_rx);
Huang Shijiea4688bc2014-09-19 15:42:57 +08001429
Jiada Wang73631812014-12-09 18:11:23 +09001430 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijiea4688bc2014-09-19 15:42:57 +08001431 imx_stop_tx(port);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001432 imx_stop_rx(port);
1433 imx_disable_dma(sport);
Jiada Wang73631812014-12-09 18:11:23 +09001434 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001435 imx_uart_dma_exit(sport);
1436 }
1437
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001438 mctrl_gpio_disable_ms(sport->gpios);
1439
Xinyu Chen9ec18822012-08-27 09:36:51 +02001440 spin_lock_irqsave(&sport->port.lock, flags);
Fabian Godehardt2e146392009-06-11 14:38:38 +01001441 temp = readl(sport->port.membase + UCR2);
1442 temp &= ~(UCR2_TXEN);
1443 writel(temp, sport->port.membase + UCR2);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001444 spin_unlock_irqrestore(&sport->port.lock, flags);
Fabian Godehardt2e146392009-06-11 14:38:38 +01001445
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446 /*
1447 * Stop our timer.
1448 */
1449 del_timer_sync(&sport->timer);
1450
1451 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452 * Disable all interrupts, port and break condition.
1453 */
1454
Xinyu Chen9ec18822012-08-27 09:36:51 +02001455 spin_lock_irqsave(&sport->port.lock, flags);
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001456 temp = readl(sport->port.membase + UCR1);
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +01001457 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN |
1458 UCR1_RXDMAEN | UCR1_ATDMAEN);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001459
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001460 writel(temp, sport->port.membase + UCR1);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001461 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijie28eb4272013-06-04 09:59:33 +08001462
Huang Shijie1cf93e02013-06-28 13:39:42 +08001463 clk_disable_unprepare(sport->clk_per);
1464 clk_disable_unprepare(sport->clk_ipg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001465}
1466
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001467static void imx_flush_buffer(struct uart_port *port)
1468{
1469 struct imx_port *sport = (struct imx_port *)port;
Dirk Behme82e86ae2014-12-09 18:11:27 +09001470 struct scatterlist *sgl = &sport->tx_sgl[0];
Dirk Behmea2c718c2014-12-09 18:11:31 +09001471 unsigned long temp;
Fabio Estevam4f86a952015-02-07 15:46:41 -02001472 int i = 100, ubir, ubmr, uts;
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001473
Dirk Behme82e86ae2014-12-09 18:11:27 +09001474 if (!sport->dma_chan_tx)
1475 return;
1476
1477 sport->tx_bytes = 0;
1478 dmaengine_terminate_all(sport->dma_chan_tx);
1479 if (sport->dma_is_txing) {
1480 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1481 DMA_TO_DEVICE);
Dirk Behmea2c718c2014-12-09 18:11:31 +09001482 temp = readl(sport->port.membase + UCR1);
1483 temp &= ~UCR1_TDMAEN;
1484 writel(temp, sport->port.membase + UCR1);
Dirk Behme82e86ae2014-12-09 18:11:27 +09001485 sport->dma_is_txing = false;
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001486 }
Fabio Estevam934084a2015-01-13 10:00:26 -02001487
1488 /*
1489 * According to the Reference Manual description of the UART SRST bit:
1490 * "Reset the transmit and receive state machines,
1491 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1492 * and UTS[6-3]". As we don't need to restore the old values from
1493 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1494 */
1495 ubir = readl(sport->port.membase + UBIR);
1496 ubmr = readl(sport->port.membase + UBMR);
Fabio Estevam934084a2015-01-13 10:00:26 -02001497 uts = readl(sport->port.membase + IMX21_UTS);
1498
1499 temp = readl(sport->port.membase + UCR2);
1500 temp &= ~UCR2_SRST;
1501 writel(temp, sport->port.membase + UCR2);
1502
1503 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1504 udelay(1);
1505
1506 /* Restore the registers */
1507 writel(ubir, sport->port.membase + UBIR);
1508 writel(ubmr, sport->port.membase + UBMR);
Fabio Estevam934084a2015-01-13 10:00:26 -02001509 writel(uts, sport->port.membase + IMX21_UTS);
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001510}
1511
Linus Torvalds1da177e2005-04-16 15:20:36 -07001512static void
Alan Cox606d0992006-12-08 02:38:45 -08001513imx_set_termios(struct uart_port *port, struct ktermios *termios,
1514 struct ktermios *old)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001515{
1516 struct imx_port *sport = (struct imx_port *)port;
1517 unsigned long flags;
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001518 unsigned long ucr2, old_ucr1, old_ucr2;
1519 unsigned int baud, quot;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001520 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001521 unsigned long div, ufcr;
Oskar Schirmer534fca02009-06-11 14:52:23 +01001522 unsigned long num, denom;
Oskar Schirmerd7f8d432009-06-11 14:55:22 +01001523 uint64_t tdiv64;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524
1525 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526 * We only support CS7 and CS8.
1527 */
1528 while ((termios->c_cflag & CSIZE) != CS7 &&
1529 (termios->c_cflag & CSIZE) != CS8) {
1530 termios->c_cflag &= ~CSIZE;
1531 termios->c_cflag |= old_csize;
1532 old_csize = CS8;
1533 }
1534
1535 if ((termios->c_cflag & CSIZE) == CS8)
1536 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1537 else
1538 ucr2 = UCR2_SRST | UCR2_IRTS;
1539
1540 if (termios->c_cflag & CRTSCTS) {
Sachin Kamat82313e62013-01-07 10:25:02 +05301541 if (sport->have_rtscts) {
Sascha Hauer5b802342006-05-04 14:07:42 +01001542 ucr2 &= ~UCR2_IRTS;
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001543
Fabio Estevam12fe59f2015-03-10 12:46:29 -03001544 if (port->rs485.flags & SER_RS485_ENABLED) {
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001545 /*
1546 * RTS is mandatory for rs485 operation, so keep
1547 * it under manual control and keep transmitter
1548 * disabled.
1549 */
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001550 if (port->rs485.flags &
1551 SER_RS485_RTS_AFTER_SEND)
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001552 imx_port_rts_active(sport, &ucr2);
Fabio Estevam1a613622017-01-30 09:12:11 -02001553 else
1554 imx_port_rts_inactive(sport, &ucr2);
Fabio Estevam12fe59f2015-03-10 12:46:29 -03001555 } else {
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001556 imx_port_rts_auto(sport, &ucr2);
Fabio Estevam12fe59f2015-03-10 12:46:29 -03001557 }
Sascha Hauer5b802342006-05-04 14:07:42 +01001558 } else {
1559 termios->c_cflag &= ~CRTSCTS;
1560 }
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001561 } else if (port->rs485.flags & SER_RS485_ENABLED) {
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001562 /* disable transmitter */
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001563 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001564 imx_port_rts_active(sport, &ucr2);
Fabio Estevam1a613622017-01-30 09:12:11 -02001565 else
1566 imx_port_rts_inactive(sport, &ucr2);
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001567 }
1568
Linus Torvalds1da177e2005-04-16 15:20:36 -07001569
1570 if (termios->c_cflag & CSTOPB)
1571 ucr2 |= UCR2_STPB;
1572 if (termios->c_cflag & PARENB) {
1573 ucr2 |= UCR2_PREN;
Matt Reimer3261e362006-01-13 20:51:44 +00001574 if (termios->c_cflag & PARODD)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001575 ucr2 |= UCR2_PROE;
1576 }
1577
Eric Miao995234d2011-12-23 05:39:27 +08001578 del_timer_sync(&sport->timer);
1579
Linus Torvalds1da177e2005-04-16 15:20:36 -07001580 /*
1581 * Ask the core to calculate the divisor for us.
1582 */
Sascha Hauer036bb152008-07-05 10:02:44 +02001583 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001584 quot = uart_get_divisor(port, baud);
1585
1586 spin_lock_irqsave(&sport->port.lock, flags);
1587
1588 sport->port.read_status_mask = 0;
1589 if (termios->c_iflag & INPCK)
1590 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1591 if (termios->c_iflag & (BRKINT | PARMRK))
1592 sport->port.read_status_mask |= URXD_BRK;
1593
1594 /*
1595 * Characters to ignore
1596 */
1597 sport->port.ignore_status_mask = 0;
1598 if (termios->c_iflag & IGNPAR)
Eric Nelson865cea82014-12-18 12:37:14 -07001599 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001600 if (termios->c_iflag & IGNBRK) {
1601 sport->port.ignore_status_mask |= URXD_BRK;
1602 /*
1603 * If we're ignoring parity and break indicators,
1604 * ignore overruns too (for real raw support).
1605 */
1606 if (termios->c_iflag & IGNPAR)
1607 sport->port.ignore_status_mask |= URXD_OVRRUN;
1608 }
1609
Jiada Wang55d86932014-12-09 18:11:22 +09001610 if ((termios->c_cflag & CREAD) == 0)
1611 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1612
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613 /*
1614 * Update the per-port timeout.
1615 */
1616 uart_update_timeout(port, termios->c_cflag, baud);
1617
1618 /*
1619 * disable interrupts and drain transmitter
1620 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001621 old_ucr1 = readl(sport->port.membase + UCR1);
1622 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1623 sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001624
Sachin Kamat82313e62013-01-07 10:25:02 +05301625 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626 barrier();
1627
1628 /* then, disable everything */
Lucas Stach86a04ba2015-09-04 17:52:38 +02001629 old_ucr2 = readl(sport->port.membase + UCR2);
1630 writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001631 sport->port.membase + UCR2);
Lucas Stach86a04ba2015-09-04 17:52:38 +02001632 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001633
Uwe Kleine-Königafe9cbb2015-02-24 11:17:10 +01001634 /* custom-baudrate handling */
1635 div = sport->port.uartclk / (baud * 16);
1636 if (baud == 38400 && quot != div)
1637 baud = sport->port.uartclk / (quot * 16);
Hubert Feurstein09bd00f2013-07-18 18:52:49 +02001638
Uwe Kleine-Königafe9cbb2015-02-24 11:17:10 +01001639 div = sport->port.uartclk / (baud * 16);
1640 if (div > 7)
1641 div = 7;
1642 if (!div)
1643 div = 1;
Sascha Hauer036bb152008-07-05 10:02:44 +02001644
Oskar Schirmer534fca02009-06-11 14:52:23 +01001645 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1646 1 << 16, 1 << 16, &num, &denom);
Sascha Hauer036bb152008-07-05 10:02:44 +02001647
Alan Coxeab4f5a2010-06-01 22:52:52 +02001648 tdiv64 = sport->port.uartclk;
1649 tdiv64 *= num;
1650 do_div(tdiv64, denom * 16 * div);
1651 tty_termios_encode_baud_rate(termios,
Sascha Hauer1a2c4b32009-06-16 17:02:15 +01001652 (speed_t)tdiv64, (speed_t)tdiv64);
Oskar Schirmerd7f8d432009-06-11 14:55:22 +01001653
Oskar Schirmer534fca02009-06-11 14:52:23 +01001654 num -= 1;
1655 denom -= 1;
Sascha Hauer036bb152008-07-05 10:02:44 +02001656
1657 ufcr = readl(sport->port.membase + UFCR);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001658 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
Sascha Hauer036bb152008-07-05 10:02:44 +02001659 writel(ufcr, sport->port.membase + UFCR);
1660
Oskar Schirmer534fca02009-06-11 14:52:23 +01001661 writel(num, sport->port.membase + UBIR);
1662 writel(denom, sport->port.membase + UBMR);
1663
Huang Shijiea496e622013-07-08 17:14:17 +08001664 if (!is_imx1_uart(sport))
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001665 writel(sport->port.uartclk / div / 1000,
Shawn Guofe6b5402011-06-25 02:04:33 +08001666 sport->port.membase + IMX21_ONEMS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001667
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001668 writel(old_ucr1, sport->port.membase + UCR1);
1669
1670 /* set the parity, stop bits and data size */
Lucas Stach86a04ba2015-09-04 17:52:38 +02001671 writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001672
1673 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1674 imx_enable_ms(&sport->port);
1675
1676 spin_unlock_irqrestore(&sport->port.lock, flags);
1677}
1678
1679static const char *imx_type(struct uart_port *port)
1680{
1681 struct imx_port *sport = (struct imx_port *)port;
1682
1683 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1684}
1685
1686/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001687 * Configure/autoconfigure the port.
1688 */
1689static void imx_config_port(struct uart_port *port, int flags)
1690{
1691 struct imx_port *sport = (struct imx_port *)port;
1692
Alexander Shiyanda82f992014-02-22 16:01:33 +04001693 if (flags & UART_CONFIG_TYPE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001694 sport->port.type = PORT_IMX;
1695}
1696
1697/*
1698 * Verify the new serial_struct (for TIOCSSERIAL).
1699 * The only change we allow are to the flags and type, and
1700 * even then only between PORT_IMX and PORT_UNKNOWN
1701 */
1702static int
1703imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1704{
1705 struct imx_port *sport = (struct imx_port *)port;
1706 int ret = 0;
1707
1708 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1709 ret = -EINVAL;
1710 if (sport->port.irq != ser->irq)
1711 ret = -EINVAL;
1712 if (ser->io_type != UPIO_MEM)
1713 ret = -EINVAL;
1714 if (sport->port.uartclk / 16 != ser->baud_base)
1715 ret = -EINVAL;
Olof Johanssona50c44c2013-09-11 21:27:53 -07001716 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001717 ret = -EINVAL;
1718 if (sport->port.iobase != ser->port)
1719 ret = -EINVAL;
1720 if (ser->hub6 != 0)
1721 ret = -EINVAL;
1722 return ret;
1723}
1724
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001725#if defined(CONFIG_CONSOLE_POLL)
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001726
1727static int imx_poll_init(struct uart_port *port)
1728{
1729 struct imx_port *sport = (struct imx_port *)port;
1730 unsigned long flags;
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +01001731 unsigned long ucr1, ucr2;
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001732 int retval;
1733
1734 retval = clk_prepare_enable(sport->clk_ipg);
1735 if (retval)
1736 return retval;
1737 retval = clk_prepare_enable(sport->clk_per);
1738 if (retval)
1739 clk_disable_unprepare(sport->clk_ipg);
1740
Lucas Stachcc323822015-09-04 17:52:37 +02001741 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001742
1743 spin_lock_irqsave(&sport->port.lock, flags);
1744
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +01001745 /*
1746 * Be careful about the order of enabling bits here. First enable the
1747 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1748 * This prevents that a character that already sits in the RX fifo is
1749 * triggering an irq but the try to fetch it from there results in an
1750 * exception because UARTEN or RXEN is still off.
1751 */
1752 ucr1 = readl(port->membase + UCR1);
1753 ucr2 = readl(port->membase + UCR2);
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001754
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +01001755 if (is_imx1_uart(sport))
1756 ucr1 |= IMX1_UCR1_UARTCLKEN;
1757
1758 ucr1 |= UCR1_UARTEN;
1759 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1760
1761 ucr2 |= UCR2_RXEN;
1762
1763 writel(ucr1, sport->port.membase + UCR1);
1764 writel(ucr2, sport->port.membase + UCR2);
1765
1766 /* now enable irqs */
1767 writel(ucr1 | UCR1_RRDYEN, sport->port.membase + UCR1);
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001768
1769 spin_unlock_irqrestore(&sport->port.lock, flags);
1770
1771 return 0;
1772}
1773
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001774static int imx_poll_get_char(struct uart_port *port)
1775{
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001776 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
Dirk Behme26c47412014-09-03 12:33:53 +01001777 return NO_POLL_CHAR;
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001778
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001779 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001780}
1781
1782static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1783{
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001784 unsigned int status;
1785
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001786 /* drain */
1787 do {
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001788 status = readl_relaxed(port->membase + USR1);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001789 } while (~status & USR1_TRDY);
1790
1791 /* write */
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001792 writel_relaxed(c, port->membase + URTX0);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001793
1794 /* flush */
1795 do {
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001796 status = readl_relaxed(port->membase + USR2);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001797 } while (~status & USR2_TXDC);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001798}
1799#endif
1800
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001801static int imx_rs485_config(struct uart_port *port,
1802 struct serial_rs485 *rs485conf)
1803{
1804 struct imx_port *sport = (struct imx_port *)port;
Baruch Siach7d1cadc2016-02-29 14:34:10 +02001805 unsigned long temp;
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001806
1807 /* unimplemented */
1808 rs485conf->delay_rts_before_send = 0;
1809 rs485conf->delay_rts_after_send = 0;
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001810
1811 /* RTS is required to control the transmitter */
Fabio Estevam7b7e8e82017-01-07 19:29:13 -02001812 if (!sport->have_rtscts && !sport->have_rtsgpio)
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001813 rs485conf->flags &= ~SER_RS485_ENABLED;
1814
1815 if (rs485conf->flags & SER_RS485_ENABLED) {
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001816 /* disable transmitter */
1817 temp = readl(sport->port.membase + UCR2);
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001818 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
Uwe Kleine-König58362d52015-12-13 11:30:03 +01001819 imx_port_rts_active(sport, &temp);
Fabio Estevam1a613622017-01-30 09:12:11 -02001820 else
1821 imx_port_rts_inactive(sport, &temp);
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001822 writel(temp, sport->port.membase + UCR2);
1823 }
1824
Baruch Siach7d1cadc2016-02-29 14:34:10 +02001825 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1826 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
Uwe Kleine-Königd0a06282018-03-02 11:07:26 +01001827 rs485conf->flags & SER_RS485_RX_DURING_TX)
1828 imx_start_rx(port);
Baruch Siach7d1cadc2016-02-29 14:34:10 +02001829
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01001830 port->rs485 = *rs485conf;
1831
1832 return 0;
1833}
1834
Julia Lawall069a47e2016-09-01 19:51:35 +02001835static const struct uart_ops imx_pops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001836 .tx_empty = imx_tx_empty,
1837 .set_mctrl = imx_set_mctrl,
1838 .get_mctrl = imx_get_mctrl,
1839 .stop_tx = imx_stop_tx,
1840 .start_tx = imx_start_tx,
1841 .stop_rx = imx_stop_rx,
1842 .enable_ms = imx_enable_ms,
1843 .break_ctl = imx_break_ctl,
1844 .startup = imx_startup,
1845 .shutdown = imx_shutdown,
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001846 .flush_buffer = imx_flush_buffer,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001847 .set_termios = imx_set_termios,
1848 .type = imx_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001849 .config_port = imx_config_port,
1850 .verify_port = imx_verify_port,
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001851#if defined(CONFIG_CONSOLE_POLL)
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001852 .poll_init = imx_poll_init,
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001853 .poll_get_char = imx_poll_get_char,
1854 .poll_put_char = imx_poll_put_char,
1855#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001856};
1857
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001858static struct imx_port *imx_ports[UART_NR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001859
1860#ifdef CONFIG_SERIAL_IMX_CONSOLE
Russell Kingd3587882006-03-20 20:00:09 +00001861static void imx_console_putchar(struct uart_port *port, int ch)
1862{
1863 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001864
Shawn Guofe6b5402011-06-25 02:04:33 +08001865 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
Russell Kingd3587882006-03-20 20:00:09 +00001866 barrier();
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001867
1868 writel(ch, sport->port.membase + URTX0);
Russell Kingd3587882006-03-20 20:00:09 +00001869}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001870
1871/*
1872 * Interrupts are disabled on entering
1873 */
1874static void
1875imx_console_write(struct console *co, const char *s, unsigned int count)
1876{
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001877 struct imx_port *sport = imx_ports[co->index];
Dirk Behme0ad5a812011-12-22 09:57:52 +01001878 struct imx_port_ucrs old_ucr;
1879 unsigned int ucr1;
Shawn Guof30e8262013-02-18 13:15:36 +08001880 unsigned long flags = 0;
Thomas Gleixner677fe552013-02-14 21:01:06 +01001881 int locked = 1;
Xinyu Chen9ec18822012-08-27 09:36:51 +02001882
Thomas Gleixner677fe552013-02-14 21:01:06 +01001883 if (sport->port.sysrq)
1884 locked = 0;
1885 else if (oops_in_progress)
1886 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1887 else
1888 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001889
1890 /*
Dirk Behme0ad5a812011-12-22 09:57:52 +01001891 * First, save UCR1/2/3 and then disable interrupts
Linus Torvalds1da177e2005-04-16 15:20:36 -07001892 */
Dirk Behme0ad5a812011-12-22 09:57:52 +01001893 imx_port_ucrs_save(&sport->port, &old_ucr);
1894 ucr1 = old_ucr.ucr1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895
Shawn Guofe6b5402011-06-25 02:04:33 +08001896 if (is_imx1_uart(sport))
1897 ucr1 |= IMX1_UCR1_UARTCLKEN;
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001898 ucr1 |= UCR1_UARTEN;
1899 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1900
1901 writel(ucr1, sport->port.membase + UCR1);
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001902
Dirk Behme0ad5a812011-12-22 09:57:52 +01001903 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001904
Russell Kingd3587882006-03-20 20:00:09 +00001905 uart_console_write(&sport->port, s, count, imx_console_putchar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001906
1907 /*
1908 * Finally, wait for transmitter to become empty
Dirk Behme0ad5a812011-12-22 09:57:52 +01001909 * and restore UCR1/2/3
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001911 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001912
Dirk Behme0ad5a812011-12-22 09:57:52 +01001913 imx_port_ucrs_restore(&sport->port, &old_ucr);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001914
Thomas Gleixner677fe552013-02-14 21:01:06 +01001915 if (locked)
1916 spin_unlock_irqrestore(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917}
1918
1919/*
1920 * If the port was already initialised (eg, by a boot loader),
1921 * try to determine the current setup.
1922 */
1923static void __init
1924imx_console_get_options(struct imx_port *sport, int *baud,
1925 int *parity, int *bits)
1926{
Sascha Hauer587897f2005-04-29 22:46:40 +01001927
Roel Kluin2e2eb502009-12-09 12:31:36 -08001928 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929 /* ok, the port was enabled */
Sachin Kamat82313e62013-01-07 10:25:02 +05301930 unsigned int ucr2, ubir, ubmr, uartclk;
Sascha Hauer587897f2005-04-29 22:46:40 +01001931 unsigned int baud_raw;
1932 unsigned int ucfr_rfdiv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001933
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001934 ucr2 = readl(sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001935
1936 *parity = 'n';
1937 if (ucr2 & UCR2_PREN) {
1938 if (ucr2 & UCR2_PROE)
1939 *parity = 'o';
1940 else
1941 *parity = 'e';
1942 }
1943
1944 if (ucr2 & UCR2_WS)
1945 *bits = 8;
1946 else
1947 *bits = 7;
1948
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001949 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1950 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001951
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001952 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
Sascha Hauer587897f2005-04-29 22:46:40 +01001953 if (ucfr_rfdiv == 6)
1954 ucfr_rfdiv = 7;
1955 else
1956 ucfr_rfdiv = 6 - ucfr_rfdiv;
1957
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001958 uartclk = clk_get_rate(sport->clk_per);
Sascha Hauer587897f2005-04-29 22:46:40 +01001959 uartclk /= ucfr_rfdiv;
1960
1961 { /*
1962 * The next code provides exact computation of
1963 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1964 * without need of float support or long long division,
1965 * which would be required to prevent 32bit arithmetic overflow
1966 */
1967 unsigned int mul = ubir + 1;
1968 unsigned int div = 16 * (ubmr + 1);
1969 unsigned int rem = uartclk % div;
1970
1971 baud_raw = (uartclk / div) * mul;
1972 baud_raw += (rem * mul + div / 2) / div;
1973 *baud = (baud_raw + 50) / 100 * 100;
1974 }
1975
Sachin Kamat82313e62013-01-07 10:25:02 +05301976 if (*baud != baud_raw)
Sachin Kamat50bbdba2013-01-07 10:25:05 +05301977 pr_info("Console IMX rounded baud rate from %d to %d\n",
Sascha Hauer587897f2005-04-29 22:46:40 +01001978 baud_raw, *baud);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979 }
1980}
1981
1982static int __init
1983imx_console_setup(struct console *co, char *options)
1984{
1985 struct imx_port *sport;
1986 int baud = 9600;
1987 int bits = 8;
1988 int parity = 'n';
1989 int flow = 'n';
Huang Shijie1cf93e02013-06-28 13:39:42 +08001990 int retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001991
1992 /*
1993 * Check whether an invalid uart number has been specified, and
1994 * if so, search for the first available port that does have
1995 * console support.
1996 */
1997 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1998 co->index = 0;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001999 sport = imx_ports[co->index];
Sachin Kamat82313e62013-01-07 10:25:02 +05302000 if (sport == NULL)
Eric Lammertse76afc42009-05-19 20:53:20 -04002001 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002002
Huang Shijie1cf93e02013-06-28 13:39:42 +08002003 /* For setting the registers, we only need to enable the ipg clock. */
2004 retval = clk_prepare_enable(sport->clk_ipg);
2005 if (retval)
2006 goto error_console;
2007
Linus Torvalds1da177e2005-04-16 15:20:36 -07002008 if (options)
2009 uart_parse_options(options, &baud, &parity, &bits, &flow);
2010 else
2011 imx_console_get_options(sport, &baud, &parity, &bits);
2012
Lucas Stachcc323822015-09-04 17:52:37 +02002013 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
Sascha Hauer587897f2005-04-29 22:46:40 +01002014
Huang Shijie1cf93e02013-06-28 13:39:42 +08002015 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2016
Fabio Estevam0c727a42015-08-18 12:43:12 -03002017 if (retval) {
Fugang Duanbc0cecf2020-11-11 10:51:36 +08002018 clk_disable_unprepare(sport->clk_ipg);
Fabio Estevam0c727a42015-08-18 12:43:12 -03002019 goto error_console;
2020 }
2021
Fugang Duanbc0cecf2020-11-11 10:51:36 +08002022 retval = clk_prepare_enable(sport->clk_per);
Fabio Estevam0c727a42015-08-18 12:43:12 -03002023 if (retval)
Fugang Duanbc0cecf2020-11-11 10:51:36 +08002024 clk_disable_unprepare(sport->clk_ipg);
Huang Shijie1cf93e02013-06-28 13:39:42 +08002025
2026error_console:
2027 return retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002028}
2029
Vincent Sanders9f4426d2005-10-01 22:56:34 +01002030static struct uart_driver imx_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031static struct console imx_console = {
Sascha Hauere3d13ff2008-07-05 10:02:48 +02002032 .name = DEV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002033 .write = imx_console_write,
2034 .device = uart_console_device,
2035 .setup = imx_console_setup,
2036 .flags = CON_PRINTBUFFER,
2037 .index = -1,
2038 .data = &imx_reg,
2039};
2040
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041#define IMX_CONSOLE &imx_console
Lucas Stach913c6c02015-08-28 11:56:19 +02002042
2043#ifdef CONFIG_OF
2044static void imx_console_early_putchar(struct uart_port *port, int ch)
2045{
2046 while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
2047 cpu_relax();
2048
2049 writel_relaxed(ch, port->membase + URTX0);
2050}
2051
2052static void imx_console_early_write(struct console *con, const char *s,
2053 unsigned count)
2054{
2055 struct earlycon_device *dev = con->data;
2056
2057 uart_console_write(&dev->port, s, count, imx_console_early_putchar);
2058}
2059
2060static int __init
2061imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2062{
2063 if (!dev->port.membase)
2064 return -ENODEV;
2065
2066 dev->con->write = imx_console_early_write;
2067
2068 return 0;
2069}
2070OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2071OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2072#endif
2073
Linus Torvalds1da177e2005-04-16 15:20:36 -07002074#else
2075#define IMX_CONSOLE NULL
2076#endif
2077
2078static struct uart_driver imx_reg = {
2079 .owner = THIS_MODULE,
2080 .driver_name = DRIVER_NAME,
Sascha Hauere3d13ff2008-07-05 10:02:48 +02002081 .dev_name = DEV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002082 .major = SERIAL_IMX_MAJOR,
2083 .minor = MINOR_START,
2084 .nr = ARRAY_SIZE(imx_ports),
2085 .cons = IMX_CONSOLE,
2086};
2087
Shawn Guo22698aa2011-06-25 02:04:34 +08002088#ifdef CONFIG_OF
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01002089/*
2090 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2091 * could successfully get all information from dt or a negative errno.
2092 */
Shawn Guo22698aa2011-06-25 02:04:34 +08002093static int serial_imx_probe_dt(struct imx_port *sport,
2094 struct platform_device *pdev)
2095{
2096 struct device_node *np = pdev->dev.of_node;
Shawn Guoff059672011-09-22 14:48:13 +08002097 int ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08002098
LABBE Corentin5f8b9042015-11-24 15:36:57 +01002099 sport->devdata = of_device_get_match_data(&pdev->dev);
2100 if (!sport->devdata)
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01002101 /* no device tree device */
2102 return 1;
Shawn Guo22698aa2011-06-25 02:04:34 +08002103
Shawn Guoff059672011-09-22 14:48:13 +08002104 ret = of_alias_get_id(np, "serial");
2105 if (ret < 0) {
2106 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
Uwe Kleine-Königa197a192011-12-14 21:26:51 +01002107 return ret;
Shawn Guoff059672011-09-22 14:48:13 +08002108 }
2109 sport->port.line = ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08002110
Geert Uytterhoeven1006ed72016-04-22 17:22:21 +02002111 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2112 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
Shawn Guo22698aa2011-06-25 02:04:34 +08002113 sport->have_rtscts = 1;
2114
Huang Shijie20ff2fe2013-05-30 14:07:12 +08002115 if (of_get_property(np, "fsl,dte-mode", NULL))
2116 sport->dte_mode = 1;
2117
Fabio Estevam7b7e8e82017-01-07 19:29:13 -02002118 if (of_get_property(np, "rts-gpios", NULL))
2119 sport->have_rtsgpio = 1;
2120
Shawn Guo22698aa2011-06-25 02:04:34 +08002121 return 0;
2122}
2123#else
2124static inline int serial_imx_probe_dt(struct imx_port *sport,
2125 struct platform_device *pdev)
2126{
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01002127 return 1;
Shawn Guo22698aa2011-06-25 02:04:34 +08002128}
2129#endif
2130
2131static void serial_imx_probe_pdata(struct imx_port *sport,
2132 struct platform_device *pdev)
2133{
Jingoo Han574de552013-07-30 17:06:57 +09002134 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
Shawn Guo22698aa2011-06-25 02:04:34 +08002135
2136 sport->port.line = pdev->id;
2137 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2138
2139 if (!pdata)
2140 return;
2141
2142 if (pdata->flags & IMXUART_HAVE_RTSCTS)
2143 sport->have_rtscts = 1;
Shawn Guo22698aa2011-06-25 02:04:34 +08002144}
2145
Sascha Hauer2582d8c2008-07-05 10:02:45 +02002146static int serial_imx_probe(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002147{
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002148 struct imx_port *sport;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002149 void __iomem *base;
Fabio Estevam8a61f0c2015-06-17 17:35:43 -03002150 int ret = 0, reg;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002151 struct resource *res;
Uwe Kleine-König842633b2015-02-24 11:17:07 +01002152 int txirq, rxirq, rtsirq;
Sascha Hauer5b802342006-05-04 14:07:42 +01002153
Sachin Kamat42d34192013-01-07 10:25:06 +05302154 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002155 if (!sport)
2156 return -ENOMEM;
2157
Shawn Guo22698aa2011-06-25 02:04:34 +08002158 ret = serial_imx_probe_dt(sport, pdev);
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01002159 if (ret > 0)
Shawn Guo22698aa2011-06-25 02:04:34 +08002160 serial_imx_probe_pdata(sport, pdev);
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01002161 else if (ret < 0)
Sachin Kamat42d34192013-01-07 10:25:06 +05302162 return ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08002163
Geert Uytterhoeven24182ff2018-02-23 14:38:31 +01002164 if (sport->port.line >= ARRAY_SIZE(imx_ports)) {
2165 dev_err(&pdev->dev, "serial%d out of range\n",
2166 sport->port.line);
2167 return -EINVAL;
2168 }
2169
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Alexander Shiyanda82f992014-02-22 16:01:33 +04002171 base = devm_ioremap_resource(&pdev->dev, res);
2172 if (IS_ERR(base))
2173 return PTR_ERR(base);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002174
Uwe Kleine-König842633b2015-02-24 11:17:07 +01002175 rxirq = platform_get_irq(pdev, 0);
2176 txirq = platform_get_irq(pdev, 1);
2177 rtsirq = platform_get_irq(pdev, 2);
2178
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002179 sport->port.dev = &pdev->dev;
2180 sport->port.mapbase = res->start;
2181 sport->port.membase = base;
2182 sport->port.type = PORT_IMX,
2183 sport->port.iotype = UPIO_MEM;
Uwe Kleine-König842633b2015-02-24 11:17:07 +01002184 sport->port.irq = rxirq;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002185 sport->port.fifosize = 32;
2186 sport->port.ops = &imx_pops;
Uwe Kleine-König17b8f2a2015-02-24 11:17:11 +01002187 sport->port.rs485_config = imx_rs485_config;
2188 sport->port.rs485.flags =
2189 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002190 sport->port.flags = UPF_BOOT_AUTOCONF;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002191 init_timer(&sport->timer);
2192 sport->timer.function = imx_timeout;
2193 sport->timer.data = (unsigned long)sport;
Sascha Hauer38a41fd2008-07-05 10:02:46 +02002194
Uwe Kleine-König58362d52015-12-13 11:30:03 +01002195 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2196 if (IS_ERR(sport->gpios))
2197 return PTR_ERR(sport->gpios);
2198
Sascha Hauer3a9465f2012-03-07 09:31:43 +01002199 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2200 if (IS_ERR(sport->clk_ipg)) {
2201 ret = PTR_ERR(sport->clk_ipg);
Uwe Kleine-König833462e2012-08-20 09:57:04 +02002202 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
Sachin Kamat42d34192013-01-07 10:25:06 +05302203 return ret;
Sascha Hauer38a41fd2008-07-05 10:02:46 +02002204 }
Sascha Hauer38a41fd2008-07-05 10:02:46 +02002205
Sascha Hauer3a9465f2012-03-07 09:31:43 +01002206 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2207 if (IS_ERR(sport->clk_per)) {
2208 ret = PTR_ERR(sport->clk_per);
Uwe Kleine-König833462e2012-08-20 09:57:04 +02002209 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
Sachin Kamat42d34192013-01-07 10:25:06 +05302210 return ret;
Sascha Hauer3a9465f2012-03-07 09:31:43 +01002211 }
2212
Sascha Hauer3a9465f2012-03-07 09:31:43 +01002213 sport->port.uartclk = clk_get_rate(sport->clk_per);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002214
Fabio Estevam8a61f0c2015-06-17 17:35:43 -03002215 /* For register access, we only need to enable the ipg clock. */
2216 ret = clk_prepare_enable(sport->clk_ipg);
Uwe Kleine-König1e512d42016-09-08 14:27:53 +02002217 if (ret) {
Christoph Niedermaier2690f972023-12-24 10:32:09 +01002218 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
Fabio Estevam8a61f0c2015-06-17 17:35:43 -03002219 return ret;
Uwe Kleine-König1e512d42016-09-08 14:27:53 +02002220 }
Fabio Estevam8a61f0c2015-06-17 17:35:43 -03002221
2222 /* Disable interrupts before requesting them */
2223 reg = readl_relaxed(sport->port.membase + UCR1);
2224 reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2225 UCR1_TXMPTYEN | UCR1_RTSDEN);
2226 writel_relaxed(reg, sport->port.membase + UCR1);
2227
Uwe Kleine-Könige61c38d2017-04-04 11:18:51 +02002228 if (!is_imx1_uart(sport) && sport->dte_mode) {
2229 /*
2230 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2231 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2232 * and DCD (when they are outputs) or enables the respective
2233 * irqs. So set this bit early, i.e. before requesting irqs.
2234 */
Uwe Kleine-König6df765d2017-05-24 21:38:46 +02002235 reg = readl(sport->port.membase + UFCR);
2236 if (!(reg & UFCR_DCEDTE))
2237 writel(reg | UFCR_DCEDTE, sport->port.membase + UFCR);
Uwe Kleine-Könige61c38d2017-04-04 11:18:51 +02002238
2239 /*
2240 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2241 * enabled later because they cannot be cleared
2242 * (confirmed on i.MX25) which makes them unusable.
2243 */
2244 writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2245 sport->port.membase + UCR3);
2246
2247 } else {
Uwe Kleine-König6df765d2017-05-24 21:38:46 +02002248 unsigned long ucr3 = UCR3_DSR;
2249
2250 reg = readl(sport->port.membase + UFCR);
2251 if (reg & UFCR_DCEDTE)
2252 writel(reg & ~UFCR_DCEDTE, sport->port.membase + UFCR);
2253
2254 if (!is_imx1_uart(sport))
2255 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2256 writel(ucr3, sport->port.membase + UCR3);
Uwe Kleine-Könige61c38d2017-04-04 11:18:51 +02002257 }
2258
Fabio Estevam8a61f0c2015-06-17 17:35:43 -03002259 clk_disable_unprepare(sport->clk_ipg);
2260
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002261 /*
2262 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2263 * chips only have one interrupt.
2264 */
Uwe Kleine-König842633b2015-02-24 11:17:07 +01002265 if (txirq > 0) {
2266 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002267 dev_name(&pdev->dev), sport);
Uwe Kleine-König1e512d42016-09-08 14:27:53 +02002268 if (ret) {
2269 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2270 ret);
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002271 return ret;
Uwe Kleine-König1e512d42016-09-08 14:27:53 +02002272 }
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002273
Uwe Kleine-König842633b2015-02-24 11:17:07 +01002274 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002275 dev_name(&pdev->dev), sport);
Uwe Kleine-König1e512d42016-09-08 14:27:53 +02002276 if (ret) {
2277 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2278 ret);
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002279 return ret;
Uwe Kleine-König1e512d42016-09-08 14:27:53 +02002280 }
Uwe Kleine-Königd428e432018-09-20 14:11:17 +02002281
2282 ret = devm_request_irq(&pdev->dev, rtsirq, imx_rtsint, 0,
2283 dev_name(&pdev->dev), sport);
2284 if (ret) {
2285 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2286 ret);
2287 return ret;
2288 }
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002289 } else {
Uwe Kleine-König842633b2015-02-24 11:17:07 +01002290 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002291 dev_name(&pdev->dev), sport);
Uwe Kleine-König1e512d42016-09-08 14:27:53 +02002292 if (ret) {
2293 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002294 return ret;
Uwe Kleine-König1e512d42016-09-08 14:27:53 +02002295 }
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002296 }
2297
Shawn Guo22698aa2011-06-25 02:04:34 +08002298 imx_ports[sport->port.line] = sport;
Sascha Hauer5b802342006-05-04 14:07:42 +01002299
Richard Zhao0a86a862012-09-18 16:14:58 +08002300 platform_set_drvdata(pdev, sport);
Sascha Hauer2582d8c2008-07-05 10:02:45 +02002301
Alexander Shiyan45af7802014-02-22 16:01:35 +04002302 return uart_add_one_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002303}
2304
Sascha Hauer2582d8c2008-07-05 10:02:45 +02002305static int serial_imx_remove(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002306{
Sascha Hauer2582d8c2008-07-05 10:02:45 +02002307 struct imx_port *sport = platform_get_drvdata(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002308
Alexander Shiyan45af7802014-02-22 16:01:35 +04002309 return uart_remove_one_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002310}
2311
Eduardo Valentinc868cbb2015-08-11 10:21:23 -07002312static void serial_imx_restore_context(struct imx_port *sport)
2313{
2314 if (!sport->context_saved)
2315 return;
2316
2317 writel(sport->saved_reg[4], sport->port.membase + UFCR);
2318 writel(sport->saved_reg[5], sport->port.membase + UESC);
2319 writel(sport->saved_reg[6], sport->port.membase + UTIM);
2320 writel(sport->saved_reg[7], sport->port.membase + UBIR);
2321 writel(sport->saved_reg[8], sport->port.membase + UBMR);
2322 writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2323 writel(sport->saved_reg[0], sport->port.membase + UCR1);
2324 writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2325 writel(sport->saved_reg[2], sport->port.membase + UCR3);
2326 writel(sport->saved_reg[3], sport->port.membase + UCR4);
2327 sport->context_saved = false;
2328}
2329
2330static void serial_imx_save_context(struct imx_port *sport)
2331{
2332 /* Save necessary regs */
2333 sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2334 sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2335 sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2336 sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2337 sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2338 sport->saved_reg[5] = readl(sport->port.membase + UESC);
2339 sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2340 sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2341 sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2342 sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2343 sport->context_saved = true;
2344}
2345
Eduardo Valentin189550b2015-08-11 10:21:21 -07002346static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2347{
2348 unsigned int val;
2349
2350 val = readl(sport->port.membase + UCR3);
2351 if (on)
2352 val |= UCR3_AWAKEN;
2353 else
2354 val &= ~UCR3_AWAKEN;
2355 writel(val, sport->port.membase + UCR3);
Eduardo Valentinbc857342015-08-11 10:21:22 -07002356
Fabio Estevame6e7d6b2018-01-04 15:58:34 -02002357 if (sport->have_rtscts) {
2358 val = readl(sport->port.membase + UCR1);
2359 if (on)
2360 val |= UCR1_RTSDEN;
2361 else
2362 val &= ~UCR1_RTSDEN;
2363 writel(val, sport->port.membase + UCR1);
2364 }
Eduardo Valentin189550b2015-08-11 10:21:21 -07002365}
2366
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002367static int imx_serial_port_suspend_noirq(struct device *dev)
2368{
2369 struct platform_device *pdev = to_platform_device(dev);
2370 struct imx_port *sport = platform_get_drvdata(pdev);
2371 int ret;
2372
2373 ret = clk_enable(sport->clk_ipg);
2374 if (ret)
2375 return ret;
2376
Eduardo Valentinc868cbb2015-08-11 10:21:23 -07002377 serial_imx_save_context(sport);
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002378
2379 clk_disable(sport->clk_ipg);
2380
2381 return 0;
2382}
2383
2384static int imx_serial_port_resume_noirq(struct device *dev)
2385{
2386 struct platform_device *pdev = to_platform_device(dev);
2387 struct imx_port *sport = platform_get_drvdata(pdev);
2388 int ret;
2389
2390 ret = clk_enable(sport->clk_ipg);
2391 if (ret)
2392 return ret;
2393
Eduardo Valentinc868cbb2015-08-11 10:21:23 -07002394 serial_imx_restore_context(sport);
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002395
2396 clk_disable(sport->clk_ipg);
2397
2398 return 0;
2399}
2400
2401static int imx_serial_port_suspend(struct device *dev)
2402{
2403 struct platform_device *pdev = to_platform_device(dev);
2404 struct imx_port *sport = platform_get_drvdata(pdev);
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002405
2406 /* enable wakeup from i.MX UART */
Eduardo Valentin189550b2015-08-11 10:21:21 -07002407 serial_imx_enable_wakeup(sport, true);
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002408
2409 uart_suspend_port(&imx_reg, &sport->port);
Maxim Yu. Osipov81b289c2017-08-14 16:27:49 +02002410 disable_irq(sport->port.irq);
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002411
Martin Fuzzey29add682016-01-05 16:53:31 +01002412 /* Needed to enable clock in suspend_noirq */
2413 return clk_prepare(sport->clk_ipg);
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002414}
2415
2416static int imx_serial_port_resume(struct device *dev)
2417{
2418 struct platform_device *pdev = to_platform_device(dev);
2419 struct imx_port *sport = platform_get_drvdata(pdev);
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002420
2421 /* disable wakeup from i.MX UART */
Eduardo Valentin189550b2015-08-11 10:21:21 -07002422 serial_imx_enable_wakeup(sport, false);
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002423
2424 uart_resume_port(&imx_reg, &sport->port);
Maxim Yu. Osipov81b289c2017-08-14 16:27:49 +02002425 enable_irq(sport->port.irq);
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002426
Martin Fuzzey29add682016-01-05 16:53:31 +01002427 clk_unprepare(sport->clk_ipg);
2428
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002429 return 0;
2430}
2431
2432static const struct dev_pm_ops imx_serial_port_pm_ops = {
2433 .suspend_noirq = imx_serial_port_suspend_noirq,
2434 .resume_noirq = imx_serial_port_resume_noirq,
2435 .suspend = imx_serial_port_suspend,
2436 .resume = imx_serial_port_resume,
2437};
2438
Russell King3ae5eae2005-11-09 22:32:44 +00002439static struct platform_driver serial_imx_driver = {
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01002440 .probe = serial_imx_probe,
2441 .remove = serial_imx_remove,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002442
Shawn Guofe6b5402011-06-25 02:04:33 +08002443 .id_table = imx_uart_devtype,
Russell King3ae5eae2005-11-09 22:32:44 +00002444 .driver = {
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01002445 .name = "imx-uart",
Shawn Guo22698aa2011-06-25 02:04:34 +08002446 .of_match_table = imx_uart_dt_ids,
Shenwei Wang90bb6bd2015-07-30 10:32:36 -05002447 .pm = &imx_serial_port_pm_ops,
Russell King3ae5eae2005-11-09 22:32:44 +00002448 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002449};
2450
2451static int __init imx_serial_init(void)
2452{
Fabio Estevamf0fd1b72014-10-27 14:49:40 -02002453 int ret = uart_register_driver(&imx_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002454
Linus Torvalds1da177e2005-04-16 15:20:36 -07002455 if (ret)
2456 return ret;
2457
Russell King3ae5eae2005-11-09 22:32:44 +00002458 ret = platform_driver_register(&serial_imx_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002459 if (ret != 0)
2460 uart_unregister_driver(&imx_reg);
2461
Uwe Kleine-Königf2278242011-11-22 14:22:55 +01002462 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002463}
2464
2465static void __exit imx_serial_exit(void)
2466{
Russell Kingc889b892005-11-21 17:05:21 +00002467 platform_driver_unregister(&serial_imx_driver);
Sascha Hauer4b300c32007-07-17 13:35:46 +01002468 uart_unregister_driver(&imx_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002469}
2470
2471module_init(imx_serial_init);
2472module_exit(imx_serial_exit);
2473
2474MODULE_AUTHOR("Sascha Hauer");
2475MODULE_DESCRIPTION("IMX generic serial port driver");
2476MODULE_LICENSE("GPL");
Kay Sieverse169c132008-04-15 14:34:35 -07002477MODULE_ALIAS("platform:imx-uart");