blob: c4f50a328501867d179b094146098313b82cdb1e [file] [log] [blame]
Michael Hennerich2714d9a2007-10-11 00:29:49 +08001/*
2 * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/interrupt.h>
10#include <asm/bfin-global.h>
11#include <asm/reboot.h>
Mike Frysingercdbf4c32008-10-13 11:33:43 +080012#include <asm/bfrom.h>
Michael Hennerich2714d9a2007-10-11 00:29:49 +080013
Mike Frysinger6a42a912008-04-23 08:01:31 +080014/* A system soft reset makes external memory unusable so force
15 * this function into L1. We use the compiler ssync here rather
16 * than SSYNC() because it's safe (no interrupts and such) and
17 * we save some L1. We do not need to force sanity in the SYSCR
18 * register as the BMODE selection bit is cleared by the soft
19 * reset while the Core B bit (on dual core parts) is cleared by
20 * the core reset.
Michael Hennerich2714d9a2007-10-11 00:29:49 +080021 */
Mike Frysingeradab7eb2009-02-04 16:49:45 +080022__attribute__ ((__l1_text__, __noreturn__))
Mike Frysingera6595bf2009-02-04 16:49:45 +080023static void bfin_reset(void)
Michael Hennerich2714d9a2007-10-11 00:29:49 +080024{
Bob Liub5affb02012-05-16 17:37:24 +080025#ifndef CONFIG_BF60x
Mike Frysinger80310392011-05-02 00:00:35 -040026 if (!ANOMALY_05000353 && !ANOMALY_05000386)
27 bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
28
Mike Frysinger6a42a912008-04-23 08:01:31 +080029 /* Wait for completion of "system" events such as cache line
30 * line fills so that we avoid infinite stalls later on as
31 * much as possible. This code is in L1, so it won't trigger
32 * any such event after this point in time.
33 */
34 __builtin_bfin_ssync();
Michael Hennerich2714d9a2007-10-11 00:29:49 +080035
Mike Frysinger80310392011-05-02 00:00:35 -040036 /* Initiate System software reset. */
37 bfin_write_SWRST(0x7);
38
39 /* Due to the way reset is handled in the hardware, we need
40 * to delay for 10 SCLKS. The only reliable way to do this is
41 * to calculate the CCLK/SCLK ratio and multiply 10. For now,
42 * we'll assume worse case which is a 1:15 ratio.
Mike Frysingeradab7eb2009-02-04 16:49:45 +080043 */
Mike Frysinger80310392011-05-02 00:00:35 -040044 asm(
45 "LSETUP (1f, 1f) LC0 = %0\n"
46 "1: nop;"
47 :
48 : "a" (15 * 10)
49 : "LC0", "LB0", "LT0"
50 );
Michael Hennerich444ad822008-01-22 18:38:02 +080051
Mike Frysinger80310392011-05-02 00:00:35 -040052 /* Clear System software reset */
53 bfin_write_SWRST(0);
Michael Hennerich444ad822008-01-22 18:38:02 +080054
Mike Frysinger80310392011-05-02 00:00:35 -040055 /* The BF526 ROM will crash during reset */
Mike Frysingeradab7eb2009-02-04 16:49:45 +080056#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
Mike Frysingerb0d3dc12011-06-30 00:49:30 -040057 /* Seems to be fixed with newer parts though ... */
58 if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
59 bfin_read_SWRST();
Mike Frysingeradab7eb2009-02-04 16:49:45 +080060#endif
Mike Frysinger80310392011-05-02 00:00:35 -040061 /* Wait for the SWRST write to complete. Cannot rely on SSYNC
62 * though as the System state is all reset now.
63 */
64 asm(
65 "LSETUP (1f, 1f) LC1 = %0\n"
66 "1: nop;"
67 :
68 : "a" (15 * 1)
69 : "LC1", "LB1", "LT1"
70 );
Mike Frysinger6a42a912008-04-23 08:01:31 +080071
Mike Frysingeradab7eb2009-02-04 16:49:45 +080072 while (1)
Mike Frysinger6a42a912008-04-23 08:01:31 +080073 /* Issue core reset */
Michael Hennerich2714d9a2007-10-11 00:29:49 +080074 asm("raise 1");
Bob Liub5affb02012-05-16 17:37:24 +080075#else
76 while (1)
77 bfin_write_RCU0_CTL(0x1);
78#endif
Michael Hennerich2714d9a2007-10-11 00:29:49 +080079}
80
81__attribute__((weak))
82void native_machine_restart(char *cmd)
83{
84}
85
86void machine_restart(char *cmd)
87{
88 native_machine_restart(cmd);
Graf Yang8f658732008-11-18 17:48:22 +080089 if (smp_processor_id())
90 smp_call_function((void *)bfin_reset, 0, 1);
Mike Frysingercdbf4c32008-10-13 11:33:43 +080091 else
Graf Yang8f658732008-11-18 17:48:22 +080092 bfin_reset();
Michael Hennerich2714d9a2007-10-11 00:29:49 +080093}
94
95__attribute__((weak))
96void native_machine_halt(void)
97{
98 idle_with_irq_disabled();
99}
100
101void machine_halt(void)
102{
103 native_machine_halt();
104}
105
106__attribute__((weak))
107void native_machine_power_off(void)
108{
109 idle_with_irq_disabled();
110}
111
112void machine_power_off(void)
113{
114 native_machine_power_off();
115}