Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 1 | /* |
Uwe Zeisberger | f30c226 | 2006-10-03 23:01:26 +0200 | [diff] [blame] | 2 | * arch/xtensa/kernel/pci.c |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 3 | * |
| 4 | * PCI bios-type initialisation for PCI machines |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your |
| 9 | * option) any later version. |
| 10 | * |
| 11 | * Copyright (C) 2001-2005 Tensilica Inc. |
| 12 | * |
| 13 | * Based largely on work from Cort (ppc/kernel/pci.c) |
| 14 | * IO functions copied from sparc. |
| 15 | * |
| 16 | * Chris Zankel <chris@zankel.net> |
| 17 | * |
| 18 | */ |
| 19 | |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 20 | #include <linux/kernel.h> |
| 21 | #include <linux/pci.h> |
| 22 | #include <linux/delay.h> |
| 23 | #include <linux/string.h> |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/sched.h> |
| 26 | #include <linux/errno.h> |
| 27 | #include <linux/bootmem.h> |
| 28 | |
| 29 | #include <asm/pci-bridge.h> |
| 30 | #include <asm/platform.h> |
| 31 | |
| 32 | #undef DEBUG |
| 33 | |
| 34 | #ifdef DEBUG |
| 35 | #define DBG(x...) printk(x) |
| 36 | #else |
| 37 | #define DBG(x...) |
| 38 | #endif |
| 39 | |
| 40 | /* PCI Controller */ |
| 41 | |
| 42 | |
| 43 | /* |
| 44 | * pcibios_alloc_controller |
| 45 | * pcibios_enable_device |
| 46 | * pcibios_fixups |
| 47 | * pcibios_align_resource |
| 48 | * pcibios_fixup_bus |
| 49 | * pcibios_setup |
| 50 | * pci_bus_add_device |
| 51 | * pci_mmap_page_range |
| 52 | */ |
| 53 | |
| 54 | struct pci_controller* pci_ctrl_head; |
| 55 | struct pci_controller** pci_ctrl_tail = &pci_ctrl_head; |
| 56 | |
| 57 | static int pci_bus_count; |
| 58 | |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 59 | /* |
| 60 | * We need to avoid collisions with `mirrored' VGA ports |
| 61 | * and other strange ISA hardware, so we always want the |
| 62 | * addresses to be allocated in the 0x000-0x0ff region |
| 63 | * modulo 0x400. |
| 64 | * |
| 65 | * Why? Because some silly external IO cards only decode |
| 66 | * the low 10 bits of the IO address. The 0x00-0xff region |
| 67 | * is reserved for motherboard devices that decode all 16 |
| 68 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, |
| 69 | * but we want to try to avoid allocating at 0x2900-0x2bff |
| 70 | * which might have be mirrored at 0x0100-0x03ff.. |
| 71 | */ |
Dominik Brodowski | b26b2d4 | 2010-01-01 17:40:49 +0100 | [diff] [blame] | 72 | resource_size_t |
Dominik Brodowski | 3b7a17f | 2010-01-01 17:40:50 +0100 | [diff] [blame] | 73 | pcibios_align_resource(void *data, const struct resource *res, |
| 74 | resource_size_t size, resource_size_t align) |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 75 | { |
| 76 | struct pci_dev *dev = data; |
Dominik Brodowski | b26b2d4 | 2010-01-01 17:40:49 +0100 | [diff] [blame] | 77 | resource_size_t start = res->start; |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 78 | |
| 79 | if (res->flags & IORESOURCE_IO) { |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 80 | if (size > 0x100) { |
| 81 | printk(KERN_ERR "PCI: I/O Region %s/%d too large" |
Chris Zankel | 9ec55a9 | 2005-06-30 02:59:00 -0700 | [diff] [blame] | 82 | " (%ld bytes)\n", pci_name(dev), |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 83 | dev->resource - res, size); |
| 84 | } |
| 85 | |
Dominik Brodowski | b26b2d4 | 2010-01-01 17:40:49 +0100 | [diff] [blame] | 86 | if (start & 0x300) |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 87 | start = (start + 0x3ff) & ~0x3ff; |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 88 | } |
Dominik Brodowski | b26b2d4 | 2010-01-01 17:40:49 +0100 | [diff] [blame] | 89 | |
| 90 | return start; |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | int |
| 94 | pcibios_enable_resources(struct pci_dev *dev, int mask) |
| 95 | { |
| 96 | u16 cmd, old_cmd; |
| 97 | int idx; |
| 98 | struct resource *r; |
| 99 | |
| 100 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 101 | old_cmd = cmd; |
| 102 | for(idx=0; idx<6; idx++) { |
| 103 | r = &dev->resource[idx]; |
| 104 | if (!r->start && r->end) { |
| 105 | printk (KERN_ERR "PCI: Device %s not available because " |
Chris Zankel | 9ec55a9 | 2005-06-30 02:59:00 -0700 | [diff] [blame] | 106 | "of resource collisions\n", pci_name(dev)); |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 107 | return -EINVAL; |
| 108 | } |
| 109 | if (r->flags & IORESOURCE_IO) |
| 110 | cmd |= PCI_COMMAND_IO; |
| 111 | if (r->flags & IORESOURCE_MEM) |
| 112 | cmd |= PCI_COMMAND_MEMORY; |
| 113 | } |
| 114 | if (dev->resource[PCI_ROM_RESOURCE].start) |
| 115 | cmd |= PCI_COMMAND_MEMORY; |
| 116 | if (cmd != old_cmd) { |
| 117 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
Chris Zankel | 9ec55a9 | 2005-06-30 02:59:00 -0700 | [diff] [blame] | 118 | pci_name(dev), old_cmd, cmd); |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 119 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 120 | } |
| 121 | return 0; |
| 122 | } |
| 123 | |
| 124 | struct pci_controller * __init pcibios_alloc_controller(void) |
| 125 | { |
| 126 | struct pci_controller *pci_ctrl; |
| 127 | |
| 128 | pci_ctrl = (struct pci_controller *)alloc_bootmem(sizeof(*pci_ctrl)); |
| 129 | memset(pci_ctrl, 0, sizeof(struct pci_controller)); |
| 130 | |
| 131 | *pci_ctrl_tail = pci_ctrl; |
| 132 | pci_ctrl_tail = &pci_ctrl->next; |
| 133 | |
| 134 | return pci_ctrl; |
| 135 | } |
| 136 | |
Bjorn Helgaas | 7ec303a | 2011-10-28 16:28:19 -0600 | [diff] [blame] | 137 | static void __init pci_controller_apertures(struct pci_controller *pci_ctrl, |
| 138 | struct list_head *resources) |
| 139 | { |
| 140 | struct resource *res; |
| 141 | unsigned long io_offset; |
| 142 | int i; |
| 143 | |
| 144 | io_offset = (unsigned long)pci_ctrl->io_space.base; |
| 145 | res = &pci_ctrl->io_resource; |
| 146 | if (!res->flags) { |
| 147 | if (io_offset) |
| 148 | printk (KERN_ERR "I/O resource not set for host" |
| 149 | " bridge %d\n", pci_ctrl->index); |
| 150 | res->start = 0; |
| 151 | res->end = IO_SPACE_LIMIT; |
| 152 | res->flags = IORESOURCE_IO; |
| 153 | } |
| 154 | res->start += io_offset; |
| 155 | res->end += io_offset; |
Bjorn Helgaas | 4ba2aef | 2012-02-23 20:19:04 -0700 | [diff] [blame] | 156 | pci_add_resource_offset(resources, res, io_offset); |
Bjorn Helgaas | 7ec303a | 2011-10-28 16:28:19 -0600 | [diff] [blame] | 157 | |
| 158 | for (i = 0; i < 3; i++) { |
| 159 | res = &pci_ctrl->mem_resources[i]; |
| 160 | if (!res->flags) { |
| 161 | if (i > 0) |
| 162 | continue; |
| 163 | printk(KERN_ERR "Memory resource not set for " |
| 164 | "host bridge %d\n", pci_ctrl->index); |
| 165 | res->start = 0; |
| 166 | res->end = ~0U; |
| 167 | res->flags = IORESOURCE_MEM; |
| 168 | } |
| 169 | pci_add_resource(resources, res); |
| 170 | } |
| 171 | } |
| 172 | |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 173 | static int __init pcibios_init(void) |
| 174 | { |
| 175 | struct pci_controller *pci_ctrl; |
Bjorn Helgaas | 7ec303a | 2011-10-28 16:28:19 -0600 | [diff] [blame] | 176 | struct list_head resources; |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 177 | struct pci_bus *bus; |
| 178 | int next_busno = 0, i; |
| 179 | |
| 180 | printk("PCI: Probing PCI hardware\n"); |
| 181 | |
| 182 | /* Scan all of the recorded PCI controllers. */ |
| 183 | for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { |
| 184 | pci_ctrl->last_busno = 0xff; |
Bjorn Helgaas | 7ec303a | 2011-10-28 16:28:19 -0600 | [diff] [blame] | 185 | INIT_LIST_HEAD(&resources); |
| 186 | pci_controller_apertures(pci_ctrl, &resources); |
| 187 | bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno, |
| 188 | pci_ctrl->ops, pci_ctrl, &resources); |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 189 | pci_ctrl->bus = bus; |
| 190 | pci_ctrl->last_busno = bus->subordinate; |
| 191 | if (next_busno <= pci_ctrl->last_busno) |
| 192 | next_busno = pci_ctrl->last_busno+1; |
| 193 | } |
| 194 | pci_bus_count = next_busno; |
| 195 | |
| 196 | return platform_pcibios_fixup(); |
| 197 | } |
| 198 | |
| 199 | subsys_initcall(pcibios_init); |
| 200 | |
| 201 | void __init pcibios_fixup_bus(struct pci_bus *bus) |
| 202 | { |
Bjorn Helgaas | 7ec303a | 2011-10-28 16:28:19 -0600 | [diff] [blame] | 203 | if (bus->parent) { |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 204 | /* This is a subordinate bridge */ |
| 205 | pci_read_bridge_bases(bus); |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 206 | } |
| 207 | } |
| 208 | |
| 209 | char __init *pcibios_setup(char *str) |
| 210 | { |
| 211 | return str; |
| 212 | } |
| 213 | |
Myron Stowe | 9cdce18 | 2011-10-28 15:48:31 -0600 | [diff] [blame] | 214 | void pcibios_set_master(struct pci_dev *dev) |
| 215 | { |
| 216 | /* No special bus mastering setup handling */ |
| 217 | } |
| 218 | |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 219 | /* the next one is stolen from the alpha port... */ |
| 220 | |
| 221 | void __init |
| 222 | pcibios_update_irq(struct pci_dev *dev, int irq) |
| 223 | { |
| 224 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); |
| 225 | } |
| 226 | |
| 227 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
| 228 | { |
| 229 | u16 cmd, old_cmd; |
| 230 | int idx; |
| 231 | struct resource *r; |
| 232 | |
| 233 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 234 | old_cmd = cmd; |
| 235 | for (idx=0; idx<6; idx++) { |
| 236 | r = &dev->resource[idx]; |
| 237 | if (!r->start && r->end) { |
| 238 | printk(KERN_ERR "PCI: Device %s not available because " |
Chris Zankel | 9ec55a9 | 2005-06-30 02:59:00 -0700 | [diff] [blame] | 239 | "of resource collisions\n", pci_name(dev)); |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 240 | return -EINVAL; |
| 241 | } |
| 242 | if (r->flags & IORESOURCE_IO) |
| 243 | cmd |= PCI_COMMAND_IO; |
| 244 | if (r->flags & IORESOURCE_MEM) |
| 245 | cmd |= PCI_COMMAND_MEMORY; |
| 246 | } |
| 247 | if (cmd != old_cmd) { |
| 248 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
Chris Zankel | 9ec55a9 | 2005-06-30 02:59:00 -0700 | [diff] [blame] | 249 | pci_name(dev), old_cmd, cmd); |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 250 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 251 | } |
| 252 | |
| 253 | return 0; |
| 254 | } |
| 255 | |
| 256 | #ifdef CONFIG_PROC_FS |
| 257 | |
| 258 | /* |
| 259 | * Return the index of the PCI controller for device pdev. |
| 260 | */ |
| 261 | |
| 262 | int |
| 263 | pci_controller_num(struct pci_dev *dev) |
| 264 | { |
| 265 | struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata; |
| 266 | return pci_ctrl->index; |
| 267 | } |
| 268 | |
| 269 | #endif /* CONFIG_PROC_FS */ |
| 270 | |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 271 | /* |
| 272 | * Platform support for /proc/bus/pci/X/Y mmap()s, |
| 273 | * modelled on the sparc64 implementation by Dave Miller. |
| 274 | * -- paulus. |
| 275 | */ |
| 276 | |
| 277 | /* |
| 278 | * Adjust vm_pgoff of VMA such that it is the physical page offset |
| 279 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. |
| 280 | * |
| 281 | * Basically, the user finds the base address for his device which he wishes |
| 282 | * to mmap. They read the 32-bit value from the config space base register, |
| 283 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the |
| 284 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. |
| 285 | * |
| 286 | * Returns negative error code on failure, zero on success. |
| 287 | */ |
| 288 | static __inline__ int |
| 289 | __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma, |
| 290 | enum pci_mmap_state mmap_state) |
| 291 | { |
| 292 | struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata; |
| 293 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; |
| 294 | unsigned long io_offset = 0; |
| 295 | int i, res_bit; |
| 296 | |
| 297 | if (pci_ctrl == 0) |
| 298 | return -EINVAL; /* should never happen */ |
| 299 | |
| 300 | /* If memory, add on the PCI bridge address offset */ |
| 301 | if (mmap_state == pci_mmap_mem) { |
| 302 | res_bit = IORESOURCE_MEM; |
| 303 | } else { |
| 304 | io_offset = (unsigned long)pci_ctrl->io_space.base; |
| 305 | offset += io_offset; |
| 306 | res_bit = IORESOURCE_IO; |
| 307 | } |
| 308 | |
| 309 | /* |
| 310 | * Check that the offset requested corresponds to one of the |
| 311 | * resources of the device. |
| 312 | */ |
| 313 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
| 314 | struct resource *rp = &dev->resource[i]; |
| 315 | int flags = rp->flags; |
| 316 | |
| 317 | /* treat ROM as memory (should be already) */ |
| 318 | if (i == PCI_ROM_RESOURCE) |
| 319 | flags |= IORESOURCE_MEM; |
| 320 | |
| 321 | /* Active and same type? */ |
| 322 | if ((flags & res_bit) == 0) |
| 323 | continue; |
| 324 | |
| 325 | /* In the range of this resource? */ |
| 326 | if (offset < (rp->start & PAGE_MASK) || offset > rp->end) |
| 327 | continue; |
| 328 | |
| 329 | /* found it! construct the final physical address */ |
| 330 | if (mmap_state == pci_mmap_io) |
| 331 | offset += pci_ctrl->io_space.start - io_offset; |
| 332 | vma->vm_pgoff = offset >> PAGE_SHIFT; |
| 333 | return 0; |
| 334 | } |
| 335 | |
| 336 | return -EINVAL; |
| 337 | } |
| 338 | |
| 339 | /* |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 340 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci |
| 341 | * device mapping. |
| 342 | */ |
| 343 | static __inline__ void |
| 344 | __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, |
| 345 | enum pci_mmap_state mmap_state, int write_combine) |
| 346 | { |
| 347 | int prot = pgprot_val(vma->vm_page_prot); |
| 348 | |
| 349 | /* Set to write-through */ |
| 350 | prot &= ~_PAGE_NO_CACHE; |
| 351 | #if 0 |
| 352 | if (!write_combine) |
| 353 | prot |= _PAGE_WRITETHRU; |
| 354 | #endif |
| 355 | vma->vm_page_prot = __pgprot(prot); |
| 356 | } |
| 357 | |
| 358 | /* |
| 359 | * Perform the actual remap of the pages for a PCI device mapping, as |
| 360 | * appropriate for this architecture. The region in the process to map |
| 361 | * is described by vm_start and vm_end members of VMA, the base physical |
| 362 | * address is found in vm_pgoff. |
| 363 | * The pci device structure is provided so that architectures may make mapping |
| 364 | * decisions on a per-device or per-bus basis. |
| 365 | * |
| 366 | * Returns a negative error code on failure, zero on success. |
| 367 | */ |
| 368 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, |
| 369 | enum pci_mmap_state mmap_state, |
| 370 | int write_combine) |
| 371 | { |
| 372 | int ret; |
| 373 | |
| 374 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); |
| 375 | if (ret < 0) |
| 376 | return ret; |
| 377 | |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 378 | __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine); |
| 379 | |
Chris Zankel | 288a60c | 2005-09-22 21:44:23 -0700 | [diff] [blame] | 380 | ret = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
| 381 | vma->vm_end - vma->vm_start,vma->vm_page_prot); |
Chris Zankel | 5a0015d | 2005-06-23 22:01:16 -0700 | [diff] [blame] | 382 | |
| 383 | return ret; |
| 384 | } |