Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1 | /* |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 2 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 18 | #include <linux/slab.h> |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 19 | #include <asm/unaligned.h> |
| 20 | |
Luis R. Rodriguez | af03abe | 2009-09-09 02:33:11 -0700 | [diff] [blame] | 21 | #include "hw.h" |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 22 | #include "hw-ops.h" |
Luis R. Rodriguez | cfe8cba | 2009-09-13 23:39:31 -0700 | [diff] [blame] | 23 | #include "rc.h" |
Luis R. Rodriguez | b622a72 | 2010-04-15 17:39:28 -0400 | [diff] [blame] | 24 | #include "ar9003_mac.h" |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 25 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 26 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 27 | |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 28 | MODULE_AUTHOR("Atheros Communications"); |
| 29 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); |
| 30 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); |
| 31 | MODULE_LICENSE("Dual BSD/GPL"); |
| 32 | |
| 33 | static int __init ath9k_init(void) |
| 34 | { |
| 35 | return 0; |
| 36 | } |
| 37 | module_init(ath9k_init); |
| 38 | |
| 39 | static void __exit ath9k_exit(void) |
| 40 | { |
| 41 | return; |
| 42 | } |
| 43 | module_exit(ath9k_exit); |
| 44 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 45 | /* Private hardware callbacks */ |
| 46 | |
| 47 | static void ath9k_hw_init_cal_settings(struct ath_hw *ah) |
| 48 | { |
| 49 | ath9k_hw_private_ops(ah)->init_cal_settings(ah); |
| 50 | } |
| 51 | |
| 52 | static void ath9k_hw_init_mode_regs(struct ath_hw *ah) |
| 53 | { |
| 54 | ath9k_hw_private_ops(ah)->init_mode_regs(ah); |
| 55 | } |
| 56 | |
Luis R. Rodriguez | 6477396 | 2010-04-15 17:38:17 -0400 | [diff] [blame] | 57 | static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, |
| 58 | struct ath9k_channel *chan) |
| 59 | { |
| 60 | return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); |
| 61 | } |
| 62 | |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 63 | static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) |
| 64 | { |
| 65 | if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) |
| 66 | return; |
| 67 | |
| 68 | ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); |
| 69 | } |
| 70 | |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 71 | static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) |
| 72 | { |
| 73 | /* You will not have this callback if using the old ANI */ |
| 74 | if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) |
| 75 | return; |
| 76 | |
| 77 | ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); |
| 78 | } |
| 79 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 80 | /********************/ |
| 81 | /* Helper Functions */ |
| 82 | /********************/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 83 | |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 84 | static void ath9k_hw_set_clockrate(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 85 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 86 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 87 | struct ath_common *common = ath9k_hw_common(ah); |
| 88 | unsigned int clockrate; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 89 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 90 | if (!ah->curchan) /* should really check for CCK instead */ |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 91 | clockrate = ATH9K_CLOCK_RATE_CCK; |
| 92 | else if (conf->channel->band == IEEE80211_BAND_2GHZ) |
| 93 | clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; |
| 94 | else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) |
| 95 | clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; |
Vasanthakumar Thiagarajan | e555372 | 2010-04-26 15:04:33 -0400 | [diff] [blame] | 96 | else |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 97 | clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; |
| 98 | |
| 99 | if (conf_is_ht40(conf)) |
| 100 | clockrate *= 2; |
| 101 | |
| 102 | common->clockrate = clockrate; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 103 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 104 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 105 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 106 | { |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 107 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 108 | |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 109 | return usecs * common->clockrate; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 110 | } |
| 111 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 112 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 113 | { |
| 114 | int i; |
| 115 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 116 | BUG_ON(timeout < AH_TIME_QUANTUM); |
| 117 | |
| 118 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 119 | if ((REG_READ(ah, reg) & mask) == val) |
| 120 | return true; |
| 121 | |
| 122 | udelay(AH_TIME_QUANTUM); |
| 123 | } |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 124 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 125 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, |
| 126 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
| 127 | timeout, reg, REG_READ(ah, reg), mask, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 128 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 129 | return false; |
| 130 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 131 | EXPORT_SYMBOL(ath9k_hw_wait); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 132 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 133 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) |
| 134 | { |
| 135 | u32 retval; |
| 136 | int i; |
| 137 | |
| 138 | for (i = 0, retval = 0; i < n; i++) { |
| 139 | retval = (retval << 1) | (val & 1); |
| 140 | val >>= 1; |
| 141 | } |
| 142 | return retval; |
| 143 | } |
| 144 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 145 | bool ath9k_get_channel_edges(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 146 | u16 flags, u16 *low, |
| 147 | u16 *high) |
| 148 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 149 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 150 | |
| 151 | if (flags & CHANNEL_5GHZ) { |
| 152 | *low = pCap->low_5ghz_chan; |
| 153 | *high = pCap->high_5ghz_chan; |
| 154 | return true; |
| 155 | } |
| 156 | if ((flags & CHANNEL_2GHZ)) { |
| 157 | *low = pCap->low_2ghz_chan; |
| 158 | *high = pCap->high_2ghz_chan; |
| 159 | return true; |
| 160 | } |
| 161 | return false; |
| 162 | } |
| 163 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 164 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 165 | u8 phy, int kbps, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 166 | u32 frameLen, u16 rateix, |
| 167 | bool shortPreamble) |
| 168 | { |
| 169 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 170 | |
| 171 | if (kbps == 0) |
| 172 | return 0; |
| 173 | |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 174 | switch (phy) { |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 175 | case WLAN_RC_PHY_CCK: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 176 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 177 | if (shortPreamble) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 178 | phyTime >>= 1; |
| 179 | numBits = frameLen << 3; |
| 180 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); |
| 181 | break; |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 182 | case WLAN_RC_PHY_OFDM: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 183 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 184 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
| 185 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 186 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 187 | txTime = OFDM_SIFS_TIME_QUARTER |
| 188 | + OFDM_PREAMBLE_TIME_QUARTER |
| 189 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 190 | } else if (ah->curchan && |
| 191 | IS_CHAN_HALF_RATE(ah->curchan)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 192 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
| 193 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 194 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 195 | txTime = OFDM_SIFS_TIME_HALF + |
| 196 | OFDM_PREAMBLE_TIME_HALF |
| 197 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); |
| 198 | } else { |
| 199 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; |
| 200 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 201 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 202 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME |
| 203 | + (numSymbols * OFDM_SYMBOL_TIME); |
| 204 | } |
| 205 | break; |
| 206 | default: |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 207 | ath_err(ath9k_hw_common(ah), |
| 208 | "Unknown phy %u (rate ix %u)\n", phy, rateix); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 209 | txTime = 0; |
| 210 | break; |
| 211 | } |
| 212 | |
| 213 | return txTime; |
| 214 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 215 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 216 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 217 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 218 | struct ath9k_channel *chan, |
| 219 | struct chan_centers *centers) |
| 220 | { |
| 221 | int8_t extoff; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 222 | |
| 223 | if (!IS_CHAN_HT40(chan)) { |
| 224 | centers->ctl_center = centers->ext_center = |
| 225 | centers->synth_center = chan->channel; |
| 226 | return; |
| 227 | } |
| 228 | |
| 229 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
| 230 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { |
| 231 | centers->synth_center = |
| 232 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; |
| 233 | extoff = 1; |
| 234 | } else { |
| 235 | centers->synth_center = |
| 236 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; |
| 237 | extoff = -1; |
| 238 | } |
| 239 | |
| 240 | centers->ctl_center = |
| 241 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); |
Luis R. Rodriguez | 6420014 | 2009-09-13 22:05:04 -0700 | [diff] [blame] | 242 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 243 | centers->ext_center = |
Luis R. Rodriguez | 6420014 | 2009-09-13 22:05:04 -0700 | [diff] [blame] | 244 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 245 | } |
| 246 | |
| 247 | /******************/ |
| 248 | /* Chip Revisions */ |
| 249 | /******************/ |
| 250 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 251 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 252 | { |
| 253 | u32 val; |
| 254 | |
| 255 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
| 256 | |
| 257 | if (val == 0xFF) { |
| 258 | val = REG_READ(ah, AR_SREV); |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 259 | ah->hw_version.macVersion = |
| 260 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; |
| 261 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 262 | ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 263 | } else { |
| 264 | if (!AR_SREV_9100(ah)) |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 265 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 266 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 267 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 268 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 269 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 270 | ah->is_pciexpress = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 271 | } |
| 272 | } |
| 273 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 274 | /************************************/ |
| 275 | /* HW Attach, Detach, Init Routines */ |
| 276 | /************************************/ |
| 277 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 278 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 279 | { |
Felix Fietkau | 040b74f | 2010-12-12 00:51:07 +0100 | [diff] [blame] | 280 | if (!AR_SREV_5416(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 281 | return; |
| 282 | |
| 283 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
| 284 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
| 285 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); |
| 286 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); |
| 287 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); |
| 288 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); |
| 289 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 290 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 291 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); |
| 292 | |
| 293 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
| 294 | } |
| 295 | |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 296 | /* This should work for all families including legacy */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 297 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 298 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 299 | struct ath_common *common = ath9k_hw_common(ah); |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 300 | u32 regAddr[2] = { AR_STA_ID0 }; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 301 | u32 regHold[2]; |
Joe Perches | 07b2fa5 | 2010-11-20 18:38:53 -0800 | [diff] [blame] | 302 | static const u32 patternData[4] = { |
| 303 | 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 |
| 304 | }; |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 305 | int i, j, loop_max; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 306 | |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 307 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
| 308 | loop_max = 2; |
| 309 | regAddr[1] = AR_PHY_BASE + (8 << 2); |
| 310 | } else |
| 311 | loop_max = 1; |
| 312 | |
| 313 | for (i = 0; i < loop_max; i++) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 314 | u32 addr = regAddr[i]; |
| 315 | u32 wrData, rdData; |
| 316 | |
| 317 | regHold[i] = REG_READ(ah, addr); |
| 318 | for (j = 0; j < 0x100; j++) { |
| 319 | wrData = (j << 16) | j; |
| 320 | REG_WRITE(ah, addr, wrData); |
| 321 | rdData = REG_READ(ah, addr); |
| 322 | if (rdData != wrData) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 323 | ath_err(common, |
| 324 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", |
| 325 | addr, wrData, rdData); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 326 | return false; |
| 327 | } |
| 328 | } |
| 329 | for (j = 0; j < 4; j++) { |
| 330 | wrData = patternData[j]; |
| 331 | REG_WRITE(ah, addr, wrData); |
| 332 | rdData = REG_READ(ah, addr); |
| 333 | if (wrData != rdData) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 334 | ath_err(common, |
| 335 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", |
| 336 | addr, wrData, rdData); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 337 | return false; |
| 338 | } |
| 339 | } |
| 340 | REG_WRITE(ah, regAddr[i], regHold[i]); |
| 341 | } |
| 342 | udelay(100); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 343 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 344 | return true; |
| 345 | } |
| 346 | |
Luis R. Rodriguez | b8b0f37 | 2009-08-03 12:24:43 -0700 | [diff] [blame] | 347 | static void ath9k_hw_init_config(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 348 | { |
| 349 | int i; |
| 350 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 351 | ah->config.dma_beacon_response_time = 2; |
| 352 | ah->config.sw_beacon_response_time = 10; |
| 353 | ah->config.additional_swba_backoff = 0; |
| 354 | ah->config.ack_6mb = 0x0; |
| 355 | ah->config.cwm_ignore_extcca = 0; |
| 356 | ah->config.pcie_powersave_enable = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 357 | ah->config.pcie_clock_req = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 358 | ah->config.pcie_waen = 0; |
| 359 | ah->config.analog_shiftreg = 1; |
Luis R. Rodriguez | 03c7251 | 2010-06-12 00:33:46 -0400 | [diff] [blame] | 360 | ah->config.enable_ani = true; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 361 | |
| 362 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 363 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
| 364 | ah->config.spurchans[i][1] = AR_NO_SPUR; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 365 | } |
| 366 | |
Luis R. Rodriguez | 5ffaf8a | 2010-02-02 11:58:33 -0500 | [diff] [blame] | 367 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
| 368 | ah->config.ht_enable = 1; |
| 369 | else |
| 370 | ah->config.ht_enable = 0; |
| 371 | |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 372 | ah->config.rx_intr_mitigation = true; |
Luis R. Rodriguez | 6a0ec30 | 2010-06-21 18:38:49 -0400 | [diff] [blame] | 373 | ah->config.pcieSerDesWrite = true; |
Luis R. Rodriguez | 6158425 | 2009-03-12 18:18:49 -0400 | [diff] [blame] | 374 | |
| 375 | /* |
| 376 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) |
| 377 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). |
| 378 | * This means we use it for all AR5416 devices, and the few |
| 379 | * minor PCI AR9280 devices out there. |
| 380 | * |
| 381 | * Serialization is required because these devices do not handle |
| 382 | * well the case of two concurrent reads/writes due to the latency |
| 383 | * involved. During one read/write another read/write can be issued |
| 384 | * on another CPU while the previous read/write may still be working |
| 385 | * on our hardware, if we hit this case the hardware poops in a loop. |
| 386 | * We prevent this by serializing reads and writes. |
| 387 | * |
| 388 | * This issue is not present on PCI-Express devices or pre-AR5416 |
| 389 | * devices (legacy, 802.11abg). |
| 390 | */ |
| 391 | if (num_possible_cpus() > 1) |
David S. Miller | 2d6a5e9 | 2009-03-17 15:01:30 -0700 | [diff] [blame] | 392 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 393 | } |
| 394 | |
Luis R. Rodriguez | 50aca25 | 2009-08-03 12:24:42 -0700 | [diff] [blame] | 395 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 396 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 397 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 398 | |
| 399 | regulatory->country_code = CTRY_DEFAULT; |
| 400 | regulatory->power_limit = MAX_RATE_POWER; |
| 401 | regulatory->tp_scale = ATH9K_TP_SCALE_MAX; |
| 402 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 403 | ah->hw_version.magic = AR5416_MAGIC; |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 404 | ah->hw_version.subvendorid = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 405 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 406 | ah->atim_window = 0; |
Felix Fietkau | 16f2411 | 2010-06-12 17:22:32 +0200 | [diff] [blame] | 407 | ah->sta_id1_defaults = |
| 408 | AR_STA_ID1_CRPT_MIC_ENABLE | |
| 409 | AR_STA_ID1_MCAST_KSRCH; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 410 | ah->enable_32kHz_clock = DONT_USE_32KHZ; |
Felix Fietkau | 4357c6b | 2010-12-13 08:40:50 +0100 | [diff] [blame] | 411 | ah->slottime = 20; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 412 | ah->globaltxtimeout = (u32) -1; |
Gabor Juhos | cbdec97 | 2009-07-24 17:27:22 +0200 | [diff] [blame] | 413 | ah->power_mode = ATH9K_PM_UNDEFINED; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 414 | } |
| 415 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 416 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 417 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 418 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 419 | u32 sum; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 420 | int i; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 421 | u16 eeval; |
Joe Perches | 07b2fa5 | 2010-11-20 18:38:53 -0800 | [diff] [blame] | 422 | static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 423 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 424 | sum = 0; |
| 425 | for (i = 0; i < 3; i++) { |
Luis R. Rodriguez | 4910167 | 2010-04-15 17:39:13 -0400 | [diff] [blame] | 426 | eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 427 | sum += eeval; |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 428 | common->macaddr[2 * i] = eeval >> 8; |
| 429 | common->macaddr[2 * i + 1] = eeval & 0xff; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 430 | } |
Sujith | d8baa93 | 2009-03-30 15:28:25 +0530 | [diff] [blame] | 431 | if (sum == 0 || sum == 0xffff * 3) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 432 | return -EADDRNOTAVAIL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 433 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 434 | return 0; |
| 435 | } |
| 436 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 437 | static int ath9k_hw_post_init(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 438 | { |
Sujith Manoharan | 6cae913d | 2011-01-04 13:16:37 +0530 | [diff] [blame] | 439 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 440 | int ecode; |
| 441 | |
Sujith Manoharan | 6cae913d | 2011-01-04 13:16:37 +0530 | [diff] [blame] | 442 | if (common->bus_ops->ath_bus_type != ATH_USB) { |
Sujith | 527d485 | 2010-03-17 14:25:16 +0530 | [diff] [blame] | 443 | if (!ath9k_hw_chip_test(ah)) |
| 444 | return -ENODEV; |
| 445 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 446 | |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 447 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
| 448 | ecode = ar9002_hw_rf_claim(ah); |
| 449 | if (ecode != 0) |
| 450 | return ecode; |
| 451 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 452 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 453 | ecode = ath9k_hw_eeprom_init(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 454 | if (ecode != 0) |
| 455 | return ecode; |
Sujith | 7d01b22 | 2009-03-13 08:55:55 +0530 | [diff] [blame] | 456 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 457 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, |
| 458 | "Eeprom VER: %d, REV: %d\n", |
| 459 | ah->eep_ops->get_eeprom_ver(ah), |
| 460 | ah->eep_ops->get_eeprom_rev(ah)); |
Sujith | 7d01b22 | 2009-03-13 08:55:55 +0530 | [diff] [blame] | 461 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 462 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
| 463 | if (ecode) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 464 | ath_err(ath9k_hw_common(ah), |
| 465 | "Failed allocating banks for external radio\n"); |
Rajkumar Manoharan | 48a7c3d | 2010-11-08 20:40:53 +0530 | [diff] [blame] | 466 | ath9k_hw_rf_free_ext_banks(ah); |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 467 | return ecode; |
Luis R. Rodriguez | 574d6b1 | 2009-10-19 02:33:37 -0400 | [diff] [blame] | 468 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 469 | |
| 470 | if (!AR_SREV_9100(ah)) { |
| 471 | ath9k_hw_ani_setup(ah); |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 472 | ath9k_hw_ani_init(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 473 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 474 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 475 | return 0; |
| 476 | } |
| 477 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 478 | static void ath9k_hw_attach_ops(struct ath_hw *ah) |
Luis R. Rodriguez | ee2bb46 | 2009-08-03 12:24:39 -0700 | [diff] [blame] | 479 | { |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 480 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 481 | ar9003_hw_attach_ops(ah); |
| 482 | else |
| 483 | ar9002_hw_attach_ops(ah); |
Luis R. Rodriguez | ee2bb46 | 2009-08-03 12:24:39 -0700 | [diff] [blame] | 484 | } |
| 485 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 486 | /* Called for all hardware families */ |
| 487 | static int __ath9k_hw_init(struct ath_hw *ah) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 488 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 489 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 490 | int r = 0; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 491 | |
Luis R. Rodriguez | bab1f62 | 2010-04-15 17:38:20 -0400 | [diff] [blame] | 492 | if (ah->hw_version.devid == AR5416_AR9100_DEVID) |
| 493 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 494 | |
| 495 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 496 | ath_err(common, "Couldn't reset chip\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 497 | return -EIO; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 498 | } |
| 499 | |
Luis R. Rodriguez | bab1f62 | 2010-04-15 17:38:20 -0400 | [diff] [blame] | 500 | ath9k_hw_init_defaults(ah); |
| 501 | ath9k_hw_init_config(ah); |
| 502 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 503 | ath9k_hw_attach_ops(ah); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 504 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 505 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 506 | ath_err(common, "Couldn't wakeup chip\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 507 | return -EIO; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 508 | } |
| 509 | |
| 510 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { |
| 511 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || |
John W. Linville | 4c85ab1 | 2010-07-28 10:06:35 -0400 | [diff] [blame] | 512 | ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && |
| 513 | !ah->is_pciexpress)) { |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 514 | ah->config.serialize_regmode = |
| 515 | SER_REG_MODE_ON; |
| 516 | } else { |
| 517 | ah->config.serialize_regmode = |
| 518 | SER_REG_MODE_OFF; |
| 519 | } |
| 520 | } |
| 521 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 522 | ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 523 | ah->config.serialize_regmode); |
| 524 | |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 525 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
| 526 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; |
| 527 | else |
| 528 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; |
| 529 | |
Felix Fietkau | 6da5a72 | 2010-12-12 00:51:12 +0100 | [diff] [blame] | 530 | switch (ah->hw_version.macVersion) { |
| 531 | case AR_SREV_VERSION_5416_PCI: |
| 532 | case AR_SREV_VERSION_5416_PCIE: |
| 533 | case AR_SREV_VERSION_9160: |
| 534 | case AR_SREV_VERSION_9100: |
| 535 | case AR_SREV_VERSION_9280: |
| 536 | case AR_SREV_VERSION_9285: |
| 537 | case AR_SREV_VERSION_9287: |
| 538 | case AR_SREV_VERSION_9271: |
| 539 | case AR_SREV_VERSION_9300: |
| 540 | case AR_SREV_VERSION_9485: |
| 541 | break; |
| 542 | default: |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 543 | ath_err(common, |
| 544 | "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", |
| 545 | ah->hw_version.macVersion, ah->hw_version.macRev); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 546 | return -EOPNOTSUPP; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 547 | } |
| 548 | |
Luis R. Rodriguez | 0df13da | 2010-04-15 17:38:59 -0400 | [diff] [blame] | 549 | if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 550 | ah->is_pciexpress = false; |
| 551 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 552 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 553 | ath9k_hw_init_cal_settings(ah); |
| 554 | |
| 555 | ah->ani_function = ATH9K_ANI_ALL; |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 556 | if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 557 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 558 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 559 | ah->ani_function &= ~ATH9K_ANI_MRC_CCK; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 560 | |
| 561 | ath9k_hw_init_mode_regs(ah); |
| 562 | |
Luis R. Rodriguez | 5efa3a6 | 2010-05-07 18:23:22 -0400 | [diff] [blame] | 563 | /* |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 564 | * Read back AR_WA into a permanent copy and set bits 14 and 17. |
| 565 | * We need to do this to avoid RMW of this register. We cannot |
| 566 | * read the reg when chip is asleep. |
| 567 | */ |
| 568 | ah->WARegVal = REG_READ(ah, AR_WA); |
| 569 | ah->WARegVal |= (AR_WA_D3_L1_DISABLE | |
| 570 | AR_WA_ASPM_TIMER_BASED_DISABLE); |
| 571 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 572 | if (ah->is_pciexpress) |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 573 | ath9k_hw_configpcipowersave(ah, 0, 0); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 574 | else |
| 575 | ath9k_hw_disablepcie(ah); |
| 576 | |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 577 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 578 | ar9002_hw_cck_chan14_spread(ah); |
Sujith | 193cd45 | 2009-09-18 15:04:07 +0530 | [diff] [blame] | 579 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 580 | r = ath9k_hw_post_init(ah); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 581 | if (r) |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 582 | return r; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 583 | |
| 584 | ath9k_hw_init_mode_gain_regs(ah); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 585 | r = ath9k_hw_fill_cap_info(ah); |
| 586 | if (r) |
| 587 | return r; |
| 588 | |
Luis R. Rodriguez | 4f3acf8 | 2009-08-03 12:24:36 -0700 | [diff] [blame] | 589 | r = ath9k_hw_init_macaddr(ah); |
| 590 | if (r) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 591 | ath_err(common, "Failed to initialize MAC address\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 592 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 593 | } |
| 594 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 595 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 596 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 597 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 598 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 599 | |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 600 | ah->bb_watchdog_timeout_ms = 25; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 601 | |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 602 | common->state = ATH_HW_INITIALIZED; |
| 603 | |
Luis R. Rodriguez | 4f3acf8 | 2009-08-03 12:24:36 -0700 | [diff] [blame] | 604 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 605 | } |
| 606 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 607 | int ath9k_hw_init(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 608 | { |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 609 | int ret; |
| 610 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 611 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 612 | /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ |
| 613 | switch (ah->hw_version.devid) { |
| 614 | case AR5416_DEVID_PCI: |
| 615 | case AR5416_DEVID_PCIE: |
| 616 | case AR5416_AR9100_DEVID: |
| 617 | case AR9160_DEVID_PCI: |
| 618 | case AR9280_DEVID_PCI: |
| 619 | case AR9280_DEVID_PCIE: |
| 620 | case AR9285_DEVID_PCIE: |
Senthil Balasubramanian | db3cc53 | 2010-04-15 17:38:18 -0400 | [diff] [blame] | 621 | case AR9287_DEVID_PCI: |
| 622 | case AR9287_DEVID_PCIE: |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 623 | case AR2427_DEVID_PCIE: |
Senthil Balasubramanian | db3cc53 | 2010-04-15 17:38:18 -0400 | [diff] [blame] | 624 | case AR9300_DEVID_PCIE: |
Vasanthakumar Thiagarajan | 3050c91 | 2010-12-06 04:27:36 -0800 | [diff] [blame] | 625 | case AR9300_DEVID_AR9485_PCIE: |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 626 | break; |
| 627 | default: |
| 628 | if (common->bus_ops->ath_bus_type == ATH_USB) |
| 629 | break; |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 630 | ath_err(common, "Hardware device ID 0x%04x not supported\n", |
| 631 | ah->hw_version.devid); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 632 | return -EOPNOTSUPP; |
| 633 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 634 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 635 | ret = __ath9k_hw_init(ah); |
| 636 | if (ret) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 637 | ath_err(common, |
| 638 | "Unable to initialize hardware; initialization status: %d\n", |
| 639 | ret); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 640 | return ret; |
| 641 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 642 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 643 | return 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 644 | } |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 645 | EXPORT_SYMBOL(ath9k_hw_init); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 646 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 647 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 648 | { |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 649 | ENABLE_REGWRITE_BUFFER(ah); |
| 650 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 651 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
| 652 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); |
| 653 | |
| 654 | REG_WRITE(ah, AR_QOS_NO_ACK, |
| 655 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | |
| 656 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | |
| 657 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); |
| 658 | |
| 659 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); |
| 660 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); |
| 661 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); |
| 662 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); |
| 663 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 664 | |
| 665 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 666 | } |
| 667 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 668 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 669 | struct ath9k_channel *chan) |
| 670 | { |
Vasanthakumar Thiagarajan | d09b17f | 2010-12-06 04:27:44 -0800 | [diff] [blame] | 671 | u32 pll; |
| 672 | |
| 673 | if (AR_SREV_9485(ah)) |
| 674 | REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666); |
| 675 | |
| 676 | pll = ath9k_hw_compute_pll_control(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 677 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 678 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 679 | |
Luis R. Rodriguez | c75724d | 2009-10-19 02:33:34 -0400 | [diff] [blame] | 680 | /* Switch the core clock for ar9271 to 117Mhz */ |
| 681 | if (AR_SREV_9271(ah)) { |
Sujith | 25e2ab1 | 2010-03-17 14:25:22 +0530 | [diff] [blame] | 682 | udelay(500); |
| 683 | REG_WRITE(ah, 0x50040, 0x304); |
Luis R. Rodriguez | c75724d | 2009-10-19 02:33:34 -0400 | [diff] [blame] | 684 | } |
| 685 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 686 | udelay(RTC_PLL_SETTLE_DELAY); |
| 687 | |
| 688 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); |
| 689 | } |
| 690 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 691 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 692 | enum nl80211_iftype opmode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 693 | { |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 694 | u32 imr_reg = AR_IMR_TXERR | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 695 | AR_IMR_TXURN | |
| 696 | AR_IMR_RXERR | |
| 697 | AR_IMR_RXORN | |
| 698 | AR_IMR_BCNMISC; |
| 699 | |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 700 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 701 | imr_reg |= AR_IMR_RXOK_HP; |
| 702 | if (ah->config.rx_intr_mitigation) |
| 703 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; |
| 704 | else |
| 705 | imr_reg |= AR_IMR_RXOK_LP; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 706 | |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 707 | } else { |
| 708 | if (ah->config.rx_intr_mitigation) |
| 709 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; |
| 710 | else |
| 711 | imr_reg |= AR_IMR_RXOK; |
| 712 | } |
| 713 | |
| 714 | if (ah->config.tx_intr_mitigation) |
| 715 | imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; |
| 716 | else |
| 717 | imr_reg |= AR_IMR_TXOK; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 718 | |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 719 | if (opmode == NL80211_IFTYPE_AP) |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 720 | imr_reg |= AR_IMR_MIB; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 721 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 722 | ENABLE_REGWRITE_BUFFER(ah); |
| 723 | |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 724 | REG_WRITE(ah, AR_IMR, imr_reg); |
Pavel Roskin | 74bad5c | 2010-02-23 18:15:27 -0500 | [diff] [blame] | 725 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
| 726 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 727 | |
| 728 | if (!AR_SREV_9100(ah)) { |
| 729 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); |
| 730 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); |
| 731 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); |
| 732 | } |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 733 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 734 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 735 | |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 736 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 737 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); |
| 738 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); |
| 739 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); |
| 740 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); |
| 741 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 742 | } |
| 743 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 744 | static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 745 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 746 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 747 | val = min(val, (u32) 0xFFFF); |
| 748 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 749 | } |
| 750 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 751 | static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 752 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 753 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 754 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); |
| 755 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); |
| 756 | } |
| 757 | |
| 758 | static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) |
| 759 | { |
| 760 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 761 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); |
| 762 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 763 | } |
| 764 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 765 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 766 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 767 | if (tu > 0xFFFF) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 768 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, |
| 769 | "bad global tx timeout %u\n", tu); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 770 | ah->globaltxtimeout = (u32) -1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 771 | return false; |
| 772 | } else { |
| 773 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 774 | ah->globaltxtimeout = tu; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 775 | return true; |
| 776 | } |
| 777 | } |
| 778 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 779 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 780 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 781 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
| 782 | int acktimeout; |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 783 | int slottime; |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 784 | int sifstime; |
| 785 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 786 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
| 787 | ah->misc_mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 788 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 789 | if (ah->misc_mode != 0) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 790 | REG_WRITE(ah, AR_PCU_MISC, |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 791 | REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 792 | |
| 793 | if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) |
| 794 | sifstime = 16; |
| 795 | else |
| 796 | sifstime = 10; |
| 797 | |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 798 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
| 799 | slottime = ah->slottime + 3 * ah->coverage_class; |
| 800 | acktimeout = slottime + sifstime; |
Felix Fietkau | 42c4568 | 2010-02-11 18:07:19 +0100 | [diff] [blame] | 801 | |
| 802 | /* |
| 803 | * Workaround for early ACK timeouts, add an offset to match the |
| 804 | * initval's 64us ack timeout value. |
| 805 | * This was initially only meant to work around an issue with delayed |
| 806 | * BA frames in some implementations, but it has been found to fix ACK |
| 807 | * timeout issues in other cases as well. |
| 808 | */ |
| 809 | if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) |
| 810 | acktimeout += 64 - sifstime - ah->slottime; |
| 811 | |
Felix Fietkau | caabf2b | 2010-12-13 08:40:51 +0100 | [diff] [blame] | 812 | ath9k_hw_setslottime(ah, ah->slottime); |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 813 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
| 814 | ath9k_hw_set_cts_timeout(ah, acktimeout); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 815 | if (ah->globaltxtimeout != (u32) -1) |
| 816 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 817 | } |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 818 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 819 | |
Sujith | 285f2dd | 2010-01-08 10:36:07 +0530 | [diff] [blame] | 820 | void ath9k_hw_deinit(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 821 | { |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 822 | struct ath_common *common = ath9k_hw_common(ah); |
| 823 | |
Sujith | 736b3a2 | 2010-03-17 14:25:24 +0530 | [diff] [blame] | 824 | if (common->state < ATH_HW_INITIALIZED) |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 825 | goto free_hw; |
| 826 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 827 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 828 | |
| 829 | free_hw: |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 830 | ath9k_hw_rf_free_ext_banks(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 831 | } |
Sujith | 285f2dd | 2010-01-08 10:36:07 +0530 | [diff] [blame] | 832 | EXPORT_SYMBOL(ath9k_hw_deinit); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 833 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 834 | /*******/ |
| 835 | /* INI */ |
| 836 | /*******/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 837 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 838 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
Bob Copeland | 3a702e4 | 2009-03-30 22:30:29 -0400 | [diff] [blame] | 839 | { |
| 840 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); |
| 841 | |
| 842 | if (IS_CHAN_B(chan)) |
| 843 | ctl |= CTL_11B; |
| 844 | else if (IS_CHAN_G(chan)) |
| 845 | ctl |= CTL_11G; |
| 846 | else |
| 847 | ctl |= CTL_11A; |
| 848 | |
| 849 | return ctl; |
| 850 | } |
| 851 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 852 | /****************************************/ |
| 853 | /* Reset and Channel Switching Routines */ |
| 854 | /****************************************/ |
| 855 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 856 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 857 | { |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 858 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 859 | u32 regval; |
| 860 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 861 | ENABLE_REGWRITE_BUFFER(ah); |
| 862 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 863 | /* |
| 864 | * set AHB_MODE not to do cacheline prefetches |
| 865 | */ |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 866 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
| 867 | regval = REG_READ(ah, AR_AHB_MODE); |
| 868 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); |
| 869 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 870 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 871 | /* |
| 872 | * let mac dma reads be in 128 byte chunks |
| 873 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 874 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; |
| 875 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); |
| 876 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 877 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 878 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 879 | /* |
| 880 | * Restore TX Trigger Level to its pre-reset value. |
| 881 | * The initial value depends on whether aggregation is enabled, and is |
| 882 | * adjusted whenever underruns are detected. |
| 883 | */ |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 884 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 885 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 886 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 887 | ENABLE_REGWRITE_BUFFER(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 888 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 889 | /* |
| 890 | * let mac dma writes be in 128 byte chunks |
| 891 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 892 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; |
| 893 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); |
| 894 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 895 | /* |
| 896 | * Setup receive FIFO threshold to hold off TX activities |
| 897 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 898 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
| 899 | |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 900 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 901 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); |
| 902 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); |
| 903 | |
| 904 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - |
| 905 | ah->caps.rx_status_len); |
| 906 | } |
| 907 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 908 | /* |
| 909 | * reduce the number of usable entries in PCU TXBUF to avoid |
| 910 | * wrap around issues. |
| 911 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 912 | if (AR_SREV_9285(ah)) { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 913 | /* For AR9285 the number of Fifos are reduced to half. |
| 914 | * So set the usable tx buf size also to half to |
| 915 | * avoid data/delimiter underruns |
| 916 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 917 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
| 918 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 919 | } else if (!AR_SREV_9271(ah)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 920 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
| 921 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); |
| 922 | } |
Vasanthakumar Thiagarajan | 744d402 | 2010-04-15 17:39:27 -0400 | [diff] [blame] | 923 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 924 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 925 | |
Vasanthakumar Thiagarajan | 744d402 | 2010-04-15 17:39:27 -0400 | [diff] [blame] | 926 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 927 | ath9k_hw_reset_txstatus_ring(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 928 | } |
| 929 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 930 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 931 | { |
| 932 | u32 val; |
| 933 | |
| 934 | val = REG_READ(ah, AR_STA_ID1); |
| 935 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); |
| 936 | switch (opmode) { |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 937 | case NL80211_IFTYPE_AP: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 938 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
| 939 | | AR_STA_ID1_KSRCH_MODE); |
| 940 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
| 941 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 942 | case NL80211_IFTYPE_ADHOC: |
Pat Erley | 9cb5412 | 2009-03-20 22:59:59 -0400 | [diff] [blame] | 943 | case NL80211_IFTYPE_MESH_POINT: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 944 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
| 945 | | AR_STA_ID1_KSRCH_MODE); |
| 946 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
| 947 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 948 | case NL80211_IFTYPE_STATION: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 949 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); |
| 950 | break; |
Rajkumar Manoharan | 5f841b4 | 2010-10-27 18:31:15 +0530 | [diff] [blame] | 951 | default: |
| 952 | if (ah->is_monitoring) |
| 953 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); |
| 954 | break; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 955 | } |
| 956 | } |
| 957 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 958 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
| 959 | u32 *coef_mantissa, u32 *coef_exponent) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 960 | { |
| 961 | u32 coef_exp, coef_man; |
| 962 | |
| 963 | for (coef_exp = 31; coef_exp > 0; coef_exp--) |
| 964 | if ((coef_scaled >> coef_exp) & 0x1) |
| 965 | break; |
| 966 | |
| 967 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); |
| 968 | |
| 969 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); |
| 970 | |
| 971 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); |
| 972 | *coef_exponent = coef_exp - 16; |
| 973 | } |
| 974 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 975 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 976 | { |
| 977 | u32 rst_flags; |
| 978 | u32 tmpReg; |
| 979 | |
Sujith | 7076849 | 2009-02-16 13:23:12 +0530 | [diff] [blame] | 980 | if (AR_SREV_9100(ah)) { |
| 981 | u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); |
| 982 | val &= ~AR_RTC_DERIVED_CLK_PERIOD; |
| 983 | val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); |
| 984 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); |
| 985 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); |
| 986 | } |
| 987 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 988 | ENABLE_REGWRITE_BUFFER(ah); |
| 989 | |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 990 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 991 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
| 992 | udelay(10); |
| 993 | } |
| 994 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 995 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
| 996 | AR_RTC_FORCE_WAKE_ON_INT); |
| 997 | |
| 998 | if (AR_SREV_9100(ah)) { |
| 999 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | |
| 1000 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; |
| 1001 | } else { |
| 1002 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); |
| 1003 | if (tmpReg & |
| 1004 | (AR_INTR_SYNC_LOCAL_TIMEOUT | |
| 1005 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1006 | u32 val; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1007 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1008 | |
| 1009 | val = AR_RC_HOSTIF; |
| 1010 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1011 | val |= AR_RC_AHB; |
| 1012 | REG_WRITE(ah, AR_RC, val); |
| 1013 | |
| 1014 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1015 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1016 | |
| 1017 | rst_flags = AR_RTC_RC_MAC_WARM; |
| 1018 | if (type == ATH9K_RESET_COLD) |
| 1019 | rst_flags |= AR_RTC_RC_MAC_COLD; |
| 1020 | } |
| 1021 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1022 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1023 | |
| 1024 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1025 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1026 | udelay(50); |
| 1027 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1028 | REG_WRITE(ah, AR_RTC_RC, 0); |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 1029 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1030 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1031 | "RTC stuck in MAC reset\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1032 | return false; |
| 1033 | } |
| 1034 | |
| 1035 | if (!AR_SREV_9100(ah)) |
| 1036 | REG_WRITE(ah, AR_RC, 0); |
| 1037 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1038 | if (AR_SREV_9100(ah)) |
| 1039 | udelay(50); |
| 1040 | |
| 1041 | return true; |
| 1042 | } |
| 1043 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1044 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1045 | { |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1046 | ENABLE_REGWRITE_BUFFER(ah); |
| 1047 | |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1048 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1049 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
| 1050 | udelay(10); |
| 1051 | } |
| 1052 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1053 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
| 1054 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1055 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1056 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1057 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
| 1058 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1059 | REG_WRITE(ah, AR_RTC_RESET, 0); |
Luis R. Rodriguez | ee03111 | 2010-06-21 18:38:51 -0400 | [diff] [blame] | 1060 | udelay(2); |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1061 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1062 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1063 | |
Senthil Balasubramanian | 84e2169 | 2010-04-15 17:38:30 -0400 | [diff] [blame] | 1064 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1065 | udelay(2); |
| 1066 | |
| 1067 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1068 | REG_WRITE(ah, AR_RC, 0); |
| 1069 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1070 | REG_WRITE(ah, AR_RTC_RESET, 1); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1071 | |
| 1072 | if (!ath9k_hw_wait(ah, |
| 1073 | AR_RTC_STATUS, |
| 1074 | AR_RTC_STATUS_M, |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 1075 | AR_RTC_STATUS_ON, |
| 1076 | AH_WAIT_TIMEOUT)) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1077 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1078 | "RTC not waking up\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1079 | return false; |
| 1080 | } |
| 1081 | |
| 1082 | ath9k_hw_read_revisions(ah); |
| 1083 | |
| 1084 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); |
| 1085 | } |
| 1086 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1087 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1088 | { |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1089 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1090 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
| 1091 | udelay(10); |
| 1092 | } |
| 1093 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1094 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 1095 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); |
| 1096 | |
| 1097 | switch (type) { |
| 1098 | case ATH9K_RESET_POWER_ON: |
| 1099 | return ath9k_hw_set_reset_power_on(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1100 | case ATH9K_RESET_WARM: |
| 1101 | case ATH9K_RESET_COLD: |
| 1102 | return ath9k_hw_set_reset(ah, type); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1103 | default: |
| 1104 | return false; |
| 1105 | } |
| 1106 | } |
| 1107 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1108 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1109 | struct ath9k_channel *chan) |
| 1110 | { |
Vivek Natarajan | 42abfbe | 2009-09-17 09:27:59 +0530 | [diff] [blame] | 1111 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 1112 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) |
| 1113 | return false; |
| 1114 | } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1115 | return false; |
| 1116 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1117 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1118 | return false; |
| 1119 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1120 | ah->chip_fullsleep = false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1121 | ath9k_hw_init_pll(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1122 | ath9k_hw_set_rfmode(ah, chan); |
| 1123 | |
| 1124 | return true; |
| 1125 | } |
| 1126 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1127 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1128 | struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1129 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1130 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1131 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 1132 | struct ieee80211_channel *channel = chan->chan; |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1133 | u32 qnum; |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1134 | int r; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1135 | |
| 1136 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { |
| 1137 | if (ath9k_hw_numtxpending(ah, qnum)) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1138 | ath_dbg(common, ATH_DBG_QUEUE, |
| 1139 | "Transmit frames pending on queue %d\n", qnum); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1140 | return false; |
| 1141 | } |
| 1142 | } |
| 1143 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1144 | if (!ath9k_hw_rfbus_req(ah)) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1145 | ath_err(common, "Could not kill baseband RX\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1146 | return false; |
| 1147 | } |
| 1148 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1149 | ath9k_hw_set_channel_regs(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1150 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1151 | r = ath9k_hw_rf_set_freq(ah, chan); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1152 | if (r) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1153 | ath_err(common, "Failed to set channel\n"); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1154 | return false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1155 | } |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 1156 | ath9k_hw_set_clockrate(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1157 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 1158 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1159 | ath9k_regd_get_ctl(regulatory, chan), |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1160 | channel->max_antenna_gain * 2, |
| 1161 | channel->max_power * 2, |
| 1162 | min((u32) MAX_RATE_POWER, |
Felix Fietkau | de40f31 | 2010-10-20 03:08:53 +0200 | [diff] [blame] | 1163 | (u32) regulatory->power_limit), false); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1164 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1165 | ath9k_hw_rfbus_done(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1166 | |
| 1167 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
| 1168 | ath9k_hw_set_delta_slope(ah, chan); |
| 1169 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1170 | ath9k_hw_spur_mitigate_freq(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1171 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1172 | return true; |
| 1173 | } |
| 1174 | |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 1175 | bool ath9k_hw_check_alive(struct ath_hw *ah) |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1176 | { |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 1177 | int count = 50; |
| 1178 | u32 reg; |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1179 | |
Felix Fietkau | e17f83e | 2010-09-22 12:34:53 +0200 | [diff] [blame] | 1180 | if (AR_SREV_9285_12_OR_LATER(ah)) |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 1181 | return true; |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1182 | |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 1183 | do { |
| 1184 | reg = REG_READ(ah, AR_OBS_BUS_1); |
| 1185 | |
| 1186 | if ((reg & 0x7E7FFFEF) == 0x00702400) |
| 1187 | continue; |
| 1188 | |
| 1189 | switch (reg & 0x7E000B00) { |
| 1190 | case 0x1E000000: |
| 1191 | case 0x52000B00: |
| 1192 | case 0x18000B00: |
| 1193 | continue; |
| 1194 | default: |
| 1195 | return true; |
| 1196 | } |
| 1197 | } while (count-- > 0); |
| 1198 | |
| 1199 | return false; |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1200 | } |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 1201 | EXPORT_SYMBOL(ath9k_hw_check_alive); |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1202 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1203 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
Felix Fietkau | 20bd2a0 | 2010-07-31 00:12:00 +0200 | [diff] [blame] | 1204 | struct ath9k_hw_cal_data *caldata, bool bChannelChange) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1205 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 1206 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1207 | u32 saveLedState; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1208 | struct ath9k_channel *curchan = ah->curchan; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1209 | u32 saveDefAntenna; |
| 1210 | u32 macStaId1; |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1211 | u64 tsf = 0; |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1212 | int i, r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1213 | |
Luis R. Rodriguez | 43c2761 | 2009-09-13 21:07:07 -0700 | [diff] [blame] | 1214 | ah->txchainmask = common->tx_chainmask; |
| 1215 | ah->rxchainmask = common->rx_chainmask; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1216 | |
Sujith Manoharan | 6d50192 | 2011-01-04 13:43:39 +0530 | [diff] [blame] | 1217 | if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) { |
Vasanthakumar Thiagarajan | 9b9cc61 | 2010-04-15 17:39:41 -0400 | [diff] [blame] | 1218 | ath9k_hw_abortpcurecv(ah); |
Felix Fietkau | 9cc2f3e | 2010-07-11 12:48:42 +0200 | [diff] [blame] | 1219 | if (!ath9k_hw_stopdmarecv(ah)) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1220 | ath_dbg(common, ATH_DBG_XMIT, |
Vasanthakumar Thiagarajan | 9b9cc61 | 2010-04-15 17:39:41 -0400 | [diff] [blame] | 1221 | "Failed to stop receive dma\n"); |
Felix Fietkau | 9cc2f3e | 2010-07-11 12:48:42 +0200 | [diff] [blame] | 1222 | bChannelChange = false; |
| 1223 | } |
Vasanthakumar Thiagarajan | 9b9cc61 | 2010-04-15 17:39:41 -0400 | [diff] [blame] | 1224 | } |
| 1225 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1226 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1227 | return -EIO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1228 | |
Felix Fietkau | d9891c7 | 2010-09-29 17:15:27 +0200 | [diff] [blame] | 1229 | if (curchan && !ah->chip_fullsleep) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1230 | ath9k_hw_getnf(ah, curchan); |
| 1231 | |
Felix Fietkau | 20bd2a0 | 2010-07-31 00:12:00 +0200 | [diff] [blame] | 1232 | ah->caldata = caldata; |
| 1233 | if (caldata && |
| 1234 | (chan->channel != caldata->channel || |
| 1235 | (chan->channelFlags & ~CHANNEL_CW_INT) != |
| 1236 | (caldata->channelFlags & ~CHANNEL_CW_INT))) { |
| 1237 | /* Operating channel changed, reset channel calibration data */ |
| 1238 | memset(caldata, 0, sizeof(*caldata)); |
| 1239 | ath9k_init_nfcal_hist_buffer(ah, chan); |
| 1240 | } |
| 1241 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1242 | if (bChannelChange && |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1243 | (ah->chip_fullsleep != true) && |
| 1244 | (ah->curchan != NULL) && |
| 1245 | (chan->channel != ah->curchan->channel) && |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1246 | ((chan->channelFlags & CHANNEL_ALL) == |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1247 | (ah->curchan->channelFlags & CHANNEL_ALL)) && |
Rajkumar Manoharan | 58d7e0f | 2010-09-08 15:57:12 +0530 | [diff] [blame] | 1248 | (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1249 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1250 | if (ath9k_hw_channel_change(ah, chan)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1251 | ath9k_hw_loadnf(ah, ah->curchan); |
Felix Fietkau | 00c8659 | 2010-07-30 21:02:09 +0200 | [diff] [blame] | 1252 | ath9k_hw_start_nfcal(ah, true); |
Rajkumar Manoharan | c2ba334 | 2010-09-03 16:00:00 +0530 | [diff] [blame] | 1253 | if (AR_SREV_9271(ah)) |
| 1254 | ar9002_hw_load_ani_reg(ah, chan); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1255 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1256 | } |
| 1257 | } |
| 1258 | |
| 1259 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); |
| 1260 | if (saveDefAntenna == 0) |
| 1261 | saveDefAntenna = 1; |
| 1262 | |
| 1263 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; |
| 1264 | |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1265 | /* For chips on which RTC reset is done, save TSF before it gets cleared */ |
Felix Fietkau | f860d52 | 2010-06-30 02:07:48 +0200 | [diff] [blame] | 1266 | if (AR_SREV_9100(ah) || |
| 1267 | (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1268 | tsf = ath9k_hw_gettsf64(ah); |
| 1269 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1270 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
| 1271 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | |
| 1272 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); |
| 1273 | |
| 1274 | ath9k_hw_mark_phy_inactive(ah); |
| 1275 | |
Vasanthakumar Thiagarajan | 45ef6a0b | 2010-12-15 07:30:53 -0800 | [diff] [blame] | 1276 | ah->paprd_table_write_done = false; |
| 1277 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 1278 | /* Only required on the first reset */ |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1279 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
| 1280 | REG_WRITE(ah, |
| 1281 | AR9271_RESET_POWER_DOWN_CONTROL, |
| 1282 | AR9271_RADIO_RF_RST); |
| 1283 | udelay(50); |
| 1284 | } |
| 1285 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1286 | if (!ath9k_hw_chip_reset(ah, chan)) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1287 | ath_err(common, "Chip reset failed\n"); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1288 | return -EINVAL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1289 | } |
| 1290 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 1291 | /* Only required on the first reset */ |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1292 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
| 1293 | ah->htc_reset_init = false; |
| 1294 | REG_WRITE(ah, |
| 1295 | AR9271_RESET_POWER_DOWN_CONTROL, |
| 1296 | AR9271_GATE_MAC_CTL); |
| 1297 | udelay(50); |
| 1298 | } |
| 1299 | |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1300 | /* Restore TSF */ |
Felix Fietkau | f860d52 | 2010-06-30 02:07:48 +0200 | [diff] [blame] | 1301 | if (tsf) |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1302 | ath9k_hw_settsf64(ah, tsf); |
| 1303 | |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 1304 | if (AR_SREV_9280_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 369391d | 2009-01-21 19:24:13 +0530 | [diff] [blame] | 1305 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1306 | |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 1307 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1308 | ar9002_hw_enable_async_fifo(ah); |
| 1309 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1310 | r = ath9k_hw_process_ini(ah, chan); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1311 | if (r) |
| 1312 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1313 | |
Felix Fietkau | f860d52 | 2010-06-30 02:07:48 +0200 | [diff] [blame] | 1314 | /* |
| 1315 | * Some AR91xx SoC devices frequently fail to accept TSF writes |
| 1316 | * right after the chip reset. When that happens, write a new |
| 1317 | * value after the initvals have been applied, with an offset |
| 1318 | * based on measured time difference |
| 1319 | */ |
| 1320 | if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { |
| 1321 | tsf += 1500; |
| 1322 | ath9k_hw_settsf64(ah, tsf); |
| 1323 | } |
| 1324 | |
Jouni Malinen | 0ced0e1 | 2009-01-08 13:32:13 +0200 | [diff] [blame] | 1325 | /* Setup MFP options for CCMP */ |
| 1326 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 1327 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt |
| 1328 | * frames when constructing CCMP AAD. */ |
| 1329 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, |
| 1330 | 0xc7ff); |
| 1331 | ah->sw_mgmt_crypto = false; |
| 1332 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 1333 | /* Disable hardware crypto for management frames */ |
| 1334 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, |
| 1335 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); |
| 1336 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
| 1337 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); |
| 1338 | ah->sw_mgmt_crypto = true; |
| 1339 | } else |
| 1340 | ah->sw_mgmt_crypto = true; |
| 1341 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1342 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
| 1343 | ath9k_hw_set_delta_slope(ah, chan); |
| 1344 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1345 | ath9k_hw_spur_mitigate_freq(ah, chan); |
Sujith | d650915 | 2009-03-13 08:56:05 +0530 | [diff] [blame] | 1346 | ah->eep_ops->set_board_values(ah, chan); |
Luis R. Rodriguez | a776582 | 2009-10-19 02:33:45 -0400 | [diff] [blame] | 1347 | |
Sujith | 6819d57 | 2010-04-16 11:53:56 +0530 | [diff] [blame] | 1348 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
| 1349 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1350 | ENABLE_REGWRITE_BUFFER(ah); |
| 1351 | |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 1352 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); |
| 1353 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1354 | | macStaId1 |
| 1355 | | AR_STA_ID1_RTS_USE_DEF |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1356 | | (ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1357 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1358 | | ah->sta_id1_defaults); |
Luis R. Rodriguez | 13b8155 | 2009-09-10 17:52:45 -0700 | [diff] [blame] | 1359 | ath_hw_setbssidmask(common); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1360 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); |
Luis R. Rodriguez | 3453ad8 | 2009-09-10 08:57:00 -0700 | [diff] [blame] | 1361 | ath9k_hw_write_associd(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1362 | REG_WRITE(ah, AR_ISR, ~0); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1363 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); |
| 1364 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1365 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1366 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1367 | r = ath9k_hw_rf_set_freq(ah, chan); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1368 | if (r) |
| 1369 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1370 | |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 1371 | ath9k_hw_set_clockrate(ah); |
| 1372 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1373 | ENABLE_REGWRITE_BUFFER(ah); |
| 1374 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1375 | for (i = 0; i < AR_NUM_DCU; i++) |
| 1376 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); |
| 1377 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1378 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1379 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1380 | ah->intr_txqs = 0; |
| 1381 | for (i = 0; i < ah->caps.total_queues; i++) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1382 | ath9k_hw_resettxqueue(ah, i); |
| 1383 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1384 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1385 | ath9k_hw_ani_cache_ini_regs(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1386 | ath9k_hw_init_qos(ah); |
| 1387 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1388 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
Felix Fietkau | 5582132 | 2010-12-17 00:57:01 +0100 | [diff] [blame] | 1389 | ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1390 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1391 | ath9k_hw_init_global_settings(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1392 | |
Luis R. Rodriguez | 6c94fdc | 2010-04-15 17:39:24 -0400 | [diff] [blame] | 1393 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 1394 | ar9002_hw_update_async_fifo(ah); |
Luis R. Rodriguez | 6c94fdc | 2010-04-15 17:39:24 -0400 | [diff] [blame] | 1395 | ar9002_hw_enable_wep_aggregation(ah); |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 1396 | } |
| 1397 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1398 | REG_WRITE(ah, AR_STA_ID1, |
| 1399 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); |
| 1400 | |
| 1401 | ath9k_hw_set_dma(ah); |
| 1402 | |
| 1403 | REG_WRITE(ah, AR_OBS, 8); |
| 1404 | |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 1405 | if (ah->config.rx_intr_mitigation) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1406 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
| 1407 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); |
| 1408 | } |
| 1409 | |
Vasanthakumar Thiagarajan | 7f62a13 | 2010-04-15 17:39:19 -0400 | [diff] [blame] | 1410 | if (ah->config.tx_intr_mitigation) { |
| 1411 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); |
| 1412 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); |
| 1413 | } |
| 1414 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1415 | ath9k_hw_init_bb(ah, chan); |
| 1416 | |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1417 | if (!ath9k_hw_init_cal(ah, chan)) |
Joe Perches | 6badaaf | 2009-06-28 09:26:32 -0700 | [diff] [blame] | 1418 | return -EIO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1419 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1420 | ENABLE_REGWRITE_BUFFER(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1421 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1422 | ath9k_hw_restore_chainmask(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1423 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
| 1424 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1425 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1426 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1427 | /* |
| 1428 | * For big endian systems turn on swapping for descriptors |
| 1429 | */ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1430 | if (AR_SREV_9100(ah)) { |
| 1431 | u32 mask; |
| 1432 | mask = REG_READ(ah, AR_CFG); |
| 1433 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1434 | ath_dbg(common, ATH_DBG_RESET, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 1435 | "CFG Byte Swap Set 0x%x\n", mask); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1436 | } else { |
| 1437 | mask = |
| 1438 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; |
| 1439 | REG_WRITE(ah, AR_CFG, mask); |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1440 | ath_dbg(common, ATH_DBG_RESET, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 1441 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1442 | } |
| 1443 | } else { |
Sujith | cbba8cd | 2010-06-02 15:53:31 +0530 | [diff] [blame] | 1444 | if (common->bus_ops->ath_bus_type == ATH_USB) { |
| 1445 | /* Configure AR9271 target WLAN */ |
| 1446 | if (AR_SREV_9271(ah)) |
| 1447 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); |
| 1448 | else |
| 1449 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); |
| 1450 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1451 | #ifdef __BIG_ENDIAN |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1452 | else |
| 1453 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1454 | #endif |
| 1455 | } |
| 1456 | |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1457 | if (ah->btcoex_hw.enabled) |
Vasanthakumar Thiagarajan | 42cc41e | 2009-08-26 21:08:45 +0530 | [diff] [blame] | 1458 | ath9k_hw_btcoex_enable(ah); |
| 1459 | |
Felix Fietkau | 00c8659 | 2010-07-30 21:02:09 +0200 | [diff] [blame] | 1460 | if (AR_SREV_9300_20_OR_LATER(ah)) |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 1461 | ar9003_hw_bb_watchdog_config(ah); |
Vasanthakumar Thiagarajan | d8903a5 | 2010-04-15 17:39:25 -0400 | [diff] [blame] | 1462 | |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1463 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1464 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1465 | EXPORT_SYMBOL(ath9k_hw_reset); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1466 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1467 | /******************************/ |
| 1468 | /* Power Management (Chipset) */ |
| 1469 | /******************************/ |
| 1470 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1471 | /* |
| 1472 | * Notify Power Mgt is disabled in self-generated frames. |
| 1473 | * If requested, force chip to sleep. |
| 1474 | */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1475 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1476 | { |
| 1477 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1478 | if (setChip) { |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1479 | /* |
| 1480 | * Clear the RTC force wake bit to allow the |
| 1481 | * mac to go to sleep. |
| 1482 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1483 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1484 | AR_RTC_FORCE_WAKE_EN); |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1485 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1486 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
| 1487 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1488 | /* Shutdown chip. Active low */ |
Sujith | 14b3af3 | 2010-03-17 14:25:18 +0530 | [diff] [blame] | 1489 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) |
Sujith | 4921be8 | 2009-09-18 15:04:27 +0530 | [diff] [blame] | 1490 | REG_CLR_BIT(ah, (AR_RTC_RESET), |
| 1491 | AR_RTC_RESET_EN); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1492 | } |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1493 | |
| 1494 | /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ |
| 1495 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 1496 | REG_WRITE(ah, AR_WA, |
| 1497 | ah->WARegVal & ~AR_WA_D3_L1_DISABLE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1498 | } |
| 1499 | |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 1500 | /* |
| 1501 | * Notify Power Management is enabled in self-generating |
| 1502 | * frames. If request, set power mode of chip to |
| 1503 | * auto/normal. Duration in units of 128us (1/8 TU). |
| 1504 | */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1505 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1506 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1507 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1508 | if (setChip) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1509 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1510 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1511 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 1512 | /* Set WakeOnInterrupt bit; clear ForceWake bit */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1513 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 1514 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1515 | } else { |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 1516 | /* |
| 1517 | * Clear the RTC force wake bit to allow the |
| 1518 | * mac to go to sleep. |
| 1519 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1520 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1521 | AR_RTC_FORCE_WAKE_EN); |
| 1522 | } |
| 1523 | } |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1524 | |
| 1525 | /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ |
| 1526 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 1527 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1528 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1529 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1530 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1531 | { |
| 1532 | u32 val; |
| 1533 | int i; |
| 1534 | |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1535 | /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ |
| 1536 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1537 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
| 1538 | udelay(10); |
| 1539 | } |
| 1540 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1541 | if (setChip) { |
| 1542 | if ((REG_READ(ah, AR_RTC_STATUS) & |
| 1543 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { |
| 1544 | if (ath9k_hw_set_reset_reg(ah, |
| 1545 | ATH9K_RESET_POWER_ON) != true) { |
| 1546 | return false; |
| 1547 | } |
Luis R. Rodriguez | e041228 | 2010-04-15 17:38:15 -0400 | [diff] [blame] | 1548 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1549 | ath9k_hw_init_pll(ah, NULL); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1550 | } |
| 1551 | if (AR_SREV_9100(ah)) |
| 1552 | REG_SET_BIT(ah, AR_RTC_RESET, |
| 1553 | AR_RTC_RESET_EN); |
| 1554 | |
| 1555 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1556 | AR_RTC_FORCE_WAKE_EN); |
| 1557 | udelay(50); |
| 1558 | |
| 1559 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
| 1560 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; |
| 1561 | if (val == AR_RTC_STATUS_ON) |
| 1562 | break; |
| 1563 | udelay(50); |
| 1564 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1565 | AR_RTC_FORCE_WAKE_EN); |
| 1566 | } |
| 1567 | if (i == 0) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1568 | ath_err(ath9k_hw_common(ah), |
| 1569 | "Failed to wakeup in %uus\n", |
| 1570 | POWER_UP_TIME / 20); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1571 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1572 | } |
| 1573 | } |
| 1574 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1575 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1576 | |
| 1577 | return true; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1578 | } |
| 1579 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1580 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1581 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1582 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1583 | int status = true, setChip = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1584 | static const char *modes[] = { |
| 1585 | "AWAKE", |
| 1586 | "FULL-SLEEP", |
| 1587 | "NETWORK SLEEP", |
| 1588 | "UNDEFINED" |
| 1589 | }; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1590 | |
Gabor Juhos | cbdec97 | 2009-07-24 17:27:22 +0200 | [diff] [blame] | 1591 | if (ah->power_mode == mode) |
| 1592 | return status; |
| 1593 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1594 | ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", |
| 1595 | modes[ah->power_mode], modes[mode]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1596 | |
| 1597 | switch (mode) { |
| 1598 | case ATH9K_PM_AWAKE: |
| 1599 | status = ath9k_hw_set_power_awake(ah, setChip); |
| 1600 | break; |
| 1601 | case ATH9K_PM_FULL_SLEEP: |
| 1602 | ath9k_set_power_sleep(ah, setChip); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1603 | ah->chip_fullsleep = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1604 | break; |
| 1605 | case ATH9K_PM_NETWORK_SLEEP: |
| 1606 | ath9k_set_power_network_sleep(ah, setChip); |
| 1607 | break; |
| 1608 | default: |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1609 | ath_err(common, "Unknown power mode %u\n", mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1610 | return false; |
| 1611 | } |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1612 | ah->power_mode = mode; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1613 | |
Luis R. Rodriguez | 69f4aab | 2010-12-07 15:13:23 -0800 | [diff] [blame] | 1614 | /* |
| 1615 | * XXX: If this warning never comes up after a while then |
| 1616 | * simply keep the ATH_DBG_WARN_ON_ONCE() but make |
| 1617 | * ath9k_hw_setpower() return type void. |
| 1618 | */ |
Sujith Manoharan | 97dcec5 | 2010-12-20 08:02:42 +0530 | [diff] [blame] | 1619 | |
| 1620 | if (!(ah->ah_flags & AH_UNPLUGGED)) |
| 1621 | ATH_DBG_WARN_ON_ONCE(!status); |
Luis R. Rodriguez | 69f4aab | 2010-12-07 15:13:23 -0800 | [diff] [blame] | 1622 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1623 | return status; |
| 1624 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1625 | EXPORT_SYMBOL(ath9k_hw_setpower); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1626 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1627 | /*******************/ |
| 1628 | /* Beacon Handling */ |
| 1629 | /*******************/ |
| 1630 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1631 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1632 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1633 | int flags = 0; |
| 1634 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1635 | ENABLE_REGWRITE_BUFFER(ah); |
| 1636 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1637 | switch (ah->opmode) { |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1638 | case NL80211_IFTYPE_ADHOC: |
Pat Erley | 9cb5412 | 2009-03-20 22:59:59 -0400 | [diff] [blame] | 1639 | case NL80211_IFTYPE_MESH_POINT: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1640 | REG_SET_BIT(ah, AR_TXCFG, |
| 1641 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); |
| 1642 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, |
| 1643 | TU_TO_USEC(next_beacon + |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1644 | (ah->atim_window ? ah-> |
| 1645 | atim_window : 1))); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1646 | flags |= AR_NDP_TIMER_EN; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1647 | case NL80211_IFTYPE_AP: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1648 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
| 1649 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, |
| 1650 | TU_TO_USEC(next_beacon - |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1651 | ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1652 | dma_beacon_response_time)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1653 | REG_WRITE(ah, AR_NEXT_SWBA, |
| 1654 | TU_TO_USEC(next_beacon - |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1655 | ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1656 | sw_beacon_response_time)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1657 | flags |= |
| 1658 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; |
| 1659 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1660 | default: |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1661 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, |
| 1662 | "%s: unsupported opmode: %d\n", |
| 1663 | __func__, ah->opmode); |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1664 | return; |
| 1665 | break; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1666 | } |
| 1667 | |
| 1668 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); |
| 1669 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); |
| 1670 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); |
| 1671 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); |
| 1672 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1673 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1674 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1675 | beacon_period &= ~ATH9K_BEACON_ENA; |
| 1676 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1677 | ath9k_hw_reset_tsf(ah); |
| 1678 | } |
| 1679 | |
| 1680 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); |
| 1681 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1682 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1683 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1684 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1685 | const struct ath9k_beacon_state *bs) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1686 | { |
| 1687 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1688 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1689 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1690 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1691 | ENABLE_REGWRITE_BUFFER(ah); |
| 1692 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1693 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); |
| 1694 | |
| 1695 | REG_WRITE(ah, AR_BEACON_PERIOD, |
| 1696 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); |
| 1697 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, |
| 1698 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); |
| 1699 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1700 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1701 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1702 | REG_RMW_FIELD(ah, AR_RSSI_THR, |
| 1703 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); |
| 1704 | |
| 1705 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; |
| 1706 | |
| 1707 | if (bs->bs_sleepduration > beaconintval) |
| 1708 | beaconintval = bs->bs_sleepduration; |
| 1709 | |
| 1710 | dtimperiod = bs->bs_dtimperiod; |
| 1711 | if (bs->bs_sleepduration > dtimperiod) |
| 1712 | dtimperiod = bs->bs_sleepduration; |
| 1713 | |
| 1714 | if (beaconintval == dtimperiod) |
| 1715 | nextTbtt = bs->bs_nextdtim; |
| 1716 | else |
| 1717 | nextTbtt = bs->bs_nexttbtt; |
| 1718 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1719 | ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
| 1720 | ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); |
| 1721 | ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); |
| 1722 | ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1723 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1724 | ENABLE_REGWRITE_BUFFER(ah); |
| 1725 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1726 | REG_WRITE(ah, AR_NEXT_DTIM, |
| 1727 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); |
| 1728 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); |
| 1729 | |
| 1730 | REG_WRITE(ah, AR_SLEEP1, |
| 1731 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) |
| 1732 | | AR_SLEEP1_ASSUME_DTIM); |
| 1733 | |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1734 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1735 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); |
| 1736 | else |
| 1737 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; |
| 1738 | |
| 1739 | REG_WRITE(ah, AR_SLEEP2, |
| 1740 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); |
| 1741 | |
| 1742 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
| 1743 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); |
| 1744 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1745 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1746 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1747 | REG_SET_BIT(ah, AR_TIMER_MODE, |
| 1748 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | |
| 1749 | AR_DTIM_TIMER_EN); |
| 1750 | |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 1751 | /* TSF Out of Range Threshold */ |
| 1752 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1753 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1754 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1755 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1756 | /*******************/ |
| 1757 | /* HW Capabilities */ |
| 1758 | /*******************/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1759 | |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1760 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1761 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1762 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1763 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1764 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1765 | struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1766 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1767 | u16 capField = 0, eeval; |
Vasanthakumar Thiagarajan | 47c80de | 2010-12-06 04:27:43 -0800 | [diff] [blame] | 1768 | u8 ant_div_ctl1, tx_chainmask, rx_chainmask; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1769 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1770 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1771 | regulatory->current_rd = eeval; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1772 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1773 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); |
Felix Fietkau | e17f83e | 2010-09-22 12:34:53 +0200 | [diff] [blame] | 1774 | if (AR_SREV_9285_12_OR_LATER(ah)) |
Sujith | fec0de1 | 2009-02-12 10:06:43 +0530 | [diff] [blame] | 1775 | eeval |= AR9285_RDEXT_DEFAULT; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1776 | regulatory->current_rd_ext = eeval; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1777 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1778 | capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1779 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1780 | if (ah->opmode != NL80211_IFTYPE_AP && |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 1781 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1782 | if (regulatory->current_rd == 0x64 || |
| 1783 | regulatory->current_rd == 0x65) |
| 1784 | regulatory->current_rd += 5; |
| 1785 | else if (regulatory->current_rd == 0x41) |
| 1786 | regulatory->current_rd = 0x43; |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1787 | ath_dbg(common, ATH_DBG_REGULATORY, |
| 1788 | "regdomain mapped to 0x%x\n", regulatory->current_rd); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1789 | } |
Sujith | dc2222a | 2008-08-14 13:26:55 +0530 | [diff] [blame] | 1790 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1791 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1792 | if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1793 | ath_err(common, |
| 1794 | "no band has been marked as supported in EEPROM\n"); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1795 | return -EINVAL; |
| 1796 | } |
| 1797 | |
Felix Fietkau | d465991 | 2010-10-14 16:02:39 +0200 | [diff] [blame] | 1798 | if (eeval & AR5416_OPFLAGS_11A) |
| 1799 | pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1800 | |
Felix Fietkau | d465991 | 2010-10-14 16:02:39 +0200 | [diff] [blame] | 1801 | if (eeval & AR5416_OPFLAGS_11G) |
| 1802 | pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1803 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1804 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1805 | /* |
| 1806 | * For AR9271 we will temporarilly uses the rx chainmax as read from |
| 1807 | * the EEPROM. |
| 1808 | */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 1809 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1810 | !(eeval & AR5416_OPFLAGS_11A) && |
| 1811 | !(AR_SREV_9271(ah))) |
| 1812 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 1813 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
| 1814 | else |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1815 | /* Use rx_chainmask from EEPROM. */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 1816 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1817 | |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 1818 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1819 | |
Felix Fietkau | 02d2ebb | 2010-11-22 15:39:39 +0100 | [diff] [blame] | 1820 | /* enable key search for every frame in an aggregate */ |
| 1821 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 1822 | ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; |
| 1823 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1824 | pCap->low_2ghz_chan = 2312; |
| 1825 | pCap->high_2ghz_chan = 2732; |
| 1826 | |
| 1827 | pCap->low_5ghz_chan = 4920; |
| 1828 | pCap->high_5ghz_chan = 6100; |
| 1829 | |
Bruno Randolf | ce2220d | 2010-09-17 11:36:25 +0900 | [diff] [blame] | 1830 | common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; |
| 1831 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1832 | if (ah->config.ht_enable) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1833 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
| 1834 | else |
| 1835 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; |
| 1836 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1837 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) |
| 1838 | pCap->total_queues = |
| 1839 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); |
| 1840 | else |
| 1841 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; |
| 1842 | |
| 1843 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) |
| 1844 | pCap->keycache_size = |
| 1845 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); |
| 1846 | else |
| 1847 | pCap->keycache_size = AR_KEYTABLE_SIZE; |
| 1848 | |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 1849 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
| 1850 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; |
| 1851 | else |
| 1852 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1853 | |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 1854 | if (AR_SREV_9271(ah)) |
| 1855 | pCap->num_gpio_pins = AR9271_NUM_GPIO; |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 1856 | else if (AR_DEVID_7010(ah)) |
| 1857 | pCap->num_gpio_pins = AR7010_NUM_GPIO; |
Felix Fietkau | e17f83e | 2010-09-22 12:34:53 +0200 | [diff] [blame] | 1858 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 1859 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 1860 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1861 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
| 1862 | else |
| 1863 | pCap->num_gpio_pins = AR_NUM_GPIO; |
| 1864 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1865 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
| 1866 | pCap->hw_caps |= ATH9K_HW_CAP_CST; |
| 1867 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; |
| 1868 | } else { |
| 1869 | pCap->rts_aggr_limit = (8 * 1024); |
| 1870 | } |
| 1871 | |
| 1872 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
| 1873 | |
Senthil Balasubramanian | e97275c | 2008-11-13 18:00:02 +0530 | [diff] [blame] | 1874 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1875 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
| 1876 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { |
| 1877 | ah->rfkill_gpio = |
| 1878 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); |
| 1879 | ah->rfkill_polarity = |
| 1880 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1881 | |
| 1882 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; |
| 1883 | } |
| 1884 | #endif |
Vasanthakumar Thiagarajan | d5d1154 | 2010-05-17 18:57:56 -0700 | [diff] [blame] | 1885 | if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) |
Vivek Natarajan | bde748a | 2010-04-05 14:48:05 +0530 | [diff] [blame] | 1886 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
| 1887 | else |
| 1888 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1889 | |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 1890 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1891 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
| 1892 | else |
| 1893 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; |
| 1894 | |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1895 | if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1896 | pCap->reg_cap = |
| 1897 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | |
| 1898 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | |
| 1899 | AR_EEPROM_EEREGCAP_EN_KK_U2 | |
| 1900 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; |
| 1901 | } else { |
| 1902 | pCap->reg_cap = |
| 1903 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | |
| 1904 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; |
| 1905 | } |
| 1906 | |
Senthil Balasubramanian | ebb90cf | 2009-09-18 15:07:33 +0530 | [diff] [blame] | 1907 | /* Advertise midband for AR5416 with FCC midband set in eeprom */ |
| 1908 | if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && |
| 1909 | AR_SREV_5416(ah)) |
| 1910 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1911 | |
Vasanthakumar Thiagarajan | 8f5dcb1 | 2010-11-26 06:10:06 -0800 | [diff] [blame] | 1912 | if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1913 | btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; |
| 1914 | btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; |
Vasanthakumar Thiagarajan | 22f25d0 | 2009-08-26 21:08:47 +0530 | [diff] [blame] | 1915 | |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 1916 | if (AR_SREV_9285(ah)) { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1917 | btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; |
| 1918 | btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 1919 | } else { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1920 | btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 1921 | } |
Vasanthakumar Thiagarajan | 22f25d0 | 2009-08-26 21:08:47 +0530 | [diff] [blame] | 1922 | } else { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1923 | btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; |
Vasanthakumar Thiagarajan | c97c92d | 2009-01-02 15:35:46 +0530 | [diff] [blame] | 1924 | } |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1925 | |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 1926 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
Vasanthakumar Thiagarajan | 784ad50 | 2010-12-06 04:27:40 -0800 | [diff] [blame] | 1927 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; |
| 1928 | if (!AR_SREV_9485(ah)) |
| 1929 | pCap->hw_caps |= ATH9K_HW_CAP_LDPC; |
| 1930 | |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 1931 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
| 1932 | pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; |
| 1933 | pCap->rx_status_len = sizeof(struct ar9003_rxs); |
Vasanthakumar Thiagarajan | 162c3be | 2010-04-15 17:38:41 -0400 | [diff] [blame] | 1934 | pCap->tx_desc_len = sizeof(struct ar9003_txc); |
Vasanthakumar Thiagarajan | 5088c2f | 2010-04-15 17:39:34 -0400 | [diff] [blame] | 1935 | pCap->txs_len = sizeof(struct ar9003_txs); |
Felix Fietkau | 4935250 | 2010-06-12 00:33:59 -0400 | [diff] [blame] | 1936 | if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) |
| 1937 | pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; |
Vasanthakumar Thiagarajan | 162c3be | 2010-04-15 17:38:41 -0400 | [diff] [blame] | 1938 | } else { |
| 1939 | pCap->tx_desc_len = sizeof(struct ath_desc); |
Felix Fietkau | 6b42e8d | 2010-04-26 15:04:35 -0400 | [diff] [blame] | 1940 | if (AR_SREV_9280_20(ah) && |
| 1941 | ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= |
| 1942 | AR5416_EEP_MINOR_VER_16) || |
| 1943 | ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) |
| 1944 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 1945 | } |
Vasanthakumar Thiagarajan | 1adf02f | 2010-04-15 17:38:24 -0400 | [diff] [blame] | 1946 | |
Vasanthakumar Thiagarajan | 6c84ce0 | 2010-04-15 17:39:16 -0400 | [diff] [blame] | 1947 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 1948 | pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; |
| 1949 | |
Senthil Balasubramanian | 6ee63f5 | 2010-11-10 05:03:16 -0800 | [diff] [blame] | 1950 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 1951 | ah->ent_mode = REG_READ(ah, AR_ENT_OTP); |
| 1952 | |
Felix Fietkau | a42acef | 2010-09-22 12:34:54 +0200 | [diff] [blame] | 1953 | if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) |
Vasanthakumar Thiagarajan | 6473d24 | 2010-05-13 18:42:38 -0700 | [diff] [blame] | 1954 | pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; |
| 1955 | |
Vasanthakumar Thiagarajan | 754dc53 | 2010-09-02 01:34:41 -0700 | [diff] [blame] | 1956 | if (AR_SREV_9285(ah)) |
| 1957 | if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { |
| 1958 | ant_div_ctl1 = |
| 1959 | ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); |
| 1960 | if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) |
| 1961 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; |
| 1962 | } |
Mohammed Shafi Shajakhan | ea066d5 | 2010-11-23 20:42:27 +0530 | [diff] [blame] | 1963 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1964 | if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) |
| 1965 | pCap->hw_caps |= ATH9K_HW_CAP_APM; |
| 1966 | } |
| 1967 | |
| 1968 | |
Vasanthakumar Thiagarajan | 754dc53 | 2010-09-02 01:34:41 -0700 | [diff] [blame] | 1969 | |
Vasanthakumar Thiagarajan | 8060e16 | 2010-12-06 04:27:42 -0800 | [diff] [blame] | 1970 | if (AR_SREV_9485_10(ah)) { |
| 1971 | pCap->pcie_lcr_extsync_en = true; |
| 1972 | pCap->pcie_lcr_offset = 0x80; |
| 1973 | } |
| 1974 | |
Vasanthakumar Thiagarajan | 47c80de | 2010-12-06 04:27:43 -0800 | [diff] [blame] | 1975 | tx_chainmask = pCap->tx_chainmask; |
| 1976 | rx_chainmask = pCap->rx_chainmask; |
| 1977 | while (tx_chainmask || rx_chainmask) { |
| 1978 | if (tx_chainmask & BIT(0)) |
| 1979 | pCap->max_txchains++; |
| 1980 | if (rx_chainmask & BIT(0)) |
| 1981 | pCap->max_rxchains++; |
| 1982 | |
| 1983 | tx_chainmask >>= 1; |
| 1984 | rx_chainmask >>= 1; |
| 1985 | } |
| 1986 | |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1987 | return 0; |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 1988 | } |
| 1989 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1990 | /****************************/ |
| 1991 | /* GPIO / RFKILL / Antennae */ |
| 1992 | /****************************/ |
| 1993 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1994 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1995 | u32 gpio, u32 type) |
| 1996 | { |
| 1997 | int addr; |
| 1998 | u32 gpio_shift, tmp; |
| 1999 | |
| 2000 | if (gpio > 11) |
| 2001 | addr = AR_GPIO_OUTPUT_MUX3; |
| 2002 | else if (gpio > 5) |
| 2003 | addr = AR_GPIO_OUTPUT_MUX2; |
| 2004 | else |
| 2005 | addr = AR_GPIO_OUTPUT_MUX1; |
| 2006 | |
| 2007 | gpio_shift = (gpio % 6) * 5; |
| 2008 | |
| 2009 | if (AR_SREV_9280_20_OR_LATER(ah) |
| 2010 | || (addr != AR_GPIO_OUTPUT_MUX1)) { |
| 2011 | REG_RMW(ah, addr, (type << gpio_shift), |
| 2012 | (0x1f << gpio_shift)); |
| 2013 | } else { |
| 2014 | tmp = REG_READ(ah, addr); |
| 2015 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); |
| 2016 | tmp &= ~(0x1f << gpio_shift); |
| 2017 | tmp |= (type << gpio_shift); |
| 2018 | REG_WRITE(ah, addr, tmp); |
| 2019 | } |
| 2020 | } |
| 2021 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2022 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2023 | { |
| 2024 | u32 gpio_shift; |
| 2025 | |
Luis R. Rodriguez | 9680e8a | 2009-09-13 23:28:00 -0700 | [diff] [blame] | 2026 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2027 | |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 2028 | if (AR_DEVID_7010(ah)) { |
| 2029 | gpio_shift = gpio; |
| 2030 | REG_RMW(ah, AR7010_GPIO_OE, |
| 2031 | (AR7010_GPIO_OE_AS_INPUT << gpio_shift), |
| 2032 | (AR7010_GPIO_OE_MASK << gpio_shift)); |
| 2033 | return; |
| 2034 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2035 | |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 2036 | gpio_shift = gpio << 1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2037 | REG_RMW(ah, |
| 2038 | AR_GPIO_OE_OUT, |
| 2039 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), |
| 2040 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); |
| 2041 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2042 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2043 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2044 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2045 | { |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 2046 | #define MS_REG_READ(x, y) \ |
| 2047 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) |
| 2048 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2049 | if (gpio >= ah->caps.num_gpio_pins) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2050 | return 0xffffffff; |
| 2051 | |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 2052 | if (AR_DEVID_7010(ah)) { |
| 2053 | u32 val; |
| 2054 | val = REG_READ(ah, AR7010_GPIO_IN); |
| 2055 | return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; |
| 2056 | } else if (AR_SREV_9300_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 9306990 | 2010-11-30 23:24:09 -0800 | [diff] [blame] | 2057 | return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & |
| 2058 | AR_GPIO_BIT(gpio)) != 0; |
Felix Fietkau | 783dfca | 2010-04-15 17:38:11 -0400 | [diff] [blame] | 2059 | else if (AR_SREV_9271(ah)) |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 2060 | return MS_REG_READ(AR9271, gpio) != 0; |
Felix Fietkau | a42acef | 2010-09-22 12:34:54 +0200 | [diff] [blame] | 2061 | else if (AR_SREV_9287_11_OR_LATER(ah)) |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 2062 | return MS_REG_READ(AR9287, gpio) != 0; |
Felix Fietkau | e17f83e | 2010-09-22 12:34:53 +0200 | [diff] [blame] | 2063 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 2064 | return MS_REG_READ(AR9285, gpio) != 0; |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 2065 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 2066 | return MS_REG_READ(AR928X, gpio) != 0; |
| 2067 | else |
| 2068 | return MS_REG_READ(AR, gpio) != 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2069 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2070 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2071 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2072 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2073 | u32 ah_signal_type) |
| 2074 | { |
| 2075 | u32 gpio_shift; |
| 2076 | |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 2077 | if (AR_DEVID_7010(ah)) { |
| 2078 | gpio_shift = gpio; |
| 2079 | REG_RMW(ah, AR7010_GPIO_OE, |
| 2080 | (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), |
| 2081 | (AR7010_GPIO_OE_MASK << gpio_shift)); |
| 2082 | return; |
| 2083 | } |
| 2084 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2085 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2086 | gpio_shift = 2 * gpio; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2087 | REG_RMW(ah, |
| 2088 | AR_GPIO_OE_OUT, |
| 2089 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), |
| 2090 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); |
| 2091 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2092 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2093 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2094 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2095 | { |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 2096 | if (AR_DEVID_7010(ah)) { |
| 2097 | val = val ? 0 : 1; |
| 2098 | REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), |
| 2099 | AR_GPIO_BIT(gpio)); |
| 2100 | return; |
| 2101 | } |
| 2102 | |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 2103 | if (AR_SREV_9271(ah)) |
| 2104 | val = ~val; |
| 2105 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2106 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
| 2107 | AR_GPIO_BIT(gpio)); |
| 2108 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2109 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2110 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2111 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2112 | { |
| 2113 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
| 2114 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2115 | EXPORT_SYMBOL(ath9k_hw_getdefantenna); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2116 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2117 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2118 | { |
| 2119 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
| 2120 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2121 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2122 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2123 | /*********************/ |
| 2124 | /* General Operation */ |
| 2125 | /*********************/ |
| 2126 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2127 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2128 | { |
| 2129 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
| 2130 | u32 phybits = REG_READ(ah, AR_PHY_ERR); |
| 2131 | |
| 2132 | if (phybits & AR_PHY_ERR_RADAR) |
| 2133 | bits |= ATH9K_RX_FILTER_PHYRADAR; |
| 2134 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) |
| 2135 | bits |= ATH9K_RX_FILTER_PHYERR; |
| 2136 | |
| 2137 | return bits; |
| 2138 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2139 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2140 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2141 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2142 | { |
| 2143 | u32 phybits; |
| 2144 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 2145 | ENABLE_REGWRITE_BUFFER(ah); |
| 2146 | |
Sujith | 7ea310b | 2009-09-03 12:08:43 +0530 | [diff] [blame] | 2147 | REG_WRITE(ah, AR_RX_FILTER, bits); |
| 2148 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2149 | phybits = 0; |
| 2150 | if (bits & ATH9K_RX_FILTER_PHYRADAR) |
| 2151 | phybits |= AR_PHY_ERR_RADAR; |
| 2152 | if (bits & ATH9K_RX_FILTER_PHYERR) |
| 2153 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; |
| 2154 | REG_WRITE(ah, AR_PHY_ERR, phybits); |
| 2155 | |
| 2156 | if (phybits) |
| 2157 | REG_WRITE(ah, AR_RXCFG, |
| 2158 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); |
| 2159 | else |
| 2160 | REG_WRITE(ah, AR_RXCFG, |
| 2161 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 2162 | |
| 2163 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2164 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2165 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2166 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2167 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2168 | { |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 2169 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
| 2170 | return false; |
| 2171 | |
| 2172 | ath9k_hw_init_pll(ah, NULL); |
| 2173 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2174 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2175 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2176 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2177 | bool ath9k_hw_disable(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2178 | { |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 2179 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2180 | return false; |
| 2181 | |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 2182 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
| 2183 | return false; |
| 2184 | |
| 2185 | ath9k_hw_init_pll(ah, NULL); |
| 2186 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2187 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2188 | EXPORT_SYMBOL(ath9k_hw_disable); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2189 | |
Felix Fietkau | de40f31 | 2010-10-20 03:08:53 +0200 | [diff] [blame] | 2190 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2191 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2192 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2193 | struct ath9k_channel *chan = ah->curchan; |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 2194 | struct ieee80211_channel *channel = chan->chan; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2195 | |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2196 | regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2197 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 2198 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2199 | ath9k_regd_get_ctl(regulatory, chan), |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 2200 | channel->max_antenna_gain * 2, |
| 2201 | channel->max_power * 2, |
| 2202 | min((u32) MAX_RATE_POWER, |
Felix Fietkau | de40f31 | 2010-10-20 03:08:53 +0200 | [diff] [blame] | 2203 | (u32) regulatory->power_limit), test); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2204 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2205 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2206 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2207 | void ath9k_hw_setopmode(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2208 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2209 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2210 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2211 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2212 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2213 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2214 | { |
| 2215 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
| 2216 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); |
| 2217 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2218 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2219 | |
Luis R. Rodriguez | f2b2143 | 2009-09-10 08:50:20 -0700 | [diff] [blame] | 2220 | void ath9k_hw_write_associd(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2221 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 2222 | struct ath_common *common = ath9k_hw_common(ah); |
| 2223 | |
| 2224 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); |
| 2225 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | |
| 2226 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2227 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2228 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2229 | |
Benoit Papillault | 1c0fc65 | 2010-04-16 00:07:26 +0200 | [diff] [blame] | 2230 | #define ATH9K_MAX_TSF_READ 10 |
| 2231 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2232 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2233 | { |
Benoit Papillault | 1c0fc65 | 2010-04-16 00:07:26 +0200 | [diff] [blame] | 2234 | u32 tsf_lower, tsf_upper1, tsf_upper2; |
| 2235 | int i; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2236 | |
Benoit Papillault | 1c0fc65 | 2010-04-16 00:07:26 +0200 | [diff] [blame] | 2237 | tsf_upper1 = REG_READ(ah, AR_TSF_U32); |
| 2238 | for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { |
| 2239 | tsf_lower = REG_READ(ah, AR_TSF_L32); |
| 2240 | tsf_upper2 = REG_READ(ah, AR_TSF_U32); |
| 2241 | if (tsf_upper2 == tsf_upper1) |
| 2242 | break; |
| 2243 | tsf_upper1 = tsf_upper2; |
| 2244 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2245 | |
Benoit Papillault | 1c0fc65 | 2010-04-16 00:07:26 +0200 | [diff] [blame] | 2246 | WARN_ON( i == ATH9K_MAX_TSF_READ ); |
| 2247 | |
| 2248 | return (((u64)tsf_upper1 << 32) | tsf_lower); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2249 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2250 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2251 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2252 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2253 | { |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2254 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
Alina Friedrichsen | b9a1619 | 2009-03-02 23:28:38 +0100 | [diff] [blame] | 2255 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2256 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2257 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2258 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2259 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2260 | { |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 2261 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
| 2262 | AH_TSF_WRITE_TIMEOUT)) |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2263 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 2264 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 2265 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2266 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2267 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2268 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2269 | |
Sujith | 54e4cec | 2009-08-07 09:45:09 +0530 | [diff] [blame] | 2270 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2271 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2272 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2273 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2274 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2275 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2276 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2277 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2278 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 2279 | void ath9k_hw_set11nmac2040(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2280 | { |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 2281 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2282 | u32 macmode; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2283 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 2284 | if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2285 | macmode = AR_2040_JOINED_RX_CLEAR; |
| 2286 | else |
| 2287 | macmode = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2288 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2289 | REG_WRITE(ah, AR_2040_MODE, macmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2290 | } |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2291 | |
| 2292 | /* HW Generic timers configuration */ |
| 2293 | |
| 2294 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = |
| 2295 | { |
| 2296 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2297 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2298 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2299 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2300 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2301 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2302 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2303 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2304 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, |
| 2305 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, |
| 2306 | AR_NDP2_TIMER_MODE, 0x0002}, |
| 2307 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, |
| 2308 | AR_NDP2_TIMER_MODE, 0x0004}, |
| 2309 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, |
| 2310 | AR_NDP2_TIMER_MODE, 0x0008}, |
| 2311 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, |
| 2312 | AR_NDP2_TIMER_MODE, 0x0010}, |
| 2313 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, |
| 2314 | AR_NDP2_TIMER_MODE, 0x0020}, |
| 2315 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, |
| 2316 | AR_NDP2_TIMER_MODE, 0x0040}, |
| 2317 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, |
| 2318 | AR_NDP2_TIMER_MODE, 0x0080} |
| 2319 | }; |
| 2320 | |
| 2321 | /* HW generic timer primitives */ |
| 2322 | |
| 2323 | /* compute and clear index of rightmost 1 */ |
| 2324 | static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) |
| 2325 | { |
| 2326 | u32 b; |
| 2327 | |
| 2328 | b = *mask; |
| 2329 | b &= (0-b); |
| 2330 | *mask &= ~b; |
| 2331 | b *= debruijn32; |
| 2332 | b >>= 27; |
| 2333 | |
| 2334 | return timer_table->gen_timer_index[b]; |
| 2335 | } |
| 2336 | |
Felix Fietkau | 744bcb4 | 2010-10-15 20:03:33 +0200 | [diff] [blame] | 2337 | static u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2338 | { |
| 2339 | return REG_READ(ah, AR_TSF_L32); |
| 2340 | } |
| 2341 | |
| 2342 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, |
| 2343 | void (*trigger)(void *), |
| 2344 | void (*overflow)(void *), |
| 2345 | void *arg, |
| 2346 | u8 timer_index) |
| 2347 | { |
| 2348 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2349 | struct ath_gen_timer *timer; |
| 2350 | |
| 2351 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); |
| 2352 | |
| 2353 | if (timer == NULL) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 2354 | ath_err(ath9k_hw_common(ah), |
| 2355 | "Failed to allocate memory for hw timer[%d]\n", |
| 2356 | timer_index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2357 | return NULL; |
| 2358 | } |
| 2359 | |
| 2360 | /* allocate a hardware generic timer slot */ |
| 2361 | timer_table->timers[timer_index] = timer; |
| 2362 | timer->index = timer_index; |
| 2363 | timer->trigger = trigger; |
| 2364 | timer->overflow = overflow; |
| 2365 | timer->arg = arg; |
| 2366 | |
| 2367 | return timer; |
| 2368 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2369 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2370 | |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 2371 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
| 2372 | struct ath_gen_timer *timer, |
| 2373 | u32 timer_next, |
| 2374 | u32 timer_period) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2375 | { |
| 2376 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2377 | u32 tsf; |
| 2378 | |
| 2379 | BUG_ON(!timer_period); |
| 2380 | |
| 2381 | set_bit(timer->index, &timer_table->timer_mask.timer_bits); |
| 2382 | |
| 2383 | tsf = ath9k_hw_gettsf32(ah); |
| 2384 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2385 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, |
| 2386 | "current tsf %x period %x timer_next %x\n", |
| 2387 | tsf, timer_period, timer_next); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2388 | |
| 2389 | /* |
| 2390 | * Pull timer_next forward if the current TSF already passed it |
| 2391 | * because of software latency |
| 2392 | */ |
| 2393 | if (timer_next < tsf) |
| 2394 | timer_next = tsf + timer_period; |
| 2395 | |
| 2396 | /* |
| 2397 | * Program generic timer registers |
| 2398 | */ |
| 2399 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, |
| 2400 | timer_next); |
| 2401 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, |
| 2402 | timer_period); |
| 2403 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 2404 | gen_tmr_configuration[timer->index].mode_mask); |
| 2405 | |
| 2406 | /* Enable both trigger and thresh interrupt masks */ |
| 2407 | REG_SET_BIT(ah, AR_IMR_S5, |
| 2408 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| 2409 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2410 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2411 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2412 | |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 2413 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2414 | { |
| 2415 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2416 | |
| 2417 | if ((timer->index < AR_FIRST_NDP_TIMER) || |
| 2418 | (timer->index >= ATH_MAX_GEN_TIMER)) { |
| 2419 | return; |
| 2420 | } |
| 2421 | |
| 2422 | /* Clear generic timer enable bits. */ |
| 2423 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 2424 | gen_tmr_configuration[timer->index].mode_mask); |
| 2425 | |
| 2426 | /* Disable both trigger and thresh interrupt masks */ |
| 2427 | REG_CLR_BIT(ah, AR_IMR_S5, |
| 2428 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| 2429 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); |
| 2430 | |
| 2431 | clear_bit(timer->index, &timer_table->timer_mask.timer_bits); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2432 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2433 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2434 | |
| 2435 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) |
| 2436 | { |
| 2437 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2438 | |
| 2439 | /* free the hardware generic timer slot */ |
| 2440 | timer_table->timers[timer->index] = NULL; |
| 2441 | kfree(timer); |
| 2442 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2443 | EXPORT_SYMBOL(ath_gen_timer_free); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2444 | |
| 2445 | /* |
| 2446 | * Generic Timer Interrupts handling |
| 2447 | */ |
| 2448 | void ath_gen_timer_isr(struct ath_hw *ah) |
| 2449 | { |
| 2450 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2451 | struct ath_gen_timer *timer; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2452 | struct ath_common *common = ath9k_hw_common(ah); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2453 | u32 trigger_mask, thresh_mask, index; |
| 2454 | |
| 2455 | /* get hardware generic timer interrupt status */ |
| 2456 | trigger_mask = ah->intr_gen_timer_trigger; |
| 2457 | thresh_mask = ah->intr_gen_timer_thresh; |
| 2458 | trigger_mask &= timer_table->timer_mask.val; |
| 2459 | thresh_mask &= timer_table->timer_mask.val; |
| 2460 | |
| 2461 | trigger_mask &= ~thresh_mask; |
| 2462 | |
| 2463 | while (thresh_mask) { |
| 2464 | index = rightmost_index(timer_table, &thresh_mask); |
| 2465 | timer = timer_table->timers[index]; |
| 2466 | BUG_ON(!timer); |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2467 | ath_dbg(common, ATH_DBG_HWTIMER, |
| 2468 | "TSF overflow for Gen timer %d\n", index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2469 | timer->overflow(timer->arg); |
| 2470 | } |
| 2471 | |
| 2472 | while (trigger_mask) { |
| 2473 | index = rightmost_index(timer_table, &trigger_mask); |
| 2474 | timer = timer_table->timers[index]; |
| 2475 | BUG_ON(!timer); |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2476 | ath_dbg(common, ATH_DBG_HWTIMER, |
| 2477 | "Gen timer[%d] trigger\n", index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2478 | timer->trigger(timer->arg); |
| 2479 | } |
| 2480 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2481 | EXPORT_SYMBOL(ath_gen_timer_isr); |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2482 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 2483 | /********/ |
| 2484 | /* HTC */ |
| 2485 | /********/ |
| 2486 | |
| 2487 | void ath9k_hw_htc_resetinit(struct ath_hw *ah) |
| 2488 | { |
| 2489 | ah->htc_reset_init = true; |
| 2490 | } |
| 2491 | EXPORT_SYMBOL(ath9k_hw_htc_resetinit); |
| 2492 | |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2493 | static struct { |
| 2494 | u32 version; |
| 2495 | const char * name; |
| 2496 | } ath_mac_bb_names[] = { |
| 2497 | /* Devices with external radios */ |
| 2498 | { AR_SREV_VERSION_5416_PCI, "5416" }, |
| 2499 | { AR_SREV_VERSION_5416_PCIE, "5418" }, |
| 2500 | { AR_SREV_VERSION_9100, "9100" }, |
| 2501 | { AR_SREV_VERSION_9160, "9160" }, |
| 2502 | /* Single-chip solutions */ |
| 2503 | { AR_SREV_VERSION_9280, "9280" }, |
| 2504 | { AR_SREV_VERSION_9285, "9285" }, |
Luis R. Rodriguez | 1115847 | 2009-10-27 12:59:35 -0400 | [diff] [blame] | 2505 | { AR_SREV_VERSION_9287, "9287" }, |
| 2506 | { AR_SREV_VERSION_9271, "9271" }, |
Luis R. Rodriguez | ec83903 | 2010-04-15 17:39:20 -0400 | [diff] [blame] | 2507 | { AR_SREV_VERSION_9300, "9300" }, |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2508 | }; |
| 2509 | |
| 2510 | /* For devices with external radios */ |
| 2511 | static struct { |
| 2512 | u16 version; |
| 2513 | const char * name; |
| 2514 | } ath_rf_names[] = { |
| 2515 | { 0, "5133" }, |
| 2516 | { AR_RAD5133_SREV_MAJOR, "5133" }, |
| 2517 | { AR_RAD5122_SREV_MAJOR, "5122" }, |
| 2518 | { AR_RAD2133_SREV_MAJOR, "2133" }, |
| 2519 | { AR_RAD2122_SREV_MAJOR, "2122" } |
| 2520 | }; |
| 2521 | |
| 2522 | /* |
| 2523 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. |
| 2524 | */ |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2525 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2526 | { |
| 2527 | int i; |
| 2528 | |
| 2529 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { |
| 2530 | if (ath_mac_bb_names[i].version == mac_bb_version) { |
| 2531 | return ath_mac_bb_names[i].name; |
| 2532 | } |
| 2533 | } |
| 2534 | |
| 2535 | return "????"; |
| 2536 | } |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2537 | |
| 2538 | /* |
| 2539 | * Return the RF name. "????" is returned if the RF is unknown. |
| 2540 | * Used for devices with external radios. |
| 2541 | */ |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2542 | static const char *ath9k_hw_rf_name(u16 rf_version) |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2543 | { |
| 2544 | int i; |
| 2545 | |
| 2546 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { |
| 2547 | if (ath_rf_names[i].version == rf_version) { |
| 2548 | return ath_rf_names[i].name; |
| 2549 | } |
| 2550 | } |
| 2551 | |
| 2552 | return "????"; |
| 2553 | } |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2554 | |
| 2555 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) |
| 2556 | { |
| 2557 | int used; |
| 2558 | |
| 2559 | /* chipsets >= AR9280 are single-chip */ |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 2560 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2561 | used = snprintf(hw_name, len, |
| 2562 | "Atheros AR%s Rev:%x", |
| 2563 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), |
| 2564 | ah->hw_version.macRev); |
| 2565 | } |
| 2566 | else { |
| 2567 | used = snprintf(hw_name, len, |
| 2568 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", |
| 2569 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), |
| 2570 | ah->hw_version.macRev, |
| 2571 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & |
| 2572 | AR_RADIO_SREV_MAJOR)), |
| 2573 | ah->hw_version.phyRev); |
| 2574 | } |
| 2575 | |
| 2576 | hw_name[used] = '\0'; |
| 2577 | } |
| 2578 | EXPORT_SYMBOL(ath9k_hw_name); |