blob: 1afb8bb85756ee55e5a2a82d5f1f825279c803ea [file] [log] [blame]
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -04002 * Copyright (c) 2008-2010 Atheros Communications Inc.
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070019#include <asm/unaligned.h>
20
Luis R. Rodriguezaf03abe2009-09-09 02:33:11 -070021#include "hw.h"
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -040022#include "hw-ops.h"
Luis R. Rodriguezcfe8cba2009-09-13 23:39:31 -070023#include "rc.h"
Luis R. Rodriguezb622a722010-04-15 17:39:28 -040024#include "ar9003_mac.h"
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070025
Sujithcbe61d82009-02-09 13:27:12 +053026static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070027
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040028MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static int __init ath9k_init(void)
34{
35 return 0;
36}
37module_init(ath9k_init);
38
39static void __exit ath9k_exit(void)
40{
41 return;
42}
43module_exit(ath9k_exit);
44
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -040045/* Private hardware callbacks */
46
47static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48{
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50}
51
52static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55}
56
Luis R. Rodriguez64773962010-04-15 17:38:17 -040057static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59{
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61}
62
Luis R. Rodriguez991312d2010-04-15 17:39:05 -040063static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64{
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69}
70
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -040071static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72{
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78}
79
Sujithf1dc5602008-10-29 10:16:30 +053080/********************/
81/* Helper Functions */
82/********************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070083
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020084static void ath9k_hw_set_clockrate(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +053085{
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -070086 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020087 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
Sujithcbe61d82009-02-09 13:27:12 +053089
Sujith2660b812009-02-09 13:27:26 +053090 if (!ah->curchan) /* should really check for CCK instead */
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020091 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
Vasanthakumar Thiagarajane5553722010-04-26 15:04:33 -040096 else
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020097 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
Sujithf1dc5602008-10-29 10:16:30 +0530103}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700104
Sujithcbe61d82009-02-09 13:27:12 +0530105static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
Sujithf1dc5602008-10-29 10:16:30 +0530106{
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200107 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +0530108
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200109 return usecs * common->clockrate;
Sujithf1dc5602008-10-29 10:16:30 +0530110}
111
Sujith0caa7b12009-02-16 13:23:20 +0530112bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700113{
114 int i;
115
Sujith0caa7b12009-02-16 13:23:20 +0530116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
Sujith04bd4632008-11-28 22:18:05 +0530124
Joe Perches226afe62010-12-02 19:12:37 -0800125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
Sujithf1dc5602008-10-29 10:16:30 +0530128
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700129 return false;
130}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400131EXPORT_SYMBOL(ath9k_hw_wait);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700132
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700133u32 ath9k_hw_reverse_bits(u32 val, u32 n)
134{
135 u32 retval;
136 int i;
137
138 for (i = 0, retval = 0; i < n; i++) {
139 retval = (retval << 1) | (val & 1);
140 val >>= 1;
141 }
142 return retval;
143}
144
Sujithcbe61d82009-02-09 13:27:12 +0530145bool ath9k_get_channel_edges(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530146 u16 flags, u16 *low,
147 u16 *high)
148{
Sujith2660b812009-02-09 13:27:26 +0530149 struct ath9k_hw_capabilities *pCap = &ah->caps;
Sujithf1dc5602008-10-29 10:16:30 +0530150
151 if (flags & CHANNEL_5GHZ) {
152 *low = pCap->low_5ghz_chan;
153 *high = pCap->high_5ghz_chan;
154 return true;
155 }
156 if ((flags & CHANNEL_2GHZ)) {
157 *low = pCap->low_2ghz_chan;
158 *high = pCap->high_2ghz_chan;
159 return true;
160 }
161 return false;
162}
163
Sujithcbe61d82009-02-09 13:27:12 +0530164u16 ath9k_hw_computetxtime(struct ath_hw *ah,
Felix Fietkau545750d2009-11-23 22:21:01 +0100165 u8 phy, int kbps,
Sujithf1dc5602008-10-29 10:16:30 +0530166 u32 frameLen, u16 rateix,
167 bool shortPreamble)
168{
169 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
Sujithf1dc5602008-10-29 10:16:30 +0530170
171 if (kbps == 0)
172 return 0;
173
Felix Fietkau545750d2009-11-23 22:21:01 +0100174 switch (phy) {
Sujith46d14a52008-11-18 09:08:13 +0530175 case WLAN_RC_PHY_CCK:
Sujithf1dc5602008-10-29 10:16:30 +0530176 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
Felix Fietkau545750d2009-11-23 22:21:01 +0100177 if (shortPreamble)
Sujithf1dc5602008-10-29 10:16:30 +0530178 phyTime >>= 1;
179 numBits = frameLen << 3;
180 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
181 break;
Sujith46d14a52008-11-18 09:08:13 +0530182 case WLAN_RC_PHY_OFDM:
Sujith2660b812009-02-09 13:27:26 +0530183 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530184 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
185 numBits = OFDM_PLCP_BITS + (frameLen << 3);
186 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
187 txTime = OFDM_SIFS_TIME_QUARTER
188 + OFDM_PREAMBLE_TIME_QUARTER
189 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
Sujith2660b812009-02-09 13:27:26 +0530190 } else if (ah->curchan &&
191 IS_CHAN_HALF_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME_HALF +
196 OFDM_PREAMBLE_TIME_HALF
197 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
198 } else {
199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
203 + (numSymbols * OFDM_SYMBOL_TIME);
204 }
205 break;
206 default:
Joe Perches38002762010-12-02 19:12:36 -0800207 ath_err(ath9k_hw_common(ah),
208 "Unknown phy %u (rate ix %u)\n", phy, rateix);
Sujithf1dc5602008-10-29 10:16:30 +0530209 txTime = 0;
210 break;
211 }
212
213 return txTime;
214}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400215EXPORT_SYMBOL(ath9k_hw_computetxtime);
Sujithf1dc5602008-10-29 10:16:30 +0530216
Sujithcbe61d82009-02-09 13:27:12 +0530217void ath9k_hw_get_channel_centers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530218 struct ath9k_channel *chan,
219 struct chan_centers *centers)
220{
221 int8_t extoff;
Sujithf1dc5602008-10-29 10:16:30 +0530222
223 if (!IS_CHAN_HT40(chan)) {
224 centers->ctl_center = centers->ext_center =
225 centers->synth_center = chan->channel;
226 return;
227 }
228
229 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
230 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
231 centers->synth_center =
232 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
233 extoff = 1;
234 } else {
235 centers->synth_center =
236 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
237 extoff = -1;
238 }
239
240 centers->ctl_center =
241 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700242 /* 25 MHz spacing is supported by hw but not on upper layers */
Sujithf1dc5602008-10-29 10:16:30 +0530243 centers->ext_center =
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700244 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
Sujithf1dc5602008-10-29 10:16:30 +0530245}
246
247/******************/
248/* Chip Revisions */
249/******************/
250
Sujithcbe61d82009-02-09 13:27:12 +0530251static void ath9k_hw_read_revisions(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530252{
253 u32 val;
254
255 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
256
257 if (val == 0xFF) {
258 val = REG_READ(ah, AR_SREV);
Sujithd535a422009-02-09 13:27:06 +0530259 ah->hw_version.macVersion =
260 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
261 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
Sujith2660b812009-02-09 13:27:26 +0530262 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
Sujithf1dc5602008-10-29 10:16:30 +0530263 } else {
264 if (!AR_SREV_9100(ah))
Sujithd535a422009-02-09 13:27:06 +0530265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
Sujithf1dc5602008-10-29 10:16:30 +0530266
Sujithd535a422009-02-09 13:27:06 +0530267 ah->hw_version.macRev = val & AR_SREV_REVISION;
Sujithf1dc5602008-10-29 10:16:30 +0530268
Sujithd535a422009-02-09 13:27:06 +0530269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
Sujith2660b812009-02-09 13:27:26 +0530270 ah->is_pciexpress = true;
Sujithf1dc5602008-10-29 10:16:30 +0530271 }
272}
273
Sujithf1dc5602008-10-29 10:16:30 +0530274/************************************/
275/* HW Attach, Detach, Init Routines */
276/************************************/
277
Sujithcbe61d82009-02-09 13:27:12 +0530278static void ath9k_hw_disablepcie(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530279{
Felix Fietkau040b74f2010-12-12 00:51:07 +0100280 if (!AR_SREV_5416(ah))
Sujithf1dc5602008-10-29 10:16:30 +0530281 return;
282
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
292
293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
294}
295
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400296/* This should work for all families including legacy */
Sujithcbe61d82009-02-09 13:27:12 +0530297static bool ath9k_hw_chip_test(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530298{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700299 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400300 u32 regAddr[2] = { AR_STA_ID0 };
Sujithf1dc5602008-10-29 10:16:30 +0530301 u32 regHold[2];
Joe Perches07b2fa52010-11-20 18:38:53 -0800302 static const u32 patternData[4] = {
303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
304 };
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400305 int i, j, loop_max;
Sujithf1dc5602008-10-29 10:16:30 +0530306
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400307 if (!AR_SREV_9300_20_OR_LATER(ah)) {
308 loop_max = 2;
309 regAddr[1] = AR_PHY_BASE + (8 << 2);
310 } else
311 loop_max = 1;
312
313 for (i = 0; i < loop_max; i++) {
Sujithf1dc5602008-10-29 10:16:30 +0530314 u32 addr = regAddr[i];
315 u32 wrData, rdData;
316
317 regHold[i] = REG_READ(ah, addr);
318 for (j = 0; j < 0x100; j++) {
319 wrData = (j << 16) | j;
320 REG_WRITE(ah, addr, wrData);
321 rdData = REG_READ(ah, addr);
322 if (rdData != wrData) {
Joe Perches38002762010-12-02 19:12:36 -0800323 ath_err(common,
324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
325 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530326 return false;
327 }
328 }
329 for (j = 0; j < 4; j++) {
330 wrData = patternData[j];
331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr);
333 if (wrData != rdData) {
Joe Perches38002762010-12-02 19:12:36 -0800334 ath_err(common,
335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
336 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530337 return false;
338 }
339 }
340 REG_WRITE(ah, regAddr[i], regHold[i]);
341 }
342 udelay(100);
Sujithcbe61d82009-02-09 13:27:12 +0530343
Sujithf1dc5602008-10-29 10:16:30 +0530344 return true;
345}
346
Luis R. Rodriguezb8b0f372009-08-03 12:24:43 -0700347static void ath9k_hw_init_config(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700348{
349 int i;
350
Sujith2660b812009-02-09 13:27:26 +0530351 ah->config.dma_beacon_response_time = 2;
352 ah->config.sw_beacon_response_time = 10;
353 ah->config.additional_swba_backoff = 0;
354 ah->config.ack_6mb = 0x0;
355 ah->config.cwm_ignore_extcca = 0;
356 ah->config.pcie_powersave_enable = 0;
Sujith2660b812009-02-09 13:27:26 +0530357 ah->config.pcie_clock_req = 0;
Sujith2660b812009-02-09 13:27:26 +0530358 ah->config.pcie_waen = 0;
359 ah->config.analog_shiftreg = 1;
Luis R. Rodriguez03c72512010-06-12 00:33:46 -0400360 ah->config.enable_ani = true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700361
362 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530363 ah->config.spurchans[i][0] = AR_NO_SPUR;
364 ah->config.spurchans[i][1] = AR_NO_SPUR;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700365 }
366
Luis R. Rodriguez5ffaf8a2010-02-02 11:58:33 -0500367 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
368 ah->config.ht_enable = 1;
369 else
370 ah->config.ht_enable = 0;
371
Sujith0ce024c2009-12-14 14:57:00 +0530372 ah->config.rx_intr_mitigation = true;
Luis R. Rodriguez6a0ec302010-06-21 18:38:49 -0400373 ah->config.pcieSerDesWrite = true;
Luis R. Rodriguez61584252009-03-12 18:18:49 -0400374
375 /*
376 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
377 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
378 * This means we use it for all AR5416 devices, and the few
379 * minor PCI AR9280 devices out there.
380 *
381 * Serialization is required because these devices do not handle
382 * well the case of two concurrent reads/writes due to the latency
383 * involved. During one read/write another read/write can be issued
384 * on another CPU while the previous read/write may still be working
385 * on our hardware, if we hit this case the hardware poops in a loop.
386 * We prevent this by serializing reads and writes.
387 *
388 * This issue is not present on PCI-Express devices or pre-AR5416
389 * devices (legacy, 802.11abg).
390 */
391 if (num_possible_cpus() > 1)
David S. Miller2d6a5e92009-03-17 15:01:30 -0700392 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700393}
394
Luis R. Rodriguez50aca252009-08-03 12:24:42 -0700395static void ath9k_hw_init_defaults(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700396{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700397 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
398
399 regulatory->country_code = CTRY_DEFAULT;
400 regulatory->power_limit = MAX_RATE_POWER;
401 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
402
Sujithd535a422009-02-09 13:27:06 +0530403 ah->hw_version.magic = AR5416_MAGIC;
Sujithd535a422009-02-09 13:27:06 +0530404 ah->hw_version.subvendorid = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700405
Sujith2660b812009-02-09 13:27:26 +0530406 ah->atim_window = 0;
Felix Fietkau16f24112010-06-12 17:22:32 +0200407 ah->sta_id1_defaults =
408 AR_STA_ID1_CRPT_MIC_ENABLE |
409 AR_STA_ID1_MCAST_KSRCH;
Sujith2660b812009-02-09 13:27:26 +0530410 ah->enable_32kHz_clock = DONT_USE_32KHZ;
Felix Fietkau4357c6b2010-12-13 08:40:50 +0100411 ah->slottime = 20;
Sujith2660b812009-02-09 13:27:26 +0530412 ah->globaltxtimeout = (u32) -1;
Gabor Juhoscbdec972009-07-24 17:27:22 +0200413 ah->power_mode = ATH9K_PM_UNDEFINED;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700414}
415
Sujithcbe61d82009-02-09 13:27:12 +0530416static int ath9k_hw_init_macaddr(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700417{
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700418 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530419 u32 sum;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700420 int i;
Sujithf1dc5602008-10-29 10:16:30 +0530421 u16 eeval;
Joe Perches07b2fa52010-11-20 18:38:53 -0800422 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700423
Sujithf1dc5602008-10-29 10:16:30 +0530424 sum = 0;
425 for (i = 0; i < 3; i++) {
Luis R. Rodriguez49101672010-04-15 17:39:13 -0400426 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530427 sum += eeval;
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700428 common->macaddr[2 * i] = eeval >> 8;
429 common->macaddr[2 * i + 1] = eeval & 0xff;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700430 }
Sujithd8baa932009-03-30 15:28:25 +0530431 if (sum == 0 || sum == 0xffff * 3)
Sujithf1dc5602008-10-29 10:16:30 +0530432 return -EADDRNOTAVAIL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700433
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700434 return 0;
435}
436
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700437static int ath9k_hw_post_init(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700438{
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530439 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700440 int ecode;
441
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530442 if (common->bus_ops->ath_bus_type != ATH_USB) {
Sujith527d4852010-03-17 14:25:16 +0530443 if (!ath9k_hw_chip_test(ah))
444 return -ENODEV;
445 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700446
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400447 if (!AR_SREV_9300_20_OR_LATER(ah)) {
448 ecode = ar9002_hw_rf_claim(ah);
449 if (ecode != 0)
450 return ecode;
451 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700452
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700453 ecode = ath9k_hw_eeprom_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700454 if (ecode != 0)
455 return ecode;
Sujith7d01b222009-03-13 08:55:55 +0530456
Joe Perches226afe62010-12-02 19:12:37 -0800457 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
458 "Eeprom VER: %d, REV: %d\n",
459 ah->eep_ops->get_eeprom_ver(ah),
460 ah->eep_ops->get_eeprom_rev(ah));
Sujith7d01b222009-03-13 08:55:55 +0530461
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400462 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
463 if (ecode) {
Joe Perches38002762010-12-02 19:12:36 -0800464 ath_err(ath9k_hw_common(ah),
465 "Failed allocating banks for external radio\n");
Rajkumar Manoharan48a7c3d2010-11-08 20:40:53 +0530466 ath9k_hw_rf_free_ext_banks(ah);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400467 return ecode;
Luis R. Rodriguez574d6b12009-10-19 02:33:37 -0400468 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700469
470 if (!AR_SREV_9100(ah)) {
471 ath9k_hw_ani_setup(ah);
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700472 ath9k_hw_ani_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700473 }
Sujithf1dc5602008-10-29 10:16:30 +0530474
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700475 return 0;
476}
477
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400478static void ath9k_hw_attach_ops(struct ath_hw *ah)
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700479{
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400480 if (AR_SREV_9300_20_OR_LATER(ah))
481 ar9003_hw_attach_ops(ah);
482 else
483 ar9002_hw_attach_ops(ah);
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700484}
485
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400486/* Called for all hardware families */
487static int __ath9k_hw_init(struct ath_hw *ah)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700488{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700489 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700490 int r = 0;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700491
Luis R. Rodriguezbab1f622010-04-15 17:38:20 -0400492 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
493 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700494
495 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
Joe Perches38002762010-12-02 19:12:36 -0800496 ath_err(common, "Couldn't reset chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700497 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700498 }
499
Luis R. Rodriguezbab1f622010-04-15 17:38:20 -0400500 ath9k_hw_init_defaults(ah);
501 ath9k_hw_init_config(ah);
502
Luis R. Rodriguez8525f282010-04-15 17:38:19 -0400503 ath9k_hw_attach_ops(ah);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400504
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -0700505 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
Joe Perches38002762010-12-02 19:12:36 -0800506 ath_err(common, "Couldn't wakeup chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700507 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700508 }
509
510 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
511 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
John W. Linville4c85ab12010-07-28 10:06:35 -0400512 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
513 !ah->is_pciexpress)) {
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700514 ah->config.serialize_regmode =
515 SER_REG_MODE_ON;
516 } else {
517 ah->config.serialize_regmode =
518 SER_REG_MODE_OFF;
519 }
520 }
521
Joe Perches226afe62010-12-02 19:12:37 -0800522 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700523 ah->config.serialize_regmode);
524
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -0500525 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
526 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
527 else
528 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
529
Felix Fietkau6da5a722010-12-12 00:51:12 +0100530 switch (ah->hw_version.macVersion) {
531 case AR_SREV_VERSION_5416_PCI:
532 case AR_SREV_VERSION_5416_PCIE:
533 case AR_SREV_VERSION_9160:
534 case AR_SREV_VERSION_9100:
535 case AR_SREV_VERSION_9280:
536 case AR_SREV_VERSION_9285:
537 case AR_SREV_VERSION_9287:
538 case AR_SREV_VERSION_9271:
539 case AR_SREV_VERSION_9300:
540 case AR_SREV_VERSION_9485:
541 break;
542 default:
Joe Perches38002762010-12-02 19:12:36 -0800543 ath_err(common,
544 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
545 ah->hw_version.macVersion, ah->hw_version.macRev);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700546 return -EOPNOTSUPP;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700547 }
548
Luis R. Rodriguez0df13da2010-04-15 17:38:59 -0400549 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400550 ah->is_pciexpress = false;
551
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700552 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700553 ath9k_hw_init_cal_settings(ah);
554
555 ah->ani_function = ATH9K_ANI_ALL;
Felix Fietkau7a370812010-09-22 12:34:52 +0200556 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700557 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -0400558 if (!AR_SREV_9300_20_OR_LATER(ah))
559 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700560
561 ath9k_hw_init_mode_regs(ah);
562
Luis R. Rodriguez5efa3a62010-05-07 18:23:22 -0400563 /*
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -0400564 * Read back AR_WA into a permanent copy and set bits 14 and 17.
565 * We need to do this to avoid RMW of this register. We cannot
566 * read the reg when chip is asleep.
567 */
568 ah->WARegVal = REG_READ(ah, AR_WA);
569 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
570 AR_WA_ASPM_TIMER_BASED_DISABLE);
571
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700572 if (ah->is_pciexpress)
Vivek Natarajan93b1b372009-09-17 09:24:58 +0530573 ath9k_hw_configpcipowersave(ah, 0, 0);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700574 else
575 ath9k_hw_disablepcie(ah);
576
Luis R. Rodriguezd8f492b2010-04-15 17:39:04 -0400577 if (!AR_SREV_9300_20_OR_LATER(ah))
578 ar9002_hw_cck_chan14_spread(ah);
Sujith193cd452009-09-18 15:04:07 +0530579
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700580 r = ath9k_hw_post_init(ah);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700581 if (r)
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700582 return r;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700583
584 ath9k_hw_init_mode_gain_regs(ah);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +0100585 r = ath9k_hw_fill_cap_info(ah);
586 if (r)
587 return r;
588
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700589 r = ath9k_hw_init_macaddr(ah);
590 if (r) {
Joe Perches38002762010-12-02 19:12:36 -0800591 ath_err(common, "Failed to initialize MAC address\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700592 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700593 }
594
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400595 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
Sujith2660b812009-02-09 13:27:26 +0530596 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700597 else
Sujith2660b812009-02-09 13:27:26 +0530598 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700599
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -0400600 ah->bb_watchdog_timeout_ms = 25;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700601
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400602 common->state = ATH_HW_INITIALIZED;
603
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700604 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700605}
606
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400607int ath9k_hw_init(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530608{
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400609 int ret;
610 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530611
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400612 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
613 switch (ah->hw_version.devid) {
614 case AR5416_DEVID_PCI:
615 case AR5416_DEVID_PCIE:
616 case AR5416_AR9100_DEVID:
617 case AR9160_DEVID_PCI:
618 case AR9280_DEVID_PCI:
619 case AR9280_DEVID_PCIE:
620 case AR9285_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400621 case AR9287_DEVID_PCI:
622 case AR9287_DEVID_PCIE:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400623 case AR2427_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400624 case AR9300_DEVID_PCIE:
Vasanthakumar Thiagarajan3050c912010-12-06 04:27:36 -0800625 case AR9300_DEVID_AR9485_PCIE:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400626 break;
627 default:
628 if (common->bus_ops->ath_bus_type == ATH_USB)
629 break;
Joe Perches38002762010-12-02 19:12:36 -0800630 ath_err(common, "Hardware device ID 0x%04x not supported\n",
631 ah->hw_version.devid);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400632 return -EOPNOTSUPP;
633 }
Sujithf1dc5602008-10-29 10:16:30 +0530634
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400635 ret = __ath9k_hw_init(ah);
636 if (ret) {
Joe Perches38002762010-12-02 19:12:36 -0800637 ath_err(common,
638 "Unable to initialize hardware; initialization status: %d\n",
639 ret);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400640 return ret;
641 }
Sujithf1dc5602008-10-29 10:16:30 +0530642
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400643 return 0;
Sujithf1dc5602008-10-29 10:16:30 +0530644}
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400645EXPORT_SYMBOL(ath9k_hw_init);
Sujithf1dc5602008-10-29 10:16:30 +0530646
Sujithcbe61d82009-02-09 13:27:12 +0530647static void ath9k_hw_init_qos(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530648{
Sujith7d0d0df2010-04-16 11:53:57 +0530649 ENABLE_REGWRITE_BUFFER(ah);
650
Sujithf1dc5602008-10-29 10:16:30 +0530651 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
652 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
653
654 REG_WRITE(ah, AR_QOS_NO_ACK,
655 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
656 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
657 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
658
659 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
660 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
661 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
662 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
663 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
Sujith7d0d0df2010-04-16 11:53:57 +0530664
665 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530666}
667
Sujithcbe61d82009-02-09 13:27:12 +0530668static void ath9k_hw_init_pll(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530669 struct ath9k_channel *chan)
670{
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800671 u32 pll;
672
673 if (AR_SREV_9485(ah))
674 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
675
676 pll = ath9k_hw_compute_pll_control(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +0530677
Gabor Juhosd03a66c2009-01-14 20:17:09 +0100678 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
Sujithf1dc5602008-10-29 10:16:30 +0530679
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400680 /* Switch the core clock for ar9271 to 117Mhz */
681 if (AR_SREV_9271(ah)) {
Sujith25e2ab12010-03-17 14:25:22 +0530682 udelay(500);
683 REG_WRITE(ah, 0x50040, 0x304);
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400684 }
685
Sujithf1dc5602008-10-29 10:16:30 +0530686 udelay(RTC_PLL_SETTLE_DELAY);
687
688 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
689}
690
Sujithcbe61d82009-02-09 13:27:12 +0530691static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
Colin McCabed97809d2008-12-01 13:38:55 -0800692 enum nl80211_iftype opmode)
Sujithf1dc5602008-10-29 10:16:30 +0530693{
Pavel Roskin152d5302010-03-31 18:05:37 -0400694 u32 imr_reg = AR_IMR_TXERR |
Sujithf1dc5602008-10-29 10:16:30 +0530695 AR_IMR_TXURN |
696 AR_IMR_RXERR |
697 AR_IMR_RXORN |
698 AR_IMR_BCNMISC;
699
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400700 if (AR_SREV_9300_20_OR_LATER(ah)) {
701 imr_reg |= AR_IMR_RXOK_HP;
702 if (ah->config.rx_intr_mitigation)
703 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
704 else
705 imr_reg |= AR_IMR_RXOK_LP;
Sujithf1dc5602008-10-29 10:16:30 +0530706
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400707 } else {
708 if (ah->config.rx_intr_mitigation)
709 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
710 else
711 imr_reg |= AR_IMR_RXOK;
712 }
713
714 if (ah->config.tx_intr_mitigation)
715 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
716 else
717 imr_reg |= AR_IMR_TXOK;
Sujithf1dc5602008-10-29 10:16:30 +0530718
Colin McCabed97809d2008-12-01 13:38:55 -0800719 if (opmode == NL80211_IFTYPE_AP)
Pavel Roskin152d5302010-03-31 18:05:37 -0400720 imr_reg |= AR_IMR_MIB;
Sujithf1dc5602008-10-29 10:16:30 +0530721
Sujith7d0d0df2010-04-16 11:53:57 +0530722 ENABLE_REGWRITE_BUFFER(ah);
723
Pavel Roskin152d5302010-03-31 18:05:37 -0400724 REG_WRITE(ah, AR_IMR, imr_reg);
Pavel Roskin74bad5c2010-02-23 18:15:27 -0500725 ah->imrs2_reg |= AR_IMR_S2_GTT;
726 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
Sujithf1dc5602008-10-29 10:16:30 +0530727
728 if (!AR_SREV_9100(ah)) {
729 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
730 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
731 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
732 }
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400733
Sujith7d0d0df2010-04-16 11:53:57 +0530734 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530735
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400736 if (AR_SREV_9300_20_OR_LATER(ah)) {
737 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
738 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
739 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
740 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
741 }
Sujithf1dc5602008-10-29 10:16:30 +0530742}
743
Felix Fietkau0005baf2010-01-15 02:33:40 +0100744static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +0530745{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100746 u32 val = ath9k_hw_mac_to_clks(ah, us);
747 val = min(val, (u32) 0xFFFF);
748 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
Sujithf1dc5602008-10-29 10:16:30 +0530749}
750
Felix Fietkau0005baf2010-01-15 02:33:40 +0100751static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +0530752{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100753 u32 val = ath9k_hw_mac_to_clks(ah, us);
754 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
755 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
756}
757
758static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
759{
760 u32 val = ath9k_hw_mac_to_clks(ah, us);
761 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
762 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
Sujithf1dc5602008-10-29 10:16:30 +0530763}
764
Sujithcbe61d82009-02-09 13:27:12 +0530765static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
Sujithf1dc5602008-10-29 10:16:30 +0530766{
Sujithf1dc5602008-10-29 10:16:30 +0530767 if (tu > 0xFFFF) {
Joe Perches226afe62010-12-02 19:12:37 -0800768 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
769 "bad global tx timeout %u\n", tu);
Sujith2660b812009-02-09 13:27:26 +0530770 ah->globaltxtimeout = (u32) -1;
Sujithf1dc5602008-10-29 10:16:30 +0530771 return false;
772 } else {
773 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
Sujith2660b812009-02-09 13:27:26 +0530774 ah->globaltxtimeout = tu;
Sujithf1dc5602008-10-29 10:16:30 +0530775 return true;
776 }
777}
778
Felix Fietkau0005baf2010-01-15 02:33:40 +0100779void ath9k_hw_init_global_settings(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530780{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100781 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
782 int acktimeout;
Felix Fietkaue239d852010-01-15 02:34:58 +0100783 int slottime;
Felix Fietkau0005baf2010-01-15 02:33:40 +0100784 int sifstime;
785
Joe Perches226afe62010-12-02 19:12:37 -0800786 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
787 ah->misc_mode);
Sujithf1dc5602008-10-29 10:16:30 +0530788
Sujith2660b812009-02-09 13:27:26 +0530789 if (ah->misc_mode != 0)
Sujithf1dc5602008-10-29 10:16:30 +0530790 REG_WRITE(ah, AR_PCU_MISC,
Sujith2660b812009-02-09 13:27:26 +0530791 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
Felix Fietkau0005baf2010-01-15 02:33:40 +0100792
793 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
794 sifstime = 16;
795 else
796 sifstime = 10;
797
Felix Fietkaue239d852010-01-15 02:34:58 +0100798 /* As defined by IEEE 802.11-2007 17.3.8.6 */
799 slottime = ah->slottime + 3 * ah->coverage_class;
800 acktimeout = slottime + sifstime;
Felix Fietkau42c45682010-02-11 18:07:19 +0100801
802 /*
803 * Workaround for early ACK timeouts, add an offset to match the
804 * initval's 64us ack timeout value.
805 * This was initially only meant to work around an issue with delayed
806 * BA frames in some implementations, but it has been found to fix ACK
807 * timeout issues in other cases as well.
808 */
809 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
810 acktimeout += 64 - sifstime - ah->slottime;
811
Felix Fietkaucaabf2b2010-12-13 08:40:51 +0100812 ath9k_hw_setslottime(ah, ah->slottime);
Felix Fietkau0005baf2010-01-15 02:33:40 +0100813 ath9k_hw_set_ack_timeout(ah, acktimeout);
814 ath9k_hw_set_cts_timeout(ah, acktimeout);
Sujith2660b812009-02-09 13:27:26 +0530815 if (ah->globaltxtimeout != (u32) -1)
816 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
Sujithf1dc5602008-10-29 10:16:30 +0530817}
Felix Fietkau0005baf2010-01-15 02:33:40 +0100818EXPORT_SYMBOL(ath9k_hw_init_global_settings);
Sujithf1dc5602008-10-29 10:16:30 +0530819
Sujith285f2dd2010-01-08 10:36:07 +0530820void ath9k_hw_deinit(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700821{
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400822 struct ath_common *common = ath9k_hw_common(ah);
823
Sujith736b3a22010-03-17 14:25:24 +0530824 if (common->state < ATH_HW_INITIALIZED)
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400825 goto free_hw;
826
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -0700827 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400828
829free_hw:
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400830 ath9k_hw_rf_free_ext_banks(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700831}
Sujith285f2dd2010-01-08 10:36:07 +0530832EXPORT_SYMBOL(ath9k_hw_deinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700833
Sujithf1dc5602008-10-29 10:16:30 +0530834/*******/
835/* INI */
836/*******/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700837
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400838u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Bob Copeland3a702e42009-03-30 22:30:29 -0400839{
840 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
841
842 if (IS_CHAN_B(chan))
843 ctl |= CTL_11B;
844 else if (IS_CHAN_G(chan))
845 ctl |= CTL_11G;
846 else
847 ctl |= CTL_11A;
848
849 return ctl;
850}
851
Sujithf1dc5602008-10-29 10:16:30 +0530852/****************************************/
853/* Reset and Channel Switching Routines */
854/****************************************/
855
Sujithcbe61d82009-02-09 13:27:12 +0530856static inline void ath9k_hw_set_dma(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530857{
Felix Fietkau57b32222010-04-15 17:39:22 -0400858 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530859 u32 regval;
860
Sujith7d0d0df2010-04-16 11:53:57 +0530861 ENABLE_REGWRITE_BUFFER(ah);
862
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400863 /*
864 * set AHB_MODE not to do cacheline prefetches
865 */
Felix Fietkau57b32222010-04-15 17:39:22 -0400866 if (!AR_SREV_9300_20_OR_LATER(ah)) {
867 regval = REG_READ(ah, AR_AHB_MODE);
868 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
869 }
Sujithf1dc5602008-10-29 10:16:30 +0530870
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400871 /*
872 * let mac dma reads be in 128 byte chunks
873 */
Sujithf1dc5602008-10-29 10:16:30 +0530874 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
875 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
876
Sujith7d0d0df2010-04-16 11:53:57 +0530877 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530878
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400879 /*
880 * Restore TX Trigger Level to its pre-reset value.
881 * The initial value depends on whether aggregation is enabled, and is
882 * adjusted whenever underruns are detected.
883 */
Felix Fietkau57b32222010-04-15 17:39:22 -0400884 if (!AR_SREV_9300_20_OR_LATER(ah))
885 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
Sujithf1dc5602008-10-29 10:16:30 +0530886
Sujith7d0d0df2010-04-16 11:53:57 +0530887 ENABLE_REGWRITE_BUFFER(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530888
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400889 /*
890 * let mac dma writes be in 128 byte chunks
891 */
Sujithf1dc5602008-10-29 10:16:30 +0530892 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
893 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
894
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400895 /*
896 * Setup receive FIFO threshold to hold off TX activities
897 */
Sujithf1dc5602008-10-29 10:16:30 +0530898 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
899
Felix Fietkau57b32222010-04-15 17:39:22 -0400900 if (AR_SREV_9300_20_OR_LATER(ah)) {
901 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
902 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
903
904 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
905 ah->caps.rx_status_len);
906 }
907
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400908 /*
909 * reduce the number of usable entries in PCU TXBUF to avoid
910 * wrap around issues.
911 */
Sujithf1dc5602008-10-29 10:16:30 +0530912 if (AR_SREV_9285(ah)) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400913 /* For AR9285 the number of Fifos are reduced to half.
914 * So set the usable tx buf size also to half to
915 * avoid data/delimiter underruns
916 */
Sujithf1dc5602008-10-29 10:16:30 +0530917 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
918 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400919 } else if (!AR_SREV_9271(ah)) {
Sujithf1dc5602008-10-29 10:16:30 +0530920 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
921 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
922 }
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -0400923
Sujith7d0d0df2010-04-16 11:53:57 +0530924 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530925
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -0400926 if (AR_SREV_9300_20_OR_LATER(ah))
927 ath9k_hw_reset_txstatus_ring(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530928}
929
Sujithcbe61d82009-02-09 13:27:12 +0530930static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
Sujithf1dc5602008-10-29 10:16:30 +0530931{
932 u32 val;
933
934 val = REG_READ(ah, AR_STA_ID1);
935 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
936 switch (opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -0800937 case NL80211_IFTYPE_AP:
Sujithf1dc5602008-10-29 10:16:30 +0530938 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
939 | AR_STA_ID1_KSRCH_MODE);
940 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
941 break;
Colin McCabed97809d2008-12-01 13:38:55 -0800942 case NL80211_IFTYPE_ADHOC:
Pat Erley9cb54122009-03-20 22:59:59 -0400943 case NL80211_IFTYPE_MESH_POINT:
Sujithf1dc5602008-10-29 10:16:30 +0530944 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
945 | AR_STA_ID1_KSRCH_MODE);
946 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
947 break;
Colin McCabed97809d2008-12-01 13:38:55 -0800948 case NL80211_IFTYPE_STATION:
Sujithf1dc5602008-10-29 10:16:30 +0530949 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
950 break;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +0530951 default:
952 if (ah->is_monitoring)
953 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
954 break;
Sujithf1dc5602008-10-29 10:16:30 +0530955 }
956}
957
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400958void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
959 u32 *coef_mantissa, u32 *coef_exponent)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700960{
961 u32 coef_exp, coef_man;
962
963 for (coef_exp = 31; coef_exp > 0; coef_exp--)
964 if ((coef_scaled >> coef_exp) & 0x1)
965 break;
966
967 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
968
969 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
970
971 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
972 *coef_exponent = coef_exp - 16;
973}
974
Sujithcbe61d82009-02-09 13:27:12 +0530975static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
Sujithf1dc5602008-10-29 10:16:30 +0530976{
977 u32 rst_flags;
978 u32 tmpReg;
979
Sujith70768492009-02-16 13:23:12 +0530980 if (AR_SREV_9100(ah)) {
981 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
982 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
983 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
984 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
985 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
986 }
987
Sujith7d0d0df2010-04-16 11:53:57 +0530988 ENABLE_REGWRITE_BUFFER(ah);
989
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -0400990 if (AR_SREV_9300_20_OR_LATER(ah)) {
991 REG_WRITE(ah, AR_WA, ah->WARegVal);
992 udelay(10);
993 }
994
Sujithf1dc5602008-10-29 10:16:30 +0530995 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
996 AR_RTC_FORCE_WAKE_ON_INT);
997
998 if (AR_SREV_9100(ah)) {
999 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1000 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1001 } else {
1002 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1003 if (tmpReg &
1004 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1005 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001006 u32 val;
Sujithf1dc5602008-10-29 10:16:30 +05301007 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001008
1009 val = AR_RC_HOSTIF;
1010 if (!AR_SREV_9300_20_OR_LATER(ah))
1011 val |= AR_RC_AHB;
1012 REG_WRITE(ah, AR_RC, val);
1013
1014 } else if (!AR_SREV_9300_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301015 REG_WRITE(ah, AR_RC, AR_RC_AHB);
Sujithf1dc5602008-10-29 10:16:30 +05301016
1017 rst_flags = AR_RTC_RC_MAC_WARM;
1018 if (type == ATH9K_RESET_COLD)
1019 rst_flags |= AR_RTC_RC_MAC_COLD;
1020 }
1021
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001022 REG_WRITE(ah, AR_RTC_RC, rst_flags);
Sujith7d0d0df2010-04-16 11:53:57 +05301023
1024 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301025
Sujithf1dc5602008-10-29 10:16:30 +05301026 udelay(50);
1027
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001028 REG_WRITE(ah, AR_RTC_RC, 0);
Sujith0caa7b12009-02-16 13:23:20 +05301029 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
Joe Perches226afe62010-12-02 19:12:37 -08001030 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1031 "RTC stuck in MAC reset\n");
Sujithf1dc5602008-10-29 10:16:30 +05301032 return false;
1033 }
1034
1035 if (!AR_SREV_9100(ah))
1036 REG_WRITE(ah, AR_RC, 0);
1037
Sujithf1dc5602008-10-29 10:16:30 +05301038 if (AR_SREV_9100(ah))
1039 udelay(50);
1040
1041 return true;
1042}
1043
Sujithcbe61d82009-02-09 13:27:12 +05301044static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301045{
Sujith7d0d0df2010-04-16 11:53:57 +05301046 ENABLE_REGWRITE_BUFFER(ah);
1047
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001048 if (AR_SREV_9300_20_OR_LATER(ah)) {
1049 REG_WRITE(ah, AR_WA, ah->WARegVal);
1050 udelay(10);
1051 }
1052
Sujithf1dc5602008-10-29 10:16:30 +05301053 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1054 AR_RTC_FORCE_WAKE_ON_INT);
1055
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001056 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301057 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1058
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001059 REG_WRITE(ah, AR_RTC_RESET, 0);
Luis R. Rodriguezee031112010-06-21 18:38:51 -04001060 udelay(2);
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301061
Sujith7d0d0df2010-04-16 11:53:57 +05301062 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301063
Senthil Balasubramanian84e21692010-04-15 17:38:30 -04001064 if (!AR_SREV_9300_20_OR_LATER(ah))
1065 udelay(2);
1066
1067 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301068 REG_WRITE(ah, AR_RC, 0);
1069
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001070 REG_WRITE(ah, AR_RTC_RESET, 1);
Sujithf1dc5602008-10-29 10:16:30 +05301071
1072 if (!ath9k_hw_wait(ah,
1073 AR_RTC_STATUS,
1074 AR_RTC_STATUS_M,
Sujith0caa7b12009-02-16 13:23:20 +05301075 AR_RTC_STATUS_ON,
1076 AH_WAIT_TIMEOUT)) {
Joe Perches226afe62010-12-02 19:12:37 -08001077 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1078 "RTC not waking up\n");
Sujithf1dc5602008-10-29 10:16:30 +05301079 return false;
1080 }
1081
1082 ath9k_hw_read_revisions(ah);
1083
1084 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1085}
1086
Sujithcbe61d82009-02-09 13:27:12 +05301087static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Sujithf1dc5602008-10-29 10:16:30 +05301088{
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001089 if (AR_SREV_9300_20_OR_LATER(ah)) {
1090 REG_WRITE(ah, AR_WA, ah->WARegVal);
1091 udelay(10);
1092 }
1093
Sujithf1dc5602008-10-29 10:16:30 +05301094 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1095 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1096
1097 switch (type) {
1098 case ATH9K_RESET_POWER_ON:
1099 return ath9k_hw_set_reset_power_on(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301100 case ATH9K_RESET_WARM:
1101 case ATH9K_RESET_COLD:
1102 return ath9k_hw_set_reset(ah, type);
Sujithf1dc5602008-10-29 10:16:30 +05301103 default:
1104 return false;
1105 }
1106}
1107
Sujithcbe61d82009-02-09 13:27:12 +05301108static bool ath9k_hw_chip_reset(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301109 struct ath9k_channel *chan)
1110{
Vivek Natarajan42abfbe2009-09-17 09:27:59 +05301111 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +05301112 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1113 return false;
1114 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
Sujithf1dc5602008-10-29 10:16:30 +05301115 return false;
1116
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001117 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05301118 return false;
1119
Sujith2660b812009-02-09 13:27:26 +05301120 ah->chip_fullsleep = false;
Sujithf1dc5602008-10-29 10:16:30 +05301121 ath9k_hw_init_pll(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301122 ath9k_hw_set_rfmode(ah, chan);
1123
1124 return true;
1125}
1126
Sujithcbe61d82009-02-09 13:27:12 +05301127static bool ath9k_hw_channel_change(struct ath_hw *ah,
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001128 struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301129{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001130 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001131 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001132 struct ieee80211_channel *channel = chan->chan;
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001133 u32 qnum;
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001134 int r;
Sujithf1dc5602008-10-29 10:16:30 +05301135
1136 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1137 if (ath9k_hw_numtxpending(ah, qnum)) {
Joe Perches226afe62010-12-02 19:12:37 -08001138 ath_dbg(common, ATH_DBG_QUEUE,
1139 "Transmit frames pending on queue %d\n", qnum);
Sujithf1dc5602008-10-29 10:16:30 +05301140 return false;
1141 }
1142 }
1143
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001144 if (!ath9k_hw_rfbus_req(ah)) {
Joe Perches38002762010-12-02 19:12:36 -08001145 ath_err(common, "Could not kill baseband RX\n");
Sujithf1dc5602008-10-29 10:16:30 +05301146 return false;
1147 }
1148
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001149 ath9k_hw_set_channel_regs(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301150
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001151 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001152 if (r) {
Joe Perches38002762010-12-02 19:12:36 -08001153 ath_err(common, "Failed to set channel\n");
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001154 return false;
Sujithf1dc5602008-10-29 10:16:30 +05301155 }
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001156 ath9k_hw_set_clockrate(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301157
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07001158 ah->eep_ops->set_txpower(ah, chan,
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001159 ath9k_regd_get_ctl(regulatory, chan),
Sujithf74df6f2009-02-09 13:27:24 +05301160 channel->max_antenna_gain * 2,
1161 channel->max_power * 2,
1162 min((u32) MAX_RATE_POWER,
Felix Fietkaude40f312010-10-20 03:08:53 +02001163 (u32) regulatory->power_limit), false);
Sujithf1dc5602008-10-29 10:16:30 +05301164
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001165 ath9k_hw_rfbus_done(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301166
1167 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1168 ath9k_hw_set_delta_slope(ah, chan);
1169
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001170 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301171
Sujithf1dc5602008-10-29 10:16:30 +05301172 return true;
1173}
1174
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001175bool ath9k_hw_check_alive(struct ath_hw *ah)
Johannes Berg3b319aa2009-06-13 14:50:26 +05301176{
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001177 int count = 50;
1178 u32 reg;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301179
Felix Fietkaue17f83e2010-09-22 12:34:53 +02001180 if (AR_SREV_9285_12_OR_LATER(ah))
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001181 return true;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301182
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001183 do {
1184 reg = REG_READ(ah, AR_OBS_BUS_1);
1185
1186 if ((reg & 0x7E7FFFEF) == 0x00702400)
1187 continue;
1188
1189 switch (reg & 0x7E000B00) {
1190 case 0x1E000000:
1191 case 0x52000B00:
1192 case 0x18000B00:
1193 continue;
1194 default:
1195 return true;
1196 }
1197 } while (count-- > 0);
1198
1199 return false;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301200}
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001201EXPORT_SYMBOL(ath9k_hw_check_alive);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301202
Sujithcbe61d82009-02-09 13:27:12 +05301203int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001204 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001205{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001206 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001207 u32 saveLedState;
Sujith2660b812009-02-09 13:27:26 +05301208 struct ath9k_channel *curchan = ah->curchan;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001209 u32 saveDefAntenna;
1210 u32 macStaId1;
Sujith46fe7822009-09-17 09:25:25 +05301211 u64 tsf = 0;
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001212 int i, r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001213
Luis R. Rodriguez43c27612009-09-13 21:07:07 -07001214 ah->txchainmask = common->tx_chainmask;
1215 ah->rxchainmask = common->rx_chainmask;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001216
Sujith Manoharan6d501922011-01-04 13:43:39 +05301217 if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) {
Vasanthakumar Thiagarajan9b9cc612010-04-15 17:39:41 -04001218 ath9k_hw_abortpcurecv(ah);
Felix Fietkau9cc2f3e2010-07-11 12:48:42 +02001219 if (!ath9k_hw_stopdmarecv(ah)) {
Joe Perches226afe62010-12-02 19:12:37 -08001220 ath_dbg(common, ATH_DBG_XMIT,
Vasanthakumar Thiagarajan9b9cc612010-04-15 17:39:41 -04001221 "Failed to stop receive dma\n");
Felix Fietkau9cc2f3e2010-07-11 12:48:42 +02001222 bChannelChange = false;
1223 }
Vasanthakumar Thiagarajan9b9cc612010-04-15 17:39:41 -04001224 }
1225
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001226 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001227 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001228
Felix Fietkaud9891c72010-09-29 17:15:27 +02001229 if (curchan && !ah->chip_fullsleep)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001230 ath9k_hw_getnf(ah, curchan);
1231
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001232 ah->caldata = caldata;
1233 if (caldata &&
1234 (chan->channel != caldata->channel ||
1235 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1236 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1237 /* Operating channel changed, reset channel calibration data */
1238 memset(caldata, 0, sizeof(*caldata));
1239 ath9k_init_nfcal_hist_buffer(ah, chan);
1240 }
1241
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001242 if (bChannelChange &&
Sujith2660b812009-02-09 13:27:26 +05301243 (ah->chip_fullsleep != true) &&
1244 (ah->curchan != NULL) &&
1245 (chan->channel != ah->curchan->channel) &&
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001246 ((chan->channelFlags & CHANNEL_ALL) ==
Sujith2660b812009-02-09 13:27:26 +05301247 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
Rajkumar Manoharan58d7e0f2010-09-08 15:57:12 +05301248 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001249
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001250 if (ath9k_hw_channel_change(ah, chan)) {
Sujith2660b812009-02-09 13:27:26 +05301251 ath9k_hw_loadnf(ah, ah->curchan);
Felix Fietkau00c86592010-07-30 21:02:09 +02001252 ath9k_hw_start_nfcal(ah, true);
Rajkumar Manoharanc2ba3342010-09-03 16:00:00 +05301253 if (AR_SREV_9271(ah))
1254 ar9002_hw_load_ani_reg(ah, chan);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001255 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001256 }
1257 }
1258
1259 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1260 if (saveDefAntenna == 0)
1261 saveDefAntenna = 1;
1262
1263 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1264
Sujith46fe7822009-09-17 09:25:25 +05301265 /* For chips on which RTC reset is done, save TSF before it gets cleared */
Felix Fietkauf860d522010-06-30 02:07:48 +02001266 if (AR_SREV_9100(ah) ||
1267 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
Sujith46fe7822009-09-17 09:25:25 +05301268 tsf = ath9k_hw_gettsf64(ah);
1269
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001270 saveLedState = REG_READ(ah, AR_CFG_LED) &
1271 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1272 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1273
1274 ath9k_hw_mark_phy_inactive(ah);
1275
Vasanthakumar Thiagarajan45ef6a0b2010-12-15 07:30:53 -08001276 ah->paprd_table_write_done = false;
1277
Sujith05020d22010-03-17 14:25:23 +05301278 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001279 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1280 REG_WRITE(ah,
1281 AR9271_RESET_POWER_DOWN_CONTROL,
1282 AR9271_RADIO_RF_RST);
1283 udelay(50);
1284 }
1285
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001286 if (!ath9k_hw_chip_reset(ah, chan)) {
Joe Perches38002762010-12-02 19:12:36 -08001287 ath_err(common, "Chip reset failed\n");
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001288 return -EINVAL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001289 }
1290
Sujith05020d22010-03-17 14:25:23 +05301291 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001292 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1293 ah->htc_reset_init = false;
1294 REG_WRITE(ah,
1295 AR9271_RESET_POWER_DOWN_CONTROL,
1296 AR9271_GATE_MAC_CTL);
1297 udelay(50);
1298 }
1299
Sujith46fe7822009-09-17 09:25:25 +05301300 /* Restore TSF */
Felix Fietkauf860d522010-06-30 02:07:48 +02001301 if (tsf)
Sujith46fe7822009-09-17 09:25:25 +05301302 ath9k_hw_settsf64(ah, tsf);
1303
Felix Fietkau7a370812010-09-22 12:34:52 +02001304 if (AR_SREV_9280_20_OR_LATER(ah))
Vasanthakumar Thiagarajan369391d2009-01-21 19:24:13 +05301305 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001306
Sujithe9141f72010-06-01 15:14:10 +05301307 if (!AR_SREV_9300_20_OR_LATER(ah))
1308 ar9002_hw_enable_async_fifo(ah);
1309
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001310 r = ath9k_hw_process_ini(ah, chan);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001311 if (r)
1312 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001313
Felix Fietkauf860d522010-06-30 02:07:48 +02001314 /*
1315 * Some AR91xx SoC devices frequently fail to accept TSF writes
1316 * right after the chip reset. When that happens, write a new
1317 * value after the initvals have been applied, with an offset
1318 * based on measured time difference
1319 */
1320 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1321 tsf += 1500;
1322 ath9k_hw_settsf64(ah, tsf);
1323 }
1324
Jouni Malinen0ced0e12009-01-08 13:32:13 +02001325 /* Setup MFP options for CCMP */
1326 if (AR_SREV_9280_20_OR_LATER(ah)) {
1327 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1328 * frames when constructing CCMP AAD. */
1329 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1330 0xc7ff);
1331 ah->sw_mgmt_crypto = false;
1332 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1333 /* Disable hardware crypto for management frames */
1334 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1335 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1336 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1337 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1338 ah->sw_mgmt_crypto = true;
1339 } else
1340 ah->sw_mgmt_crypto = true;
1341
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001342 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1343 ath9k_hw_set_delta_slope(ah, chan);
1344
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001345 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithd6509152009-03-13 08:56:05 +05301346 ah->eep_ops->set_board_values(ah, chan);
Luis R. Rodrigueza7765822009-10-19 02:33:45 -04001347
Sujith6819d572010-04-16 11:53:56 +05301348 ath9k_hw_set_operating_mode(ah, ah->opmode);
1349
Sujith7d0d0df2010-04-16 11:53:57 +05301350 ENABLE_REGWRITE_BUFFER(ah);
1351
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001352 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1353 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001354 | macStaId1
1355 | AR_STA_ID1_RTS_USE_DEF
Sujith2660b812009-02-09 13:27:26 +05301356 | (ah->config.
Sujith60b67f52008-08-07 10:52:38 +05301357 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
Sujith2660b812009-02-09 13:27:26 +05301358 | ah->sta_id1_defaults);
Luis R. Rodriguez13b81552009-09-10 17:52:45 -07001359 ath_hw_setbssidmask(common);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001360 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
Luis R. Rodriguez3453ad82009-09-10 08:57:00 -07001361 ath9k_hw_write_associd(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001362 REG_WRITE(ah, AR_ISR, ~0);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001363 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1364
Sujith7d0d0df2010-04-16 11:53:57 +05301365 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301366
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001367 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001368 if (r)
1369 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001370
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001371 ath9k_hw_set_clockrate(ah);
1372
Sujith7d0d0df2010-04-16 11:53:57 +05301373 ENABLE_REGWRITE_BUFFER(ah);
1374
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001375 for (i = 0; i < AR_NUM_DCU; i++)
1376 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1377
Sujith7d0d0df2010-04-16 11:53:57 +05301378 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301379
Sujith2660b812009-02-09 13:27:26 +05301380 ah->intr_txqs = 0;
1381 for (i = 0; i < ah->caps.total_queues; i++)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001382 ath9k_hw_resettxqueue(ah, i);
1383
Sujith2660b812009-02-09 13:27:26 +05301384 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -04001385 ath9k_hw_ani_cache_ini_regs(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001386 ath9k_hw_init_qos(ah);
1387
Sujith2660b812009-02-09 13:27:26 +05301388 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Felix Fietkau55821322010-12-17 00:57:01 +01001389 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301390
Felix Fietkau0005baf2010-01-15 02:33:40 +01001391 ath9k_hw_init_global_settings(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001392
Luis R. Rodriguez6c94fdc2010-04-15 17:39:24 -04001393 if (!AR_SREV_9300_20_OR_LATER(ah)) {
Sujithe9141f72010-06-01 15:14:10 +05301394 ar9002_hw_update_async_fifo(ah);
Luis R. Rodriguez6c94fdc2010-04-15 17:39:24 -04001395 ar9002_hw_enable_wep_aggregation(ah);
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301396 }
1397
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001398 REG_WRITE(ah, AR_STA_ID1,
1399 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1400
1401 ath9k_hw_set_dma(ah);
1402
1403 REG_WRITE(ah, AR_OBS, 8);
1404
Sujith0ce024c2009-12-14 14:57:00 +05301405 if (ah->config.rx_intr_mitigation) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001406 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1407 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1408 }
1409
Vasanthakumar Thiagarajan7f62a132010-04-15 17:39:19 -04001410 if (ah->config.tx_intr_mitigation) {
1411 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1412 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1413 }
1414
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001415 ath9k_hw_init_bb(ah, chan);
1416
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001417 if (!ath9k_hw_init_cal(ah, chan))
Joe Perches6badaaf2009-06-28 09:26:32 -07001418 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001419
Sujith7d0d0df2010-04-16 11:53:57 +05301420 ENABLE_REGWRITE_BUFFER(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001421
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001422 ath9k_hw_restore_chainmask(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001423 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1424
Sujith7d0d0df2010-04-16 11:53:57 +05301425 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301426
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001427 /*
1428 * For big endian systems turn on swapping for descriptors
1429 */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001430 if (AR_SREV_9100(ah)) {
1431 u32 mask;
1432 mask = REG_READ(ah, AR_CFG);
1433 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
Joe Perches226afe62010-12-02 19:12:37 -08001434 ath_dbg(common, ATH_DBG_RESET,
Sujith04bd4632008-11-28 22:18:05 +05301435 "CFG Byte Swap Set 0x%x\n", mask);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001436 } else {
1437 mask =
1438 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1439 REG_WRITE(ah, AR_CFG, mask);
Joe Perches226afe62010-12-02 19:12:37 -08001440 ath_dbg(common, ATH_DBG_RESET,
Sujith04bd4632008-11-28 22:18:05 +05301441 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001442 }
1443 } else {
Sujithcbba8cd2010-06-02 15:53:31 +05301444 if (common->bus_ops->ath_bus_type == ATH_USB) {
1445 /* Configure AR9271 target WLAN */
1446 if (AR_SREV_9271(ah))
1447 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1448 else
1449 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1450 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001451#ifdef __BIG_ENDIAN
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001452 else
1453 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001454#endif
1455 }
1456
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07001457 if (ah->btcoex_hw.enabled)
Vasanthakumar Thiagarajan42cc41e2009-08-26 21:08:45 +05301458 ath9k_hw_btcoex_enable(ah);
1459
Felix Fietkau00c86592010-07-30 21:02:09 +02001460 if (AR_SREV_9300_20_OR_LATER(ah))
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -04001461 ar9003_hw_bb_watchdog_config(ah);
Vasanthakumar Thiagarajand8903a52010-04-15 17:39:25 -04001462
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001463 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001464}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04001465EXPORT_SYMBOL(ath9k_hw_reset);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001466
Sujithf1dc5602008-10-29 10:16:30 +05301467/******************************/
1468/* Power Management (Chipset) */
1469/******************************/
1470
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001471/*
1472 * Notify Power Mgt is disabled in self-generated frames.
1473 * If requested, force chip to sleep.
1474 */
Sujithcbe61d82009-02-09 13:27:12 +05301475static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
Sujithf1dc5602008-10-29 10:16:30 +05301476{
1477 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1478 if (setChip) {
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001479 /*
1480 * Clear the RTC force wake bit to allow the
1481 * mac to go to sleep.
1482 */
Sujithf1dc5602008-10-29 10:16:30 +05301483 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1484 AR_RTC_FORCE_WAKE_EN);
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001485 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301486 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1487
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001488 /* Shutdown chip. Active low */
Sujith14b3af32010-03-17 14:25:18 +05301489 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
Sujith4921be82009-09-18 15:04:27 +05301490 REG_CLR_BIT(ah, (AR_RTC_RESET),
1491 AR_RTC_RESET_EN);
Sujithf1dc5602008-10-29 10:16:30 +05301492 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001493
1494 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1495 if (AR_SREV_9300_20_OR_LATER(ah))
1496 REG_WRITE(ah, AR_WA,
1497 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001498}
1499
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04001500/*
1501 * Notify Power Management is enabled in self-generating
1502 * frames. If request, set power mode of chip to
1503 * auto/normal. Duration in units of 128us (1/8 TU).
1504 */
Sujithcbe61d82009-02-09 13:27:12 +05301505static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001506{
Sujithf1dc5602008-10-29 10:16:30 +05301507 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1508 if (setChip) {
Sujith2660b812009-02-09 13:27:26 +05301509 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001510
Sujithf1dc5602008-10-29 10:16:30 +05301511 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04001512 /* Set WakeOnInterrupt bit; clear ForceWake bit */
Sujithf1dc5602008-10-29 10:16:30 +05301513 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1514 AR_RTC_FORCE_WAKE_ON_INT);
1515 } else {
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04001516 /*
1517 * Clear the RTC force wake bit to allow the
1518 * mac to go to sleep.
1519 */
Sujithf1dc5602008-10-29 10:16:30 +05301520 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1521 AR_RTC_FORCE_WAKE_EN);
1522 }
1523 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001524
1525 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1526 if (AR_SREV_9300_20_OR_LATER(ah))
1527 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Sujithf1dc5602008-10-29 10:16:30 +05301528}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001529
Sujithcbe61d82009-02-09 13:27:12 +05301530static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
Sujithf1dc5602008-10-29 10:16:30 +05301531{
1532 u32 val;
1533 int i;
1534
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001535 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1536 if (AR_SREV_9300_20_OR_LATER(ah)) {
1537 REG_WRITE(ah, AR_WA, ah->WARegVal);
1538 udelay(10);
1539 }
1540
Sujithf1dc5602008-10-29 10:16:30 +05301541 if (setChip) {
1542 if ((REG_READ(ah, AR_RTC_STATUS) &
1543 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1544 if (ath9k_hw_set_reset_reg(ah,
1545 ATH9K_RESET_POWER_ON) != true) {
1546 return false;
1547 }
Luis R. Rodrigueze0412282010-04-15 17:38:15 -04001548 if (!AR_SREV_9300_20_OR_LATER(ah))
1549 ath9k_hw_init_pll(ah, NULL);
Sujithf1dc5602008-10-29 10:16:30 +05301550 }
1551 if (AR_SREV_9100(ah))
1552 REG_SET_BIT(ah, AR_RTC_RESET,
1553 AR_RTC_RESET_EN);
1554
1555 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1556 AR_RTC_FORCE_WAKE_EN);
1557 udelay(50);
1558
1559 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1560 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1561 if (val == AR_RTC_STATUS_ON)
1562 break;
1563 udelay(50);
1564 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1565 AR_RTC_FORCE_WAKE_EN);
1566 }
1567 if (i == 0) {
Joe Perches38002762010-12-02 19:12:36 -08001568 ath_err(ath9k_hw_common(ah),
1569 "Failed to wakeup in %uus\n",
1570 POWER_UP_TIME / 20);
Sujithf1dc5602008-10-29 10:16:30 +05301571 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001572 }
1573 }
1574
Sujithf1dc5602008-10-29 10:16:30 +05301575 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1576
1577 return true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001578}
1579
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001580bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Sujithf1dc5602008-10-29 10:16:30 +05301581{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001582 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +05301583 int status = true, setChip = true;
Sujithf1dc5602008-10-29 10:16:30 +05301584 static const char *modes[] = {
1585 "AWAKE",
1586 "FULL-SLEEP",
1587 "NETWORK SLEEP",
1588 "UNDEFINED"
1589 };
Sujithf1dc5602008-10-29 10:16:30 +05301590
Gabor Juhoscbdec972009-07-24 17:27:22 +02001591 if (ah->power_mode == mode)
1592 return status;
1593
Joe Perches226afe62010-12-02 19:12:37 -08001594 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1595 modes[ah->power_mode], modes[mode]);
Sujithf1dc5602008-10-29 10:16:30 +05301596
1597 switch (mode) {
1598 case ATH9K_PM_AWAKE:
1599 status = ath9k_hw_set_power_awake(ah, setChip);
1600 break;
1601 case ATH9K_PM_FULL_SLEEP:
1602 ath9k_set_power_sleep(ah, setChip);
Sujith2660b812009-02-09 13:27:26 +05301603 ah->chip_fullsleep = true;
Sujithf1dc5602008-10-29 10:16:30 +05301604 break;
1605 case ATH9K_PM_NETWORK_SLEEP:
1606 ath9k_set_power_network_sleep(ah, setChip);
1607 break;
1608 default:
Joe Perches38002762010-12-02 19:12:36 -08001609 ath_err(common, "Unknown power mode %u\n", mode);
Sujithf1dc5602008-10-29 10:16:30 +05301610 return false;
1611 }
Sujith2660b812009-02-09 13:27:26 +05301612 ah->power_mode = mode;
Sujithf1dc5602008-10-29 10:16:30 +05301613
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08001614 /*
1615 * XXX: If this warning never comes up after a while then
1616 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1617 * ath9k_hw_setpower() return type void.
1618 */
Sujith Manoharan97dcec52010-12-20 08:02:42 +05301619
1620 if (!(ah->ah_flags & AH_UNPLUGGED))
1621 ATH_DBG_WARN_ON_ONCE(!status);
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08001622
Sujithf1dc5602008-10-29 10:16:30 +05301623 return status;
1624}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04001625EXPORT_SYMBOL(ath9k_hw_setpower);
Sujithf1dc5602008-10-29 10:16:30 +05301626
Sujithf1dc5602008-10-29 10:16:30 +05301627/*******************/
1628/* Beacon Handling */
1629/*******************/
1630
Sujithcbe61d82009-02-09 13:27:12 +05301631void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001632{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001633 int flags = 0;
1634
Sujith7d0d0df2010-04-16 11:53:57 +05301635 ENABLE_REGWRITE_BUFFER(ah);
1636
Sujith2660b812009-02-09 13:27:26 +05301637 switch (ah->opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08001638 case NL80211_IFTYPE_ADHOC:
Pat Erley9cb54122009-03-20 22:59:59 -04001639 case NL80211_IFTYPE_MESH_POINT:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001640 REG_SET_BIT(ah, AR_TXCFG,
1641 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1642 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1643 TU_TO_USEC(next_beacon +
Sujith2660b812009-02-09 13:27:26 +05301644 (ah->atim_window ? ah->
1645 atim_window : 1)));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001646 flags |= AR_NDP_TIMER_EN;
Colin McCabed97809d2008-12-01 13:38:55 -08001647 case NL80211_IFTYPE_AP:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001648 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1649 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1650 TU_TO_USEC(next_beacon -
Sujith2660b812009-02-09 13:27:26 +05301651 ah->config.
Sujith60b67f52008-08-07 10:52:38 +05301652 dma_beacon_response_time));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001653 REG_WRITE(ah, AR_NEXT_SWBA,
1654 TU_TO_USEC(next_beacon -
Sujith2660b812009-02-09 13:27:26 +05301655 ah->config.
Sujith60b67f52008-08-07 10:52:38 +05301656 sw_beacon_response_time));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001657 flags |=
1658 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1659 break;
Colin McCabed97809d2008-12-01 13:38:55 -08001660 default:
Joe Perches226afe62010-12-02 19:12:37 -08001661 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1662 "%s: unsupported opmode: %d\n",
1663 __func__, ah->opmode);
Colin McCabed97809d2008-12-01 13:38:55 -08001664 return;
1665 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001666 }
1667
1668 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1669 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1670 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1671 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1672
Sujith7d0d0df2010-04-16 11:53:57 +05301673 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301674
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001675 beacon_period &= ~ATH9K_BEACON_ENA;
1676 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001677 ath9k_hw_reset_tsf(ah);
1678 }
1679
1680 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1681}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04001682EXPORT_SYMBOL(ath9k_hw_beaconinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001683
Sujithcbe61d82009-02-09 13:27:12 +05301684void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301685 const struct ath9k_beacon_state *bs)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001686{
1687 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
Sujith2660b812009-02-09 13:27:26 +05301688 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001689 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001690
Sujith7d0d0df2010-04-16 11:53:57 +05301691 ENABLE_REGWRITE_BUFFER(ah);
1692
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001693 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1694
1695 REG_WRITE(ah, AR_BEACON_PERIOD,
1696 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1697 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1698 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1699
Sujith7d0d0df2010-04-16 11:53:57 +05301700 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301701
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001702 REG_RMW_FIELD(ah, AR_RSSI_THR,
1703 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1704
1705 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1706
1707 if (bs->bs_sleepduration > beaconintval)
1708 beaconintval = bs->bs_sleepduration;
1709
1710 dtimperiod = bs->bs_dtimperiod;
1711 if (bs->bs_sleepduration > dtimperiod)
1712 dtimperiod = bs->bs_sleepduration;
1713
1714 if (beaconintval == dtimperiod)
1715 nextTbtt = bs->bs_nextdtim;
1716 else
1717 nextTbtt = bs->bs_nexttbtt;
1718
Joe Perches226afe62010-12-02 19:12:37 -08001719 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1720 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1721 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1722 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001723
Sujith7d0d0df2010-04-16 11:53:57 +05301724 ENABLE_REGWRITE_BUFFER(ah);
1725
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001726 REG_WRITE(ah, AR_NEXT_DTIM,
1727 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1728 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1729
1730 REG_WRITE(ah, AR_SLEEP1,
1731 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1732 | AR_SLEEP1_ASSUME_DTIM);
1733
Sujith60b67f52008-08-07 10:52:38 +05301734 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001735 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1736 else
1737 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1738
1739 REG_WRITE(ah, AR_SLEEP2,
1740 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1741
1742 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1743 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1744
Sujith7d0d0df2010-04-16 11:53:57 +05301745 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301746
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001747 REG_SET_BIT(ah, AR_TIMER_MODE,
1748 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1749 AR_DTIM_TIMER_EN);
1750
Sujith4af9cf42009-02-12 10:06:47 +05301751 /* TSF Out of Range Threshold */
1752 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001753}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04001754EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001755
Sujithf1dc5602008-10-29 10:16:30 +05301756/*******************/
1757/* HW Capabilities */
1758/*******************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001759
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01001760int ath9k_hw_fill_cap_info(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001761{
Sujith2660b812009-02-09 13:27:26 +05301762 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001763 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001764 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07001765 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001766
Sujithf1dc5602008-10-29 10:16:30 +05301767 u16 capField = 0, eeval;
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08001768 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001769
Sujithf74df6f2009-02-09 13:27:24 +05301770 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001771 regulatory->current_rd = eeval;
Sujithf1dc5602008-10-29 10:16:30 +05301772
Sujithf74df6f2009-02-09 13:27:24 +05301773 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
Felix Fietkaue17f83e2010-09-22 12:34:53 +02001774 if (AR_SREV_9285_12_OR_LATER(ah))
Sujithfec0de12009-02-12 10:06:43 +05301775 eeval |= AR9285_RDEXT_DEFAULT;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001776 regulatory->current_rd_ext = eeval;
Sujithf1dc5602008-10-29 10:16:30 +05301777
Sujithf74df6f2009-02-09 13:27:24 +05301778 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
Sujithf1dc5602008-10-29 10:16:30 +05301779
Sujith2660b812009-02-09 13:27:26 +05301780 if (ah->opmode != NL80211_IFTYPE_AP &&
Sujithd535a422009-02-09 13:27:06 +05301781 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001782 if (regulatory->current_rd == 0x64 ||
1783 regulatory->current_rd == 0x65)
1784 regulatory->current_rd += 5;
1785 else if (regulatory->current_rd == 0x41)
1786 regulatory->current_rd = 0x43;
Joe Perches226afe62010-12-02 19:12:37 -08001787 ath_dbg(common, ATH_DBG_REGULATORY,
1788 "regdomain mapped to 0x%x\n", regulatory->current_rd);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001789 }
Sujithdc2222a2008-08-14 13:26:55 +05301790
Sujithf74df6f2009-02-09 13:27:24 +05301791 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01001792 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
Joe Perches38002762010-12-02 19:12:36 -08001793 ath_err(common,
1794 "no band has been marked as supported in EEPROM\n");
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01001795 return -EINVAL;
1796 }
1797
Felix Fietkaud4659912010-10-14 16:02:39 +02001798 if (eeval & AR5416_OPFLAGS_11A)
1799 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001800
Felix Fietkaud4659912010-10-14 16:02:39 +02001801 if (eeval & AR5416_OPFLAGS_11G)
1802 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
Sujithf1dc5602008-10-29 10:16:30 +05301803
Sujithf74df6f2009-02-09 13:27:24 +05301804 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001805 /*
1806 * For AR9271 we will temporarilly uses the rx chainmax as read from
1807 * the EEPROM.
1808 */
Sujith8147f5d2009-02-20 15:13:23 +05301809 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001810 !(eeval & AR5416_OPFLAGS_11A) &&
1811 !(AR_SREV_9271(ah)))
1812 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
Sujith8147f5d2009-02-20 15:13:23 +05301813 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1814 else
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001815 /* Use rx_chainmask from EEPROM. */
Sujith8147f5d2009-02-20 15:13:23 +05301816 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301817
Felix Fietkau7a370812010-09-22 12:34:52 +02001818 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
Sujithf1dc5602008-10-29 10:16:30 +05301819
Felix Fietkau02d2ebb2010-11-22 15:39:39 +01001820 /* enable key search for every frame in an aggregate */
1821 if (AR_SREV_9300_20_OR_LATER(ah))
1822 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1823
Sujithf1dc5602008-10-29 10:16:30 +05301824 pCap->low_2ghz_chan = 2312;
1825 pCap->high_2ghz_chan = 2732;
1826
1827 pCap->low_5ghz_chan = 4920;
1828 pCap->high_5ghz_chan = 6100;
1829
Bruno Randolfce2220d2010-09-17 11:36:25 +09001830 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1831
Sujith2660b812009-02-09 13:27:26 +05301832 if (ah->config.ht_enable)
Sujithf1dc5602008-10-29 10:16:30 +05301833 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1834 else
1835 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1836
Sujithf1dc5602008-10-29 10:16:30 +05301837 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1838 pCap->total_queues =
1839 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1840 else
1841 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1842
1843 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1844 pCap->keycache_size =
1845 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1846 else
1847 pCap->keycache_size = AR_KEYTABLE_SIZE;
1848
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -05001849 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1850 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
1851 else
1852 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
Sujithf1dc5602008-10-29 10:16:30 +05301853
Sujith5b5fa352010-03-17 14:25:15 +05301854 if (AR_SREV_9271(ah))
1855 pCap->num_gpio_pins = AR9271_NUM_GPIO;
Sujith88c1f4f2010-06-30 14:46:31 +05301856 else if (AR_DEVID_7010(ah))
1857 pCap->num_gpio_pins = AR7010_NUM_GPIO;
Felix Fietkaue17f83e2010-09-22 12:34:53 +02001858 else if (AR_SREV_9285_12_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05301859 pCap->num_gpio_pins = AR9285_NUM_GPIO;
Felix Fietkau7a370812010-09-22 12:34:52 +02001860 else if (AR_SREV_9280_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301861 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1862 else
1863 pCap->num_gpio_pins = AR_NUM_GPIO;
1864
Sujithf1dc5602008-10-29 10:16:30 +05301865 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1866 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1867 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1868 } else {
1869 pCap->rts_aggr_limit = (8 * 1024);
1870 }
1871
1872 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
1873
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05301874#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Sujith2660b812009-02-09 13:27:26 +05301875 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1876 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1877 ah->rfkill_gpio =
1878 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1879 ah->rfkill_polarity =
1880 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
Sujithf1dc5602008-10-29 10:16:30 +05301881
1882 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1883 }
1884#endif
Vasanthakumar Thiagarajand5d11542010-05-17 18:57:56 -07001885 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
Vivek Natarajanbde748a2010-04-05 14:48:05 +05301886 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1887 else
1888 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
Sujithf1dc5602008-10-29 10:16:30 +05301889
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05301890 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301891 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1892 else
1893 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1894
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001895 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
Sujithf1dc5602008-10-29 10:16:30 +05301896 pCap->reg_cap =
1897 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1898 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
1899 AR_EEPROM_EEREGCAP_EN_KK_U2 |
1900 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
1901 } else {
1902 pCap->reg_cap =
1903 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1904 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
1905 }
1906
Senthil Balasubramanianebb90cf2009-09-18 15:07:33 +05301907 /* Advertise midband for AR5416 with FCC midband set in eeprom */
1908 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
1909 AR_SREV_5416(ah))
1910 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
Sujithf1dc5602008-10-29 10:16:30 +05301911
Vasanthakumar Thiagarajan8f5dcb12010-11-26 06:10:06 -08001912 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07001913 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1914 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
Vasanthakumar Thiagarajan22f25d02009-08-26 21:08:47 +05301915
Vasanthakumar Thiagarajan8c8f9ba2009-09-09 15:25:52 +05301916 if (AR_SREV_9285(ah)) {
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07001917 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1918 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
Vasanthakumar Thiagarajan8c8f9ba2009-09-09 15:25:52 +05301919 } else {
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07001920 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
Vasanthakumar Thiagarajan8c8f9ba2009-09-09 15:25:52 +05301921 }
Vasanthakumar Thiagarajan22f25d02009-08-26 21:08:47 +05301922 } else {
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07001923 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
Vasanthakumar Thiagarajanc97c92d2009-01-02 15:35:46 +05301924 }
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01001925
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04001926 if (AR_SREV_9300_20_OR_LATER(ah)) {
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08001927 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1928 if (!AR_SREV_9485(ah))
1929 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1930
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04001931 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1932 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1933 pCap->rx_status_len = sizeof(struct ar9003_rxs);
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04001934 pCap->tx_desc_len = sizeof(struct ar9003_txc);
Vasanthakumar Thiagarajan5088c2f2010-04-15 17:39:34 -04001935 pCap->txs_len = sizeof(struct ar9003_txs);
Felix Fietkau49352502010-06-12 00:33:59 -04001936 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1937 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04001938 } else {
1939 pCap->tx_desc_len = sizeof(struct ath_desc);
Felix Fietkau6b42e8d2010-04-26 15:04:35 -04001940 if (AR_SREV_9280_20(ah) &&
1941 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1942 AR5416_EEP_MINOR_VER_16) ||
1943 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1944 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04001945 }
Vasanthakumar Thiagarajan1adf02f2010-04-15 17:38:24 -04001946
Vasanthakumar Thiagarajan6c84ce02010-04-15 17:39:16 -04001947 if (AR_SREV_9300_20_OR_LATER(ah))
1948 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1949
Senthil Balasubramanian6ee63f52010-11-10 05:03:16 -08001950 if (AR_SREV_9300_20_OR_LATER(ah))
1951 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1952
Felix Fietkaua42acef2010-09-22 12:34:54 +02001953 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
Vasanthakumar Thiagarajan6473d242010-05-13 18:42:38 -07001954 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1955
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07001956 if (AR_SREV_9285(ah))
1957 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1958 ant_div_ctl1 =
1959 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1960 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1961 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1962 }
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +05301963 if (AR_SREV_9300_20_OR_LATER(ah)) {
1964 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
1965 pCap->hw_caps |= ATH9K_HW_CAP_APM;
1966 }
1967
1968
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07001969
Vasanthakumar Thiagarajan8060e162010-12-06 04:27:42 -08001970 if (AR_SREV_9485_10(ah)) {
1971 pCap->pcie_lcr_extsync_en = true;
1972 pCap->pcie_lcr_offset = 0x80;
1973 }
1974
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08001975 tx_chainmask = pCap->tx_chainmask;
1976 rx_chainmask = pCap->rx_chainmask;
1977 while (tx_chainmask || rx_chainmask) {
1978 if (tx_chainmask & BIT(0))
1979 pCap->max_txchains++;
1980 if (rx_chainmask & BIT(0))
1981 pCap->max_rxchains++;
1982
1983 tx_chainmask >>= 1;
1984 rx_chainmask >>= 1;
1985 }
1986
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01001987 return 0;
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07001988}
1989
Sujithf1dc5602008-10-29 10:16:30 +05301990/****************************/
1991/* GPIO / RFKILL / Antennae */
1992/****************************/
1993
Sujithcbe61d82009-02-09 13:27:12 +05301994static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301995 u32 gpio, u32 type)
1996{
1997 int addr;
1998 u32 gpio_shift, tmp;
1999
2000 if (gpio > 11)
2001 addr = AR_GPIO_OUTPUT_MUX3;
2002 else if (gpio > 5)
2003 addr = AR_GPIO_OUTPUT_MUX2;
2004 else
2005 addr = AR_GPIO_OUTPUT_MUX1;
2006
2007 gpio_shift = (gpio % 6) * 5;
2008
2009 if (AR_SREV_9280_20_OR_LATER(ah)
2010 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2011 REG_RMW(ah, addr, (type << gpio_shift),
2012 (0x1f << gpio_shift));
2013 } else {
2014 tmp = REG_READ(ah, addr);
2015 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2016 tmp &= ~(0x1f << gpio_shift);
2017 tmp |= (type << gpio_shift);
2018 REG_WRITE(ah, addr, tmp);
2019 }
2020}
2021
Sujithcbe61d82009-02-09 13:27:12 +05302022void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302023{
2024 u32 gpio_shift;
2025
Luis R. Rodriguez9680e8a2009-09-13 23:28:00 -07002026 BUG_ON(gpio >= ah->caps.num_gpio_pins);
Sujithf1dc5602008-10-29 10:16:30 +05302027
Sujith88c1f4f2010-06-30 14:46:31 +05302028 if (AR_DEVID_7010(ah)) {
2029 gpio_shift = gpio;
2030 REG_RMW(ah, AR7010_GPIO_OE,
2031 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2032 (AR7010_GPIO_OE_MASK << gpio_shift));
2033 return;
2034 }
Sujithf1dc5602008-10-29 10:16:30 +05302035
Sujith88c1f4f2010-06-30 14:46:31 +05302036 gpio_shift = gpio << 1;
Sujithf1dc5602008-10-29 10:16:30 +05302037 REG_RMW(ah,
2038 AR_GPIO_OE_OUT,
2039 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2040 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2041}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002042EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
Sujithf1dc5602008-10-29 10:16:30 +05302043
Sujithcbe61d82009-02-09 13:27:12 +05302044u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302045{
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302046#define MS_REG_READ(x, y) \
2047 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2048
Sujith2660b812009-02-09 13:27:26 +05302049 if (gpio >= ah->caps.num_gpio_pins)
Sujithf1dc5602008-10-29 10:16:30 +05302050 return 0xffffffff;
2051
Sujith88c1f4f2010-06-30 14:46:31 +05302052 if (AR_DEVID_7010(ah)) {
2053 u32 val;
2054 val = REG_READ(ah, AR7010_GPIO_IN);
2055 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2056 } else if (AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan93069902010-11-30 23:24:09 -08002057 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2058 AR_GPIO_BIT(gpio)) != 0;
Felix Fietkau783dfca2010-04-15 17:38:11 -04002059 else if (AR_SREV_9271(ah))
Sujith5b5fa352010-03-17 14:25:15 +05302060 return MS_REG_READ(AR9271, gpio) != 0;
Felix Fietkaua42acef2010-09-22 12:34:54 +02002061 else if (AR_SREV_9287_11_OR_LATER(ah))
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05302062 return MS_REG_READ(AR9287, gpio) != 0;
Felix Fietkaue17f83e2010-09-22 12:34:53 +02002063 else if (AR_SREV_9285_12_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302064 return MS_REG_READ(AR9285, gpio) != 0;
Felix Fietkau7a370812010-09-22 12:34:52 +02002065 else if (AR_SREV_9280_20_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302066 return MS_REG_READ(AR928X, gpio) != 0;
2067 else
2068 return MS_REG_READ(AR, gpio) != 0;
Sujithf1dc5602008-10-29 10:16:30 +05302069}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002070EXPORT_SYMBOL(ath9k_hw_gpio_get);
Sujithf1dc5602008-10-29 10:16:30 +05302071
Sujithcbe61d82009-02-09 13:27:12 +05302072void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
Sujithf1dc5602008-10-29 10:16:30 +05302073 u32 ah_signal_type)
2074{
2075 u32 gpio_shift;
2076
Sujith88c1f4f2010-06-30 14:46:31 +05302077 if (AR_DEVID_7010(ah)) {
2078 gpio_shift = gpio;
2079 REG_RMW(ah, AR7010_GPIO_OE,
2080 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2081 (AR7010_GPIO_OE_MASK << gpio_shift));
2082 return;
2083 }
2084
Sujithf1dc5602008-10-29 10:16:30 +05302085 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
Sujithf1dc5602008-10-29 10:16:30 +05302086 gpio_shift = 2 * gpio;
Sujithf1dc5602008-10-29 10:16:30 +05302087 REG_RMW(ah,
2088 AR_GPIO_OE_OUT,
2089 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2090 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2091}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002092EXPORT_SYMBOL(ath9k_hw_cfg_output);
Sujithf1dc5602008-10-29 10:16:30 +05302093
Sujithcbe61d82009-02-09 13:27:12 +05302094void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
Sujithf1dc5602008-10-29 10:16:30 +05302095{
Sujith88c1f4f2010-06-30 14:46:31 +05302096 if (AR_DEVID_7010(ah)) {
2097 val = val ? 0 : 1;
2098 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2099 AR_GPIO_BIT(gpio));
2100 return;
2101 }
2102
Sujith5b5fa352010-03-17 14:25:15 +05302103 if (AR_SREV_9271(ah))
2104 val = ~val;
2105
Sujithf1dc5602008-10-29 10:16:30 +05302106 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2107 AR_GPIO_BIT(gpio));
2108}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002109EXPORT_SYMBOL(ath9k_hw_set_gpio);
Sujithf1dc5602008-10-29 10:16:30 +05302110
Sujithcbe61d82009-02-09 13:27:12 +05302111u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302112{
2113 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2114}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002115EXPORT_SYMBOL(ath9k_hw_getdefantenna);
Sujithf1dc5602008-10-29 10:16:30 +05302116
Sujithcbe61d82009-02-09 13:27:12 +05302117void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
Sujithf1dc5602008-10-29 10:16:30 +05302118{
2119 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2120}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002121EXPORT_SYMBOL(ath9k_hw_setantenna);
Sujithf1dc5602008-10-29 10:16:30 +05302122
Sujithf1dc5602008-10-29 10:16:30 +05302123/*********************/
2124/* General Operation */
2125/*********************/
2126
Sujithcbe61d82009-02-09 13:27:12 +05302127u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302128{
2129 u32 bits = REG_READ(ah, AR_RX_FILTER);
2130 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2131
2132 if (phybits & AR_PHY_ERR_RADAR)
2133 bits |= ATH9K_RX_FILTER_PHYRADAR;
2134 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2135 bits |= ATH9K_RX_FILTER_PHYERR;
2136
2137 return bits;
2138}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002139EXPORT_SYMBOL(ath9k_hw_getrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302140
Sujithcbe61d82009-02-09 13:27:12 +05302141void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
Sujithf1dc5602008-10-29 10:16:30 +05302142{
2143 u32 phybits;
2144
Sujith7d0d0df2010-04-16 11:53:57 +05302145 ENABLE_REGWRITE_BUFFER(ah);
2146
Sujith7ea310b2009-09-03 12:08:43 +05302147 REG_WRITE(ah, AR_RX_FILTER, bits);
2148
Sujithf1dc5602008-10-29 10:16:30 +05302149 phybits = 0;
2150 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2151 phybits |= AR_PHY_ERR_RADAR;
2152 if (bits & ATH9K_RX_FILTER_PHYERR)
2153 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2154 REG_WRITE(ah, AR_PHY_ERR, phybits);
2155
2156 if (phybits)
2157 REG_WRITE(ah, AR_RXCFG,
2158 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2159 else
2160 REG_WRITE(ah, AR_RXCFG,
2161 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
Sujith7d0d0df2010-04-16 11:53:57 +05302162
2163 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302164}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002165EXPORT_SYMBOL(ath9k_hw_setrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302166
Sujithcbe61d82009-02-09 13:27:12 +05302167bool ath9k_hw_phy_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302168{
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302169 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2170 return false;
2171
2172 ath9k_hw_init_pll(ah, NULL);
2173 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302174}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002175EXPORT_SYMBOL(ath9k_hw_phy_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302176
Sujithcbe61d82009-02-09 13:27:12 +05302177bool ath9k_hw_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302178{
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002179 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05302180 return false;
2181
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302182 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2183 return false;
2184
2185 ath9k_hw_init_pll(ah, NULL);
2186 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302187}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002188EXPORT_SYMBOL(ath9k_hw_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302189
Felix Fietkaude40f312010-10-20 03:08:53 +02002190void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
Sujithf1dc5602008-10-29 10:16:30 +05302191{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002192 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Sujith2660b812009-02-09 13:27:26 +05302193 struct ath9k_channel *chan = ah->curchan;
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08002194 struct ieee80211_channel *channel = chan->chan;
Sujithf1dc5602008-10-29 10:16:30 +05302195
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002196 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
Sujithf1dc5602008-10-29 10:16:30 +05302197
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07002198 ah->eep_ops->set_txpower(ah, chan,
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002199 ath9k_regd_get_ctl(regulatory, chan),
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07002200 channel->max_antenna_gain * 2,
2201 channel->max_power * 2,
2202 min((u32) MAX_RATE_POWER,
Felix Fietkaude40f312010-10-20 03:08:53 +02002203 (u32) regulatory->power_limit), test);
Sujithf1dc5602008-10-29 10:16:30 +05302204}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002205EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
Sujithf1dc5602008-10-29 10:16:30 +05302206
Sujithcbe61d82009-02-09 13:27:12 +05302207void ath9k_hw_setopmode(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302208{
Sujith2660b812009-02-09 13:27:26 +05302209 ath9k_hw_set_operating_mode(ah, ah->opmode);
Sujithf1dc5602008-10-29 10:16:30 +05302210}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002211EXPORT_SYMBOL(ath9k_hw_setopmode);
Sujithf1dc5602008-10-29 10:16:30 +05302212
Sujithcbe61d82009-02-09 13:27:12 +05302213void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
Sujithf1dc5602008-10-29 10:16:30 +05302214{
2215 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2216 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2217}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002218EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302219
Luis R. Rodriguezf2b21432009-09-10 08:50:20 -07002220void ath9k_hw_write_associd(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302221{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07002222 struct ath_common *common = ath9k_hw_common(ah);
2223
2224 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2225 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2226 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
Sujithf1dc5602008-10-29 10:16:30 +05302227}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002228EXPORT_SYMBOL(ath9k_hw_write_associd);
Sujithf1dc5602008-10-29 10:16:30 +05302229
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002230#define ATH9K_MAX_TSF_READ 10
2231
Sujithcbe61d82009-02-09 13:27:12 +05302232u64 ath9k_hw_gettsf64(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302233{
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002234 u32 tsf_lower, tsf_upper1, tsf_upper2;
2235 int i;
Sujithf1dc5602008-10-29 10:16:30 +05302236
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002237 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2238 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2239 tsf_lower = REG_READ(ah, AR_TSF_L32);
2240 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2241 if (tsf_upper2 == tsf_upper1)
2242 break;
2243 tsf_upper1 = tsf_upper2;
2244 }
Sujithf1dc5602008-10-29 10:16:30 +05302245
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002246 WARN_ON( i == ATH9K_MAX_TSF_READ );
2247
2248 return (((u64)tsf_upper1 << 32) | tsf_lower);
Sujithf1dc5602008-10-29 10:16:30 +05302249}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002250EXPORT_SYMBOL(ath9k_hw_gettsf64);
Sujithf1dc5602008-10-29 10:16:30 +05302251
Sujithcbe61d82009-02-09 13:27:12 +05302252void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002253{
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002254 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
Alina Friedrichsenb9a16192009-03-02 23:28:38 +01002255 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002256}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002257EXPORT_SYMBOL(ath9k_hw_settsf64);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002258
Sujithcbe61d82009-02-09 13:27:12 +05302259void ath9k_hw_reset_tsf(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302260{
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002261 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2262 AH_TSF_WRITE_TIMEOUT))
Joe Perches226afe62010-12-02 19:12:37 -08002263 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2264 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002265
Sujithf1dc5602008-10-29 10:16:30 +05302266 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002267}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002268EXPORT_SYMBOL(ath9k_hw_reset_tsf);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002269
Sujith54e4cec2009-08-07 09:45:09 +05302270void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002271{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002272 if (setting)
Sujith2660b812009-02-09 13:27:26 +05302273 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002274 else
Sujith2660b812009-02-09 13:27:26 +05302275 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002276}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002277EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002278
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002279void ath9k_hw_set11nmac2040(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002280{
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002281 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Sujithf1dc5602008-10-29 10:16:30 +05302282 u32 macmode;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002283
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07002284 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
Sujithf1dc5602008-10-29 10:16:30 +05302285 macmode = AR_2040_JOINED_RX_CLEAR;
2286 else
2287 macmode = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002288
Sujithf1dc5602008-10-29 10:16:30 +05302289 REG_WRITE(ah, AR_2040_MODE, macmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002290}
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302291
2292/* HW Generic timers configuration */
2293
2294static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2295{
2296 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2297 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2298 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2299 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2300 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2301 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2302 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2303 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2304 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2305 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2306 AR_NDP2_TIMER_MODE, 0x0002},
2307 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2308 AR_NDP2_TIMER_MODE, 0x0004},
2309 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2310 AR_NDP2_TIMER_MODE, 0x0008},
2311 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2312 AR_NDP2_TIMER_MODE, 0x0010},
2313 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2314 AR_NDP2_TIMER_MODE, 0x0020},
2315 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2316 AR_NDP2_TIMER_MODE, 0x0040},
2317 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2318 AR_NDP2_TIMER_MODE, 0x0080}
2319};
2320
2321/* HW generic timer primitives */
2322
2323/* compute and clear index of rightmost 1 */
2324static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2325{
2326 u32 b;
2327
2328 b = *mask;
2329 b &= (0-b);
2330 *mask &= ~b;
2331 b *= debruijn32;
2332 b >>= 27;
2333
2334 return timer_table->gen_timer_index[b];
2335}
2336
Felix Fietkau744bcb42010-10-15 20:03:33 +02002337static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302338{
2339 return REG_READ(ah, AR_TSF_L32);
2340}
2341
2342struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2343 void (*trigger)(void *),
2344 void (*overflow)(void *),
2345 void *arg,
2346 u8 timer_index)
2347{
2348 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2349 struct ath_gen_timer *timer;
2350
2351 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2352
2353 if (timer == NULL) {
Joe Perches38002762010-12-02 19:12:36 -08002354 ath_err(ath9k_hw_common(ah),
2355 "Failed to allocate memory for hw timer[%d]\n",
2356 timer_index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302357 return NULL;
2358 }
2359
2360 /* allocate a hardware generic timer slot */
2361 timer_table->timers[timer_index] = timer;
2362 timer->index = timer_index;
2363 timer->trigger = trigger;
2364 timer->overflow = overflow;
2365 timer->arg = arg;
2366
2367 return timer;
2368}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002369EXPORT_SYMBOL(ath_gen_timer_alloc);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302370
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07002371void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2372 struct ath_gen_timer *timer,
2373 u32 timer_next,
2374 u32 timer_period)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302375{
2376 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2377 u32 tsf;
2378
2379 BUG_ON(!timer_period);
2380
2381 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2382
2383 tsf = ath9k_hw_gettsf32(ah);
2384
Joe Perches226afe62010-12-02 19:12:37 -08002385 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2386 "current tsf %x period %x timer_next %x\n",
2387 tsf, timer_period, timer_next);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302388
2389 /*
2390 * Pull timer_next forward if the current TSF already passed it
2391 * because of software latency
2392 */
2393 if (timer_next < tsf)
2394 timer_next = tsf + timer_period;
2395
2396 /*
2397 * Program generic timer registers
2398 */
2399 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2400 timer_next);
2401 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2402 timer_period);
2403 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2404 gen_tmr_configuration[timer->index].mode_mask);
2405
2406 /* Enable both trigger and thresh interrupt masks */
2407 REG_SET_BIT(ah, AR_IMR_S5,
2408 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2409 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302410}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002411EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302412
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07002413void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302414{
2415 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2416
2417 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2418 (timer->index >= ATH_MAX_GEN_TIMER)) {
2419 return;
2420 }
2421
2422 /* Clear generic timer enable bits. */
2423 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2424 gen_tmr_configuration[timer->index].mode_mask);
2425
2426 /* Disable both trigger and thresh interrupt masks */
2427 REG_CLR_BIT(ah, AR_IMR_S5,
2428 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2429 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2430
2431 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302432}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002433EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302434
2435void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2436{
2437 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2438
2439 /* free the hardware generic timer slot */
2440 timer_table->timers[timer->index] = NULL;
2441 kfree(timer);
2442}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002443EXPORT_SYMBOL(ath_gen_timer_free);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302444
2445/*
2446 * Generic Timer Interrupts handling
2447 */
2448void ath_gen_timer_isr(struct ath_hw *ah)
2449{
2450 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2451 struct ath_gen_timer *timer;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002452 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302453 u32 trigger_mask, thresh_mask, index;
2454
2455 /* get hardware generic timer interrupt status */
2456 trigger_mask = ah->intr_gen_timer_trigger;
2457 thresh_mask = ah->intr_gen_timer_thresh;
2458 trigger_mask &= timer_table->timer_mask.val;
2459 thresh_mask &= timer_table->timer_mask.val;
2460
2461 trigger_mask &= ~thresh_mask;
2462
2463 while (thresh_mask) {
2464 index = rightmost_index(timer_table, &thresh_mask);
2465 timer = timer_table->timers[index];
2466 BUG_ON(!timer);
Joe Perches226afe62010-12-02 19:12:37 -08002467 ath_dbg(common, ATH_DBG_HWTIMER,
2468 "TSF overflow for Gen timer %d\n", index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302469 timer->overflow(timer->arg);
2470 }
2471
2472 while (trigger_mask) {
2473 index = rightmost_index(timer_table, &trigger_mask);
2474 timer = timer_table->timers[index];
2475 BUG_ON(!timer);
Joe Perches226afe62010-12-02 19:12:37 -08002476 ath_dbg(common, ATH_DBG_HWTIMER,
2477 "Gen timer[%d] trigger\n", index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302478 timer->trigger(timer->arg);
2479 }
2480}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002481EXPORT_SYMBOL(ath_gen_timer_isr);
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04002482
Sujith05020d22010-03-17 14:25:23 +05302483/********/
2484/* HTC */
2485/********/
2486
2487void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2488{
2489 ah->htc_reset_init = true;
2490}
2491EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2492
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04002493static struct {
2494 u32 version;
2495 const char * name;
2496} ath_mac_bb_names[] = {
2497 /* Devices with external radios */
2498 { AR_SREV_VERSION_5416_PCI, "5416" },
2499 { AR_SREV_VERSION_5416_PCIE, "5418" },
2500 { AR_SREV_VERSION_9100, "9100" },
2501 { AR_SREV_VERSION_9160, "9160" },
2502 /* Single-chip solutions */
2503 { AR_SREV_VERSION_9280, "9280" },
2504 { AR_SREV_VERSION_9285, "9285" },
Luis R. Rodriguez11158472009-10-27 12:59:35 -04002505 { AR_SREV_VERSION_9287, "9287" },
2506 { AR_SREV_VERSION_9271, "9271" },
Luis R. Rodriguezec839032010-04-15 17:39:20 -04002507 { AR_SREV_VERSION_9300, "9300" },
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04002508};
2509
2510/* For devices with external radios */
2511static struct {
2512 u16 version;
2513 const char * name;
2514} ath_rf_names[] = {
2515 { 0, "5133" },
2516 { AR_RAD5133_SREV_MAJOR, "5133" },
2517 { AR_RAD5122_SREV_MAJOR, "5122" },
2518 { AR_RAD2133_SREV_MAJOR, "2133" },
2519 { AR_RAD2122_SREV_MAJOR, "2122" }
2520};
2521
2522/*
2523 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2524 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04002525static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04002526{
2527 int i;
2528
2529 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2530 if (ath_mac_bb_names[i].version == mac_bb_version) {
2531 return ath_mac_bb_names[i].name;
2532 }
2533 }
2534
2535 return "????";
2536}
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04002537
2538/*
2539 * Return the RF name. "????" is returned if the RF is unknown.
2540 * Used for devices with external radios.
2541 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04002542static const char *ath9k_hw_rf_name(u16 rf_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04002543{
2544 int i;
2545
2546 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2547 if (ath_rf_names[i].version == rf_version) {
2548 return ath_rf_names[i].name;
2549 }
2550 }
2551
2552 return "????";
2553}
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04002554
2555void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2556{
2557 int used;
2558
2559 /* chipsets >= AR9280 are single-chip */
Felix Fietkau7a370812010-09-22 12:34:52 +02002560 if (AR_SREV_9280_20_OR_LATER(ah)) {
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04002561 used = snprintf(hw_name, len,
2562 "Atheros AR%s Rev:%x",
2563 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2564 ah->hw_version.macRev);
2565 }
2566 else {
2567 used = snprintf(hw_name, len,
2568 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2569 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2570 ah->hw_version.macRev,
2571 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2572 AR_RADIO_SREV_MAJOR)),
2573 ah->hw_version.phyRev);
2574 }
2575
2576 hw_name[used] = '\0';
2577}
2578EXPORT_SYMBOL(ath9k_hw_name);