blob: f608f02f29a3505dfe4c84055e90e782f2ebb795 [file] [log] [blame]
Vitja Makarov8b5f79f2008-02-29 12:24:23 +08001/*
Vitja Makarov8b5f79f2008-02-29 12:24:23 +08002 * Based on arm clockevents implementation and old bfin time tick.
3 *
Robin Getz96f10502009-09-24 14:11:24 +00004 * Copyright 2008-2009 Analog Devics Inc.
5 * 2008 GeoTechnologies
6 * Vitja Makarov
Vitja Makarov8b5f79f2008-02-29 12:24:23 +08007 *
Robin Getz96f10502009-09-24 14:11:24 +00008 * Licensed under the GPL-2
Vitja Makarov8b5f79f2008-02-29 12:24:23 +08009 */
Robin Getz96f10502009-09-24 14:11:24 +000010
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080011#include <linux/module.h>
12#include <linux/profile.h>
13#include <linux/interrupt.h>
14#include <linux/time.h>
Mike Frysinger764cb812008-04-24 05:07:29 +080015#include <linux/timex.h>
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080016#include <linux/irq.h>
17#include <linux/clocksource.h>
18#include <linux/clockchips.h>
Michael Henneriche6c91b62008-04-25 04:58:29 +080019#include <linux/cpufreq.h>
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080020
21#include <asm/blackfin.h>
Michael Henneriche6c91b62008-04-25 04:58:29 +080022#include <asm/time.h>
Graf Yang1fa9be72009-05-15 11:01:59 +000023#include <asm/gptimers.h>
Graf Yang60ffdb32010-01-20 10:56:24 +000024#include <asm/nmi.h>
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080025
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080026
Yi Liceb33be2009-09-15 06:50:51 +000027#if defined(CONFIG_CYCLES_CLOCKSOURCE)
28
Yi Liceb33be2009-09-15 06:50:51 +000029static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080030{
Graf Yang6c2b7072010-01-27 11:16:32 +000031#ifdef CONFIG_CPU_FREQ
Vitja Makarov1bfb4b22008-05-07 11:41:26 +080032 return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
Graf Yang6c2b7072010-01-27 11:16:32 +000033#else
34 return get_cycles();
35#endif
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080036}
37
Graf Yang1fa9be72009-05-15 11:01:59 +000038static struct clocksource bfin_cs_cycles = {
39 .name = "bfin_cs_cycles",
Graf Yange78feaa2009-09-14 04:41:00 +000040 .rating = 400,
Graf Yang1fa9be72009-05-15 11:01:59 +000041 .read = bfin_read_cycles,
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080042 .mask = CLOCKSOURCE_MASK(64),
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080043 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
44};
45
Yi Liceb33be2009-09-15 06:50:51 +000046static inline unsigned long long bfin_cs_cycles_sched_clock(void)
Magnus Damm8e196082009-04-21 12:24:00 -070047{
Mike Frysingerc768a942009-12-04 03:32:11 +000048 return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
49 bfin_cs_cycles.mult, bfin_cs_cycles.shift);
Magnus Damm8e196082009-04-21 12:24:00 -070050}
51
Graf Yang1fa9be72009-05-15 11:01:59 +000052static int __init bfin_cs_cycles_init(void)
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080053{
John Stultza1c57e02010-04-26 20:20:07 -070054 if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080055 panic("failed to register clocksource");
56
57 return 0;
58}
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080059#else
Graf Yang1fa9be72009-05-15 11:01:59 +000060# define bfin_cs_cycles_init()
Vitja Makarov8b5f79f2008-02-29 12:24:23 +080061#endif
62
Graf Yang1fa9be72009-05-15 11:01:59 +000063#ifdef CONFIG_GPTMR0_CLOCKSOURCE
64
65void __init setup_gptimer0(void)
66{
67 disable_gptimers(TIMER0bit);
68
Steven Miao2879bb32012-05-16 18:11:10 +080069#ifdef CONFIG_BF60x
70 bfin_write16(TIMER_DATA_IMSK, 0);
71 set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
72 | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
73#else
Graf Yang1fa9be72009-05-15 11:01:59 +000074 set_gptimer_config(TIMER0_id, \
75 TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
Steven Miao2879bb32012-05-16 18:11:10 +080076#endif
Graf Yang1fa9be72009-05-15 11:01:59 +000077 set_gptimer_period(TIMER0_id, -1);
78 set_gptimer_pwidth(TIMER0_id, -2);
79 SSYNC();
80 enable_gptimers(TIMER0bit);
81}
82
Yi Lif7036d62009-09-15 02:08:50 +000083static cycle_t bfin_read_gptimer0(struct clocksource *cs)
Graf Yang1fa9be72009-05-15 11:01:59 +000084{
85 return bfin_read_TIMER0_COUNTER();
86}
87
88static struct clocksource bfin_cs_gptimer0 = {
89 .name = "bfin_cs_gptimer0",
Graf Yange78feaa2009-09-14 04:41:00 +000090 .rating = 350,
Graf Yang1fa9be72009-05-15 11:01:59 +000091 .read = bfin_read_gptimer0,
92 .mask = CLOCKSOURCE_MASK(32),
Graf Yang1fa9be72009-05-15 11:01:59 +000093 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
94};
95
Yi Liceb33be2009-09-15 06:50:51 +000096static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
97{
Mike Frysingerc768a942009-12-04 03:32:11 +000098 return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
99 bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
Yi Liceb33be2009-09-15 06:50:51 +0000100}
101
Graf Yang1fa9be72009-05-15 11:01:59 +0000102static int __init bfin_cs_gptimer0_init(void)
103{
104 setup_gptimer0();
105
John Stultza1c57e02010-04-26 20:20:07 -0700106 if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
Graf Yang1fa9be72009-05-15 11:01:59 +0000107 panic("failed to register clocksource");
108
109 return 0;
110}
111#else
112# define bfin_cs_gptimer0_init()
113#endif
114
Yi Liceb33be2009-09-15 06:50:51 +0000115#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
116/* prefer to use cycles since it has higher rating */
117notrace unsigned long long sched_clock(void)
118{
119#if defined(CONFIG_CYCLES_CLOCKSOURCE)
120 return bfin_cs_cycles_sched_clock();
121#else
122 return bfin_cs_gptimer0_sched_clock();
123#endif
124}
125#endif
126
Graf Yang1fa9be72009-05-15 11:01:59 +0000127#if defined(CONFIG_TICKSOURCE_GPTMR0)
Yi Li0d152c22009-12-28 10:21:49 +0000128static int bfin_gptmr0_set_next_event(unsigned long cycles,
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800129 struct clock_event_device *evt)
130{
Graf Yang1fa9be72009-05-15 11:01:59 +0000131 disable_gptimers(TIMER0bit);
132
133 /* it starts counting three SCLK cycles after the TIMENx bit is set */
134 set_gptimer_pwidth(TIMER0_id, cycles - 3);
135 enable_gptimers(TIMER0bit);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800136 return 0;
137}
138
Yi Li0d152c22009-12-28 10:21:49 +0000139static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
Graf Yang1fa9be72009-05-15 11:01:59 +0000140 struct clock_event_device *evt)
141{
142 switch (mode) {
143 case CLOCK_EVT_MODE_PERIODIC: {
Steven Miao2879bb32012-05-16 18:11:10 +0800144#ifndef CONFIG_BF60x
Graf Yang1fa9be72009-05-15 11:01:59 +0000145 set_gptimer_config(TIMER0_id, \
146 TIMER_OUT_DIS | TIMER_IRQ_ENA | \
147 TIMER_PERIOD_CNT | TIMER_MODE_PWM);
Steven Miao2879bb32012-05-16 18:11:10 +0800148#else
149 set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
150 | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
151#endif
152
Graf Yang1fa9be72009-05-15 11:01:59 +0000153 set_gptimer_period(TIMER0_id, get_sclk() / HZ);
154 set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
155 enable_gptimers(TIMER0bit);
156 break;
157 }
158 case CLOCK_EVT_MODE_ONESHOT:
159 disable_gptimers(TIMER0bit);
Steven Miao2879bb32012-05-16 18:11:10 +0800160#ifndef CONFIG_BF60x
Graf Yang1fa9be72009-05-15 11:01:59 +0000161 set_gptimer_config(TIMER0_id, \
162 TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
Steven Miao2879bb32012-05-16 18:11:10 +0800163#else
164 set_gptimer_config(TIMER0_id, TIMER_OUT_DIS | TIMER_MODE_PWM
165 | TIMER_PULSE_HI | TIMER_IRQ_WID_DLY);
166#endif
167
Graf Yang1fa9be72009-05-15 11:01:59 +0000168 set_gptimer_period(TIMER0_id, 0);
169 break;
170 case CLOCK_EVT_MODE_UNUSED:
171 case CLOCK_EVT_MODE_SHUTDOWN:
172 disable_gptimers(TIMER0bit);
173 break;
174 case CLOCK_EVT_MODE_RESUME:
175 break;
176 }
177}
178
Yi Li0d152c22009-12-28 10:21:49 +0000179static void bfin_gptmr0_ack(void)
Graf Yang1fa9be72009-05-15 11:01:59 +0000180{
Steven Miao2879bb32012-05-16 18:11:10 +0800181 clear_gptimer_intr(TIMER0_id);
Graf Yang1fa9be72009-05-15 11:01:59 +0000182}
183
Yi Li0d152c22009-12-28 10:21:49 +0000184static void __init bfin_gptmr0_init(void)
Graf Yang1fa9be72009-05-15 11:01:59 +0000185{
186 disable_gptimers(TIMER0bit);
187}
188
Yi Li0d152c22009-12-28 10:21:49 +0000189#ifdef CONFIG_CORE_TIMER_IRQ_L1
190__attribute__((l1_text))
191#endif
192irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
Graf Yang1fa9be72009-05-15 11:01:59 +0000193{
Yi Li0d152c22009-12-28 10:21:49 +0000194 struct clock_event_device *evt = dev_id;
195 smp_mb();
Mike Frysinger0bf02ce2011-04-04 15:26:11 +0000196 /*
197 * We want to ACK before we handle so that we can handle smaller timer
198 * intervals. This way if the timer expires again while we're handling
199 * things, we're more likely to see that 2nd int rather than swallowing
200 * it by ACKing the int at the end of this handler.
201 */
Yi Li0d152c22009-12-28 10:21:49 +0000202 bfin_gptmr0_ack();
Mike Frysinger0bf02ce2011-04-04 15:26:11 +0000203 evt->event_handler(evt);
Yi Li0d152c22009-12-28 10:21:49 +0000204 return IRQ_HANDLED;
Graf Yang1fa9be72009-05-15 11:01:59 +0000205}
206
Yi Li0d152c22009-12-28 10:21:49 +0000207static struct irqaction gptmr0_irq = {
208 .name = "Blackfin GPTimer0",
Yong Zhang7832bb52011-09-07 16:10:03 +0800209 .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
Yi Li0d152c22009-12-28 10:21:49 +0000210 .handler = bfin_gptmr0_interrupt,
211};
Graf Yang1fa9be72009-05-15 11:01:59 +0000212
Yi Li0d152c22009-12-28 10:21:49 +0000213static struct clock_event_device clockevent_gptmr0 = {
214 .name = "bfin_gptimer0",
215 .rating = 300,
216 .irq = IRQ_TIMER0,
217 .shift = 32,
Steven Miao2879bb32012-05-16 18:11:10 +0800218 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
Yi Li0d152c22009-12-28 10:21:49 +0000219 .set_next_event = bfin_gptmr0_set_next_event,
220 .set_mode = bfin_gptmr0_set_mode,
221};
222
223static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
224{
225 unsigned long clock_tick;
226
227 clock_tick = get_sclk();
228 evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
229 evt->max_delta_ns = clockevent_delta2ns(-1, evt);
230 evt->min_delta_ns = clockevent_delta2ns(100, evt);
231
232 evt->cpumask = cpumask_of(0);
233
234 clockevents_register_device(evt);
235}
236#endif /* CONFIG_TICKSOURCE_GPTMR0 */
237
238#if defined(CONFIG_TICKSOURCE_CORETMR)
239/* per-cpu local core timer */
Bob Liud0014be2011-12-12 11:04:05 +0800240DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
Yi Li0d152c22009-12-28 10:21:49 +0000241
242static int bfin_coretmr_set_next_event(unsigned long cycles,
Graf Yang1fa9be72009-05-15 11:01:59 +0000243 struct clock_event_device *evt)
244{
245 bfin_write_TCNTL(TMPWR);
246 CSYNC();
247 bfin_write_TCOUNT(cycles);
248 CSYNC();
249 bfin_write_TCNTL(TMPWR | TMREN);
250 return 0;
251}
252
Yi Li0d152c22009-12-28 10:21:49 +0000253static void bfin_coretmr_set_mode(enum clock_event_mode mode,
Graf Yang1fa9be72009-05-15 11:01:59 +0000254 struct clock_event_device *evt)
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800255{
256 switch (mode) {
257 case CLOCK_EVT_MODE_PERIODIC: {
Michael Henneriche6c91b62008-04-25 04:58:29 +0800258 unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800259 bfin_write_TCNTL(TMPWR);
260 CSYNC();
Graf Yang1fa9be72009-05-15 11:01:59 +0000261 bfin_write_TSCALE(TIME_SCALE - 1);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800262 bfin_write_TPERIOD(tcount);
263 bfin_write_TCOUNT(tcount);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800264 CSYNC();
Graf Yang1fa9be72009-05-15 11:01:59 +0000265 bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800266 break;
267 }
268 case CLOCK_EVT_MODE_ONESHOT:
Graf Yang1fa9be72009-05-15 11:01:59 +0000269 bfin_write_TCNTL(TMPWR);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800270 CSYNC();
Graf Yang1fa9be72009-05-15 11:01:59 +0000271 bfin_write_TSCALE(TIME_SCALE - 1);
272 bfin_write_TPERIOD(0);
273 bfin_write_TCOUNT(0);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800274 break;
275 case CLOCK_EVT_MODE_UNUSED:
276 case CLOCK_EVT_MODE_SHUTDOWN:
277 bfin_write_TCNTL(0);
278 CSYNC();
279 break;
280 case CLOCK_EVT_MODE_RESUME:
281 break;
282 }
283}
284
Yi Li0d152c22009-12-28 10:21:49 +0000285void bfin_coretmr_init(void)
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800286{
287 /* power up the timer, but don't enable it just yet */
288 bfin_write_TCNTL(TMPWR);
289 CSYNC();
290
Yi Li0d152c22009-12-28 10:21:49 +0000291 /* the TSCALE prescaler counter. */
Michael Henneriche6c91b62008-04-25 04:58:29 +0800292 bfin_write_TSCALE(TIME_SCALE - 1);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800293 bfin_write_TPERIOD(0);
294 bfin_write_TCOUNT(0);
295
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800296 CSYNC();
297}
298
Yi Li0d152c22009-12-28 10:21:49 +0000299#ifdef CONFIG_CORE_TIMER_IRQ_L1
300__attribute__((l1_text))
301#endif
Bob Liud0014be2011-12-12 11:04:05 +0800302
Yi Li0d152c22009-12-28 10:21:49 +0000303irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
Graf Yang1fa9be72009-05-15 11:01:59 +0000304{
Yi Li0d152c22009-12-28 10:21:49 +0000305 int cpu = smp_processor_id();
306 struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
Graf Yang1fa9be72009-05-15 11:01:59 +0000307
Graf Yang1fa9be72009-05-15 11:01:59 +0000308 smp_mb();
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800309 evt->event_handler(evt);
Graf Yang60ffdb32010-01-20 10:56:24 +0000310
311 touch_nmi_watchdog();
312
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800313 return IRQ_HANDLED;
314}
315
Yi Li0d152c22009-12-28 10:21:49 +0000316static struct irqaction coretmr_irq = {
317 .name = "Blackfin CoreTimer",
Yong Zhang7832bb52011-09-07 16:10:03 +0800318 .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
Yi Li0d152c22009-12-28 10:21:49 +0000319 .handler = bfin_coretmr_interrupt,
320};
321
322void bfin_coretmr_clockevent_init(void)
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800323{
Yi Li0d152c22009-12-28 10:21:49 +0000324 unsigned long clock_tick;
325 unsigned int cpu = smp_processor_id();
326 struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
Vitja Makarov1bfb4b22008-05-07 11:41:26 +0800327
Bob Liud0014be2011-12-12 11:04:05 +0800328#ifdef CONFIG_SMP
329 evt->broadcast = smp_timer_broadcast;
330#endif
331
332
Steven Miao2879bb32012-05-16 18:11:10 +0800333#ifdef CONFIG_SMP
334 evt->broadcast = smp_timer_broadcast;
335#endif
336
337
Yi Li0d152c22009-12-28 10:21:49 +0000338 evt->name = "bfin_core_timer";
339 evt->rating = 350;
340 evt->irq = -1;
341 evt->shift = 32;
342 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
343 evt->set_next_event = bfin_coretmr_set_next_event;
344 evt->set_mode = bfin_coretmr_set_mode;
Vitja Makarov1bfb4b22008-05-07 11:41:26 +0800345
Yi Li0d152c22009-12-28 10:21:49 +0000346 clock_tick = get_cclk() / TIME_SCALE;
347 evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
348 evt->max_delta_ns = clockevent_delta2ns(-1, evt);
349 evt->min_delta_ns = clockevent_delta2ns(100, evt);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800350
Yi Li0d152c22009-12-28 10:21:49 +0000351 evt->cpumask = cpumask_of(cpu);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800352
Yi Li0d152c22009-12-28 10:21:49 +0000353 clockevents_register_device(evt);
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800354}
Yi Li0d152c22009-12-28 10:21:49 +0000355#endif /* CONFIG_TICKSOURCE_CORETMR */
356
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800357
John Stultzcb0e9962010-03-03 19:57:24 -0800358void read_persistent_clock(struct timespec *ts)
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800359{
360 time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
John Stultzcb0e9962010-03-03 19:57:24 -0800361 ts->tv_sec = secs_since_1970;
362 ts->tv_nsec = 0;
363}
364
365void __init time_init(void)
366{
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800367
368#ifdef CONFIG_RTC_DRV_BFIN
369 /* [#2663] hack to filter junk RTC values that would cause
370 * userspace to have to deal with time values greater than
371 * 2^31 seconds (which uClibc cannot cope with yet)
372 */
373 if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
374 printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
375 bfin_write_RTC_STAT(0);
376 }
377#endif
378
Graf Yang1fa9be72009-05-15 11:01:59 +0000379 bfin_cs_cycles_init();
380 bfin_cs_gptimer0_init();
Yi Li0d152c22009-12-28 10:21:49 +0000381
382#if defined(CONFIG_TICKSOURCE_CORETMR)
383 bfin_coretmr_init();
384 setup_irq(IRQ_CORETMR, &coretmr_irq);
385 bfin_coretmr_clockevent_init();
386#endif
387
388#if defined(CONFIG_TICKSOURCE_GPTMR0)
389 bfin_gptmr0_init();
390 setup_irq(IRQ_TIMER0, &gptmr0_irq);
391 gptmr0_irq.dev_id = &clockevent_gptmr0;
392 bfin_gptmr0_clockevent_init(&clockevent_gptmr0);
393#endif
394
395#if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0)
396# error at least one clock event device is required
397#endif
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800398}