Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | STMMAC Common Header File |
| 3 | |
| 4 | Copyright (C) 2007-2009 STMicroelectronics Ltd |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
| 23 | *******************************************************************************/ |
| 24 | |
| 25 | #include "descs.h" |
| 26 | #include <linux/io.h> |
| 27 | |
| 28 | /* ********************************************* |
| 29 | DMA CRS Control and Status Register Mapping |
| 30 | * *********************************************/ |
| 31 | #define DMA_BUS_MODE 0x00001000 /* Bus Mode */ |
| 32 | #define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */ |
| 33 | #define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */ |
| 34 | #define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */ |
| 35 | #define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */ |
| 36 | #define DMA_STATUS 0x00001014 /* Status Register */ |
| 37 | #define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */ |
| 38 | #define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */ |
| 39 | #define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */ |
| 40 | #define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */ |
| 41 | #define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */ |
| 42 | |
| 43 | /* ******************************** |
| 44 | DMA Control register defines |
| 45 | * ********************************/ |
| 46 | #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */ |
| 47 | #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */ |
| 48 | |
| 49 | /* ************************************** |
| 50 | DMA Interrupt Enable register defines |
| 51 | * **************************************/ |
| 52 | /**** NORMAL INTERRUPT ****/ |
| 53 | #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */ |
| 54 | #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */ |
| 55 | #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */ |
| 56 | #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */ |
| 57 | #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */ |
| 58 | |
| 59 | #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \ |
| 60 | DMA_INTR_ENA_TIE) |
| 61 | |
| 62 | /**** ABNORMAL INTERRUPT ****/ |
| 63 | #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */ |
| 64 | #define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */ |
| 65 | #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */ |
| 66 | #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */ |
| 67 | #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */ |
| 68 | #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */ |
| 69 | #define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */ |
| 70 | #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */ |
| 71 | #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */ |
| 72 | #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */ |
| 73 | |
| 74 | #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \ |
| 75 | DMA_INTR_ENA_UNE) |
| 76 | |
| 77 | /* DMA default interrupt mask */ |
| 78 | #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL) |
| 79 | |
| 80 | /* **************************** |
| 81 | * DMA Status register defines |
| 82 | * ****************************/ |
| 83 | #define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */ |
| 84 | #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */ |
| 85 | #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int. */ |
| 86 | #define DMA_STATUS_GMI 0x08000000 |
| 87 | #define DMA_STATUS_GLI 0x04000000 |
| 88 | #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */ |
| 89 | #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */ |
| 90 | #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */ |
| 91 | #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */ |
| 92 | #define DMA_STATUS_TS_SHIFT 20 |
| 93 | #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */ |
| 94 | #define DMA_STATUS_RS_SHIFT 17 |
| 95 | #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */ |
| 96 | #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */ |
| 97 | #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */ |
| 98 | #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */ |
| 99 | #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */ |
| 100 | #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */ |
| 101 | #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */ |
| 102 | #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */ |
| 103 | #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */ |
| 104 | #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */ |
| 105 | #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */ |
| 106 | #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */ |
| 107 | #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */ |
| 108 | #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */ |
| 109 | #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ |
| 110 | |
| 111 | /* Other defines */ |
| 112 | #define HASH_TABLE_SIZE 64 |
| 113 | #define PAUSE_TIME 0x200 |
| 114 | |
| 115 | /* Flow Control defines */ |
| 116 | #define FLOW_OFF 0 |
| 117 | #define FLOW_RX 1 |
| 118 | #define FLOW_TX 2 |
| 119 | #define FLOW_AUTO (FLOW_TX | FLOW_RX) |
| 120 | |
| 121 | /* DMA STORE-AND-FORWARD Operation Mode */ |
| 122 | #define SF_DMA_MODE 1 |
| 123 | |
| 124 | #define HW_CSUM 1 |
| 125 | #define NO_HW_CSUM 0 |
| 126 | |
| 127 | /* GMAC TX FIFO is 8K, Rx FIFO is 16K */ |
| 128 | #define BUF_SIZE_16KiB 16384 |
| 129 | #define BUF_SIZE_8KiB 8192 |
| 130 | #define BUF_SIZE_4KiB 4096 |
| 131 | #define BUF_SIZE_2KiB 2048 |
| 132 | |
| 133 | /* Power Down and WOL */ |
| 134 | #define PMT_NOT_SUPPORTED 0 |
| 135 | #define PMT_SUPPORTED 1 |
| 136 | |
| 137 | /* Common MAC defines */ |
| 138 | #define MAC_CTRL_REG 0x00000000 /* MAC Control */ |
| 139 | #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ |
| 140 | #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */ |
| 141 | |
| 142 | /* MAC Management Counters register */ |
| 143 | #define MMC_CONTROL 0x00000100 /* MMC Control */ |
| 144 | #define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */ |
| 145 | #define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */ |
| 146 | #define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */ |
| 147 | #define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */ |
| 148 | |
| 149 | #define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */ |
| 150 | #define MMC_CONTROL_MAX_FRM_SHIFT 3 |
| 151 | #define MMC_CONTROL_MAX_FRAME 0x7FF |
| 152 | |
| 153 | struct stmmac_extra_stats { |
| 154 | /* Transmit errors */ |
| 155 | unsigned long tx_underflow ____cacheline_aligned; |
| 156 | unsigned long tx_carrier; |
| 157 | unsigned long tx_losscarrier; |
| 158 | unsigned long tx_heartbeat; |
| 159 | unsigned long tx_deferred; |
| 160 | unsigned long tx_vlan; |
| 161 | unsigned long tx_jabber; |
| 162 | unsigned long tx_frame_flushed; |
| 163 | unsigned long tx_payload_error; |
| 164 | unsigned long tx_ip_header_error; |
| 165 | /* Receive errors */ |
| 166 | unsigned long rx_desc; |
| 167 | unsigned long rx_partial; |
| 168 | unsigned long rx_runt; |
| 169 | unsigned long rx_toolong; |
| 170 | unsigned long rx_collision; |
| 171 | unsigned long rx_crc; |
| 172 | unsigned long rx_lenght; |
| 173 | unsigned long rx_mii; |
| 174 | unsigned long rx_multicast; |
| 175 | unsigned long rx_gmac_overflow; |
| 176 | unsigned long rx_watchdog; |
| 177 | unsigned long da_rx_filter_fail; |
| 178 | unsigned long sa_rx_filter_fail; |
| 179 | unsigned long rx_missed_cntr; |
| 180 | unsigned long rx_overflow_cntr; |
| 181 | unsigned long rx_vlan; |
| 182 | /* Tx/Rx IRQ errors */ |
| 183 | unsigned long tx_undeflow_irq; |
| 184 | unsigned long tx_process_stopped_irq; |
| 185 | unsigned long tx_jabber_irq; |
| 186 | unsigned long rx_overflow_irq; |
| 187 | unsigned long rx_buf_unav_irq; |
| 188 | unsigned long rx_process_stopped_irq; |
| 189 | unsigned long rx_watchdog_irq; |
| 190 | unsigned long tx_early_irq; |
| 191 | unsigned long fatal_bus_error_irq; |
| 192 | /* Extra info */ |
| 193 | unsigned long threshold; |
| 194 | unsigned long tx_pkt_n; |
| 195 | unsigned long rx_pkt_n; |
| 196 | unsigned long poll_n; |
| 197 | unsigned long sched_timer_n; |
| 198 | unsigned long normal_irq_n; |
| 199 | }; |
| 200 | |
| 201 | /* GMAC core can compute the checksums in HW. */ |
| 202 | enum rx_frame_status { |
| 203 | good_frame = 0, |
| 204 | discard_frame = 1, |
| 205 | csum_none = 2, |
| 206 | }; |
| 207 | |
| 208 | static inline void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], |
| 209 | unsigned int high, unsigned int low) |
| 210 | { |
| 211 | unsigned long data; |
| 212 | |
| 213 | data = (addr[5] << 8) | addr[4]; |
| 214 | writel(data, ioaddr + high); |
| 215 | data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; |
| 216 | writel(data, ioaddr + low); |
| 217 | |
| 218 | return; |
| 219 | } |
| 220 | |
| 221 | static inline void stmmac_get_mac_addr(unsigned long ioaddr, |
| 222 | unsigned char *addr, unsigned int high, |
| 223 | unsigned int low) |
| 224 | { |
| 225 | unsigned int hi_addr, lo_addr; |
| 226 | |
| 227 | /* Read the MAC address from the hardware */ |
| 228 | hi_addr = readl(ioaddr + high); |
| 229 | lo_addr = readl(ioaddr + low); |
| 230 | |
| 231 | /* Extract the MAC address from the high and low words */ |
| 232 | addr[0] = lo_addr & 0xff; |
| 233 | addr[1] = (lo_addr >> 8) & 0xff; |
| 234 | addr[2] = (lo_addr >> 16) & 0xff; |
| 235 | addr[3] = (lo_addr >> 24) & 0xff; |
| 236 | addr[4] = hi_addr & 0xff; |
| 237 | addr[5] = (hi_addr >> 8) & 0xff; |
| 238 | |
| 239 | return; |
| 240 | } |
| 241 | |
| 242 | struct stmmac_ops { |
| 243 | /* MAC core initialization */ |
| 244 | void (*core_init) (unsigned long ioaddr) ____cacheline_aligned; |
| 245 | /* DMA core initialization */ |
| 246 | int (*dma_init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx); |
| 247 | /* Dump MAC registers */ |
| 248 | void (*dump_mac_regs) (unsigned long ioaddr); |
| 249 | /* Dump DMA registers */ |
| 250 | void (*dump_dma_regs) (unsigned long ioaddr); |
| 251 | /* Set tx/rx threshold in the csr6 register |
| 252 | * An invalid value enables the store-and-forward mode */ |
| 253 | void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode); |
| 254 | /* To track extra statistic (if supported) */ |
| 255 | void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x, |
| 256 | unsigned long ioaddr); |
| 257 | /* RX descriptor ring initialization */ |
| 258 | void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size, |
| 259 | int disable_rx_ic); |
| 260 | /* TX descriptor ring initialization */ |
| 261 | void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size); |
| 262 | |
| 263 | /* Invoked by the xmit function to prepare the tx descriptor */ |
| 264 | void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len, |
| 265 | int csum_flag); |
| 266 | /* Set/get the owner of the descriptor */ |
| 267 | void (*set_tx_owner) (struct dma_desc *p); |
| 268 | int (*get_tx_owner) (struct dma_desc *p); |
| 269 | /* Invoked by the xmit function to close the tx descriptor */ |
| 270 | void (*close_tx_desc) (struct dma_desc *p); |
| 271 | /* Clean the tx descriptor as soon as the tx irq is received */ |
| 272 | void (*release_tx_desc) (struct dma_desc *p); |
| 273 | /* Clear interrupt on tx frame completion. When this bit is |
| 274 | * set an interrupt happens as soon as the frame is transmitted */ |
| 275 | void (*clear_tx_ic) (struct dma_desc *p); |
| 276 | /* Last tx segment reports the transmit status */ |
| 277 | int (*get_tx_ls) (struct dma_desc *p); |
| 278 | /* Return the transmit status looking at the TDES1 */ |
| 279 | int (*tx_status) (void *data, struct stmmac_extra_stats *x, |
| 280 | struct dma_desc *p, unsigned long ioaddr); |
| 281 | /* Get the buffer size from the descriptor */ |
| 282 | int (*get_tx_len) (struct dma_desc *p); |
| 283 | /* Handle extra events on specific interrupts hw dependent */ |
| 284 | void (*host_irq_status) (unsigned long ioaddr); |
| 285 | int (*get_rx_owner) (struct dma_desc *p); |
| 286 | void (*set_rx_owner) (struct dma_desc *p); |
| 287 | /* Get the receive frame size */ |
| 288 | int (*get_rx_frame_len) (struct dma_desc *p); |
| 289 | /* Return the reception status looking at the RDES1 */ |
| 290 | int (*rx_status) (void *data, struct stmmac_extra_stats *x, |
| 291 | struct dma_desc *p); |
| 292 | /* Multicast filter setting */ |
| 293 | void (*set_filter) (struct net_device *dev); |
| 294 | /* Flow control setting */ |
| 295 | void (*flow_ctrl) (unsigned long ioaddr, unsigned int duplex, |
| 296 | unsigned int fc, unsigned int pause_time); |
| 297 | /* Set power management mode (e.g. magic frame) */ |
| 298 | void (*pmt) (unsigned long ioaddr, unsigned long mode); |
| 299 | /* Set/Get Unicast MAC addresses */ |
| 300 | void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr, |
| 301 | unsigned int reg_n); |
| 302 | void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr, |
| 303 | unsigned int reg_n); |
| 304 | }; |
| 305 | |
| 306 | struct mac_link { |
| 307 | int port; |
| 308 | int duplex; |
| 309 | int speed; |
| 310 | }; |
| 311 | |
| 312 | struct mii_regs { |
| 313 | unsigned int addr; /* MII Address */ |
| 314 | unsigned int data; /* MII Data */ |
| 315 | }; |
| 316 | |
| 317 | struct hw_cap { |
| 318 | unsigned int version; /* Core Version register (GMAC) */ |
| 319 | unsigned int pmt; /* Power-Down mode (GMAC) */ |
| 320 | struct mac_link link; |
| 321 | struct mii_regs mii; |
| 322 | }; |
| 323 | |
| 324 | struct mac_device_info { |
| 325 | struct hw_cap hw; |
| 326 | struct stmmac_ops *ops; |
| 327 | }; |
| 328 | |
| 329 | struct mac_device_info *gmac_setup(unsigned long addr); |
| 330 | struct mac_device_info *mac100_setup(unsigned long addr); |