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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 */
Kumar Gala5f7c6902005-09-09 15:02:25 -05004#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
Paul Mackerras40ef8cb2005-10-10 22:50:37 +10007#include <linux/stringify.h>
David Gibson3ddfbcf2005-11-10 12:56:55 +11008#include <asm/asm-compat.h>
Michael Neuling9c75a312008-06-26 17:07:48 +10009#include <asm/processor.h>
Kumar Gala16c57b32009-02-10 20:10:44 +000010#include <asm/ppc-opcode.h>
Paul Mackerrascf9efce2010-08-26 19:56:43 +000011#include <asm/firmware.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100012
Michael Ellermane3f2c6c2016-10-14 15:58:28 +110013#ifdef __ASSEMBLY__
David Gibson3ddfbcf2005-11-10 12:56:55 +110014
15#define SZL (BITS_PER_LONG/8)
Linus Torvalds1da177e2005-04-16 15:20:36 -070016
17/*
Paul Mackerrasc6622f62006-02-24 10:06:59 +110018 * Stuff for accurate CPU time accounting.
19 * These macros handle transitions between user and system state
20 * in exception entry and exit and accumulate time to the
21 * user_time and system_time fields in the paca.
22 */
23
Frederic Weisbeckerabf917c2012-07-25 07:56:04 +020024#ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
Christophe Leroyc223c902016-05-17 08:33:46 +020025#define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb)
26#define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb)
Paul Mackerrascf9efce2010-08-26 19:56:43 +000027#define ACCOUNT_STOLEN_TIME
Paul Mackerrasc6622f62006-02-24 10:06:59 +110028#else
Christophe Leroyc223c902016-05-17 08:33:46 +020029#define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb) \
Paul Mackerrascf9efce2010-08-26 19:56:43 +000030 MFTB(ra); /* get timebase */ \
Christophe Leroyc223c902016-05-17 08:33:46 +020031 PPC_LL rb, ACCOUNT_STARTTIME_USER(ptr); \
32 PPC_STL ra, ACCOUNT_STARTTIME(ptr); \
Paul Mackerrasc6622f62006-02-24 10:06:59 +110033 subf rb,rb,ra; /* subtract start value */ \
Christophe Leroyc223c902016-05-17 08:33:46 +020034 PPC_LL ra, ACCOUNT_USER_TIME(ptr); \
Paul Mackerrasc6622f62006-02-24 10:06:59 +110035 add ra,ra,rb; /* add on to user time */ \
Christophe Leroyc223c902016-05-17 08:33:46 +020036 PPC_STL ra, ACCOUNT_USER_TIME(ptr); \
Paul Mackerrasc6622f62006-02-24 10:06:59 +110037
Christophe Leroyc223c902016-05-17 08:33:46 +020038#define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb) \
Paul Mackerrascf9efce2010-08-26 19:56:43 +000039 MFTB(ra); /* get timebase */ \
Christophe Leroyc223c902016-05-17 08:33:46 +020040 PPC_LL rb, ACCOUNT_STARTTIME(ptr); \
41 PPC_STL ra, ACCOUNT_STARTTIME_USER(ptr); \
Paul Mackerrasc6622f62006-02-24 10:06:59 +110042 subf rb,rb,ra; /* subtract start value */ \
Christophe Leroyc223c902016-05-17 08:33:46 +020043 PPC_LL ra, ACCOUNT_SYSTEM_TIME(ptr); \
Paul Mackerrascf9efce2010-08-26 19:56:43 +000044 add ra,ra,rb; /* add on to system time */ \
Christophe Leroyc223c902016-05-17 08:33:46 +020045 PPC_STL ra, ACCOUNT_SYSTEM_TIME(ptr)
Paul Mackerrascf9efce2010-08-26 19:56:43 +000046
47#ifdef CONFIG_PPC_SPLPAR
48#define ACCOUNT_STOLEN_TIME \
49BEGIN_FW_FTR_SECTION; \
50 beq 33f; \
51 /* from user - see if there are any DTL entries to process */ \
52 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \
53 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \
Anton Blanchard7ffcf8e2013-08-07 02:01:46 +100054 addi r10,r10,LPPACA_DTLIDX; \
55 LDX_BE r10,0,r10; /* get log write index */ \
Paul Mackerrascf9efce2010-08-26 19:56:43 +000056 cmpd cr1,r11,r10; \
57 beq+ cr1,33f; \
Anton Blanchardb1576fe2014-02-04 16:04:35 +110058 bl accumulate_stolen_time; \
Benjamin Herrenschmidt990118c2012-03-02 11:01:31 +110059 ld r12,_MSR(r1); \
60 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \
Paul Mackerrascf9efce2010-08-26 19:56:43 +00006133: \
62END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
63
64#else /* CONFIG_PPC_SPLPAR */
65#define ACCOUNT_STOLEN_TIME
66
67#endif /* CONFIG_PPC_SPLPAR */
68
Frederic Weisbeckerabf917c2012-07-25 07:56:04 +020069#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
Paul Mackerrasc6622f62006-02-24 10:06:59 +110070
71/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 * Macros for storing registers into and loading registers from
73 * exception frames.
74 */
Kumar Gala5f7c6902005-09-09 15:02:25 -050075#ifdef __powerpc64__
76#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
77#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
78#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
79#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
80#else
Linus Torvalds1da177e2005-04-16 15:20:36 -070081#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
Linus Torvalds1da177e2005-04-16 15:20:36 -070082#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
Linus Torvalds1da177e2005-04-16 15:20:36 -070083#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
84 SAVE_10GPRS(22, base)
85#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
86 REST_10GPRS(22, base)
Kumar Gala5f7c6902005-09-09 15:02:25 -050087#endif
88
Kumar Gala5f7c6902005-09-09 15:02:25 -050089#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
90#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
91#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
92#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
93#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
94#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
95#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
96#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
Linus Torvalds1da177e2005-04-16 15:20:36 -070097
Paul Mackerrasde79f7b2013-09-10 20:20:42 +100098#define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
Linus Torvalds1da177e2005-04-16 15:20:36 -070099#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
100#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
101#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
102#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
103#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
Paul Mackerrasde79f7b2013-09-10 20:20:42 +1000104#define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
106#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
107#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
108#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
109#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
110
Paul Mackerrasde79f7b2013-09-10 20:20:42 +1000111#define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
Kumar Gala5f7c6902005-09-09 15:02:25 -0500112#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
113#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
114#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
115#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
116#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
Paul Mackerrasde79f7b2013-09-10 20:20:42 +1000117#define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
Kumar Gala5f7c6902005-09-09 15:02:25 -0500118#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
119#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
120#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
121#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
122#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123
Anton Blanchard926f1602013-09-23 12:04:39 +1000124#ifdef __BIG_ENDIAN__
125#define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
126#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
127#else
128#define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
129 STXVD2X(n,b,base); \
130 XXSWAPD(n,n)
131
132#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
133 XXSWAPD(n,n)
134#endif
Michael Neuling72ffff52008-06-25 14:07:18 +1000135/* Save the lower 32 VSRs in the thread VSR region */
Benjamin Herrenschmidt3ad26e52013-10-11 18:23:53 +1100136#define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
Michael Neuling72ffff52008-06-25 14:07:18 +1000137#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
138#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
139#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
140#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
141#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
Benjamin Herrenschmidt3ad26e52013-10-11 18:23:53 +1100142#define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
Michael Neuling72ffff52008-06-25 14:07:18 +1000143#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
144#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
145#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
146#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
147#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
Michael Neuling72ffff52008-06-25 14:07:18 +1000148
Scott Woodc51584d2011-06-14 18:34:27 -0500149/*
150 * b = base register for addressing, o = base offset from register of 1st EVR
151 * n = first EVR, s = scratch
152 */
153#define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
154#define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
155#define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
156#define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
157#define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
158#define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
159#define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
160#define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
161#define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
162#define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
163#define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
164#define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165
Michael Ellerman8c716322005-10-24 15:07:27 +1000166/* Macros to adjust thread priority for hardware multithreading */
167#define HMT_VERY_LOW or 31,31,31 # very low priority
168#define HMT_LOW or 1,1,1
169#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
170#define HMT_MEDIUM or 2,2,2
171#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
172#define HMT_HIGH or 3,3,3
Benjamin Herrenschmidt50fb8eb2011-01-12 17:41:28 +1100173#define HMT_EXTRA_HIGH or 7,7,7 # power7 only
Kumar Gala5f7c6902005-09-09 15:02:25 -0500174
Michael Neulingd72be892012-06-25 13:33:15 +0000175#ifdef CONFIG_PPC64
176#define ULONG_SIZE 8
177#else
178#define ULONG_SIZE 4
179#endif
Michael Neuling0b7673c2012-06-25 13:33:23 +0000180#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
181#define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
Michael Neulingd72be892012-06-25 13:33:15 +0000182
Arnd Bergmann88ced032005-12-16 22:43:46 +0100183#ifdef __KERNEL__
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000184#ifdef CONFIG_PPC64
185
Michael Neuling44ce6a52012-06-25 13:33:14 +0000186#define STACKFRAMESIZE 256
Michael Neuling0b7673c2012-06-25 13:33:23 +0000187#define __STK_REG(i) (112 + ((i)-14)*8)
188#define STK_REG(i) __STK_REG(__REG_##i)
Michael Neuling44ce6a52012-06-25 13:33:14 +0000189
Michael Ellermanf55d9662016-06-06 22:26:10 +0530190#ifdef PPC64_ELF_ABI_v2
Anton Blanchard64031052014-03-10 10:52:17 +1100191#define STK_GOT 24
Anton Blanchardb37c10d2014-02-04 16:09:02 +1100192#define __STK_PARAM(i) (32 + ((i)-3)*8)
193#else
Anton Blanchard64031052014-03-10 10:52:17 +1100194#define STK_GOT 40
Michael Neuling0b7673c2012-06-25 13:33:23 +0000195#define __STK_PARAM(i) (48 + ((i)-3)*8)
Anton Blanchardb37c10d2014-02-04 16:09:02 +1100196#endif
Michael Neuling0b7673c2012-06-25 13:33:23 +0000197#define STK_PARAM(i) __STK_PARAM(__REG_##i)
Michael Neuling44ce6a52012-06-25 13:33:14 +0000198
Michael Ellermanf55d9662016-06-06 22:26:10 +0530199#ifdef PPC64_ELF_ABI_v2
Anton Blanchard7167af72014-02-04 16:07:20 +1100200
201#define _GLOBAL(name) \
Anton Blanchard7167af72014-02-04 16:07:20 +1100202 .align 2 ; \
203 .type name,@function; \
204 .globl name; \
205name:
206
Anton Blanchard169c7ce2014-04-03 16:01:11 +1100207#define _GLOBAL_TOC(name) \
Anton Blanchard169c7ce2014-04-03 16:01:11 +1100208 .align 2 ; \
209 .type name,@function; \
210 .globl name; \
211name: \
2120: addis r2,r12,(.TOC.-0b)@ha; \
213 addi r2,r2,(.TOC.-0b)@l; \
214 .localentry name,.-name
215
Anton Blanchard7167af72014-02-04 16:07:20 +1100216#define DOTSYM(a) a
217
218#else
219
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000220#define XGLUE(a,b) a##b
221#define GLUE(a,b) XGLUE(a,b)
222
223#define _GLOBAL(name) \
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000224 .align 2 ; \
225 .globl name; \
226 .globl GLUE(.,name); \
Michael Ellermanbea2dcc2016-09-15 10:40:20 +1000227 .pushsection ".opd","aw"; \
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000228name: \
229 .quad GLUE(.,name); \
230 .quad .TOC.@tocbase; \
231 .quad 0; \
Michael Ellermanbea2dcc2016-09-15 10:40:20 +1000232 .popsection; \
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000233 .type GLUE(.,name),@function; \
234GLUE(.,name):
235
Anton Blanchard169c7ce2014-04-03 16:01:11 +1100236#define _GLOBAL_TOC(name) _GLOBAL(name)
237
Anton Blanchardc1fb0192014-02-04 16:07:01 +1100238#define DOTSYM(a) GLUE(.,a)
239
Anton Blanchard7167af72014-02-04 16:07:20 +1100240#endif
241
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000242#else /* 32-bit */
243
Kumar Gala748a7682007-09-13 15:42:35 -0500244#define _ENTRY(n) \
245 .globl n; \
246n:
247
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000248#define _GLOBAL(n) \
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000249 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
250 .globl n; \
251n:
252
Alexander Graf9715a2e2014-06-26 13:19:40 +0200253#define _GLOBAL_TOC(name) _GLOBAL(name)
254
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000255#endif
256
Nicholas Piggin6f698df2016-09-16 20:48:17 +1000257/*
258 * __kprobes (the C annotation) puts the symbol into the .kprobes.text
259 * section, which gets emitted at the end of regular text.
260 *
261 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
262 * a blacklist. The former is for core kprobe functions/data, the
263 * latter is for those that incdentially must be excluded from probing
264 * and allows them to be linked at more optimal location within text.
265 */
Nicholas Pigginc0a51492016-10-13 13:07:14 +1100266#ifdef CONFIG_KPROBES
Nicholas Piggin6f698df2016-09-16 20:48:17 +1000267#define _ASM_NOKPROBE_SYMBOL(entry) \
268 .pushsection "_kprobe_blacklist","aw"; \
269 PPC_LONG (entry) ; \
270 .popsection
Nicholas Pigginc0a51492016-10-13 13:07:14 +1100271#else
272#define _ASM_NOKPROBE_SYMBOL(entry)
273#endif
Nicholas Piggin6f698df2016-09-16 20:48:17 +1000274
Anton Blanchard151f2512016-07-01 08:19:44 +1000275#define FUNC_START(name) _GLOBAL(name)
276#define FUNC_END(name)
277
Kumar Gala5f7c6902005-09-09 15:02:25 -0500278/*
David Gibsone58c3492006-01-13 14:56:25 +1100279 * LOAD_REG_IMMEDIATE(rn, expr)
280 * Loads the value of the constant expression 'expr' into register 'rn'
281 * using immediate instructions only. Use this when it's important not
282 * to reference other data (i.e. on ppc64 when the TOC pointer is not
Paul Mackerrase31aa452008-08-30 11:41:12 +1000283 * valid) and when 'expr' is a constant or absolute address.
Kumar Gala5f7c6902005-09-09 15:02:25 -0500284 *
David Gibsone58c3492006-01-13 14:56:25 +1100285 * LOAD_REG_ADDR(rn, name)
286 * Loads the address of label 'name' into register 'rn'. Use this when
287 * you don't particularly need immediate instructions only, but you need
288 * the whole address in one register (e.g. it's a structure address and
289 * you want to access various offsets within it). On ppc32 this is
290 * identical to LOAD_REG_IMMEDIATE.
291 *
Kevin Hao1c49abe2013-12-24 15:12:05 +0800292 * LOAD_REG_ADDR_PIC(rn, name)
293 * Loads the address of label 'name' into register 'run'. Use this when
294 * the kernel doesn't run at the linked or relocated address. Please
295 * note that this macro will clobber the lr register.
296 *
David Gibsone58c3492006-01-13 14:56:25 +1100297 * LOAD_REG_ADDRBASE(rn, name)
298 * ADDROFF(name)
299 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
300 * register 'rn'. ADDROFF(name) returns the remainder of the address as
301 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
302 * in size, so is suitable for use directly as an offset in load and store
303 * instructions. Use this when loading/storing a single word or less as:
304 * LOAD_REG_ADDRBASE(rX, name)
305 * ld rY,ADDROFF(name)(rX)
Kumar Gala5f7c6902005-09-09 15:02:25 -0500306 */
Kevin Hao1c49abe2013-12-24 15:12:05 +0800307
308/* Be careful, this will clobber the lr register. */
309#define LOAD_REG_ADDR_PIC(reg, name) \
310 bl 0f; \
3110: mflr reg; \
312 addis reg,reg,(name - 0b)@ha; \
313 addi reg,reg,(name - 0b)@l;
314
Kumar Gala5f7c6902005-09-09 15:02:25 -0500315#ifdef __powerpc64__
Guenter Roeck7998eb32014-05-15 09:33:42 -0700316#ifdef HAVE_AS_ATHIGH
317#define __AS_ATHIGH high
318#else
319#define __AS_ATHIGH h
320#endif
David Gibsone58c3492006-01-13 14:56:25 +1100321#define LOAD_REG_IMMEDIATE(reg,expr) \
Michael Neuling564aa5c2012-06-25 13:33:09 +0000322 lis reg,(expr)@highest; \
323 ori reg,reg,(expr)@higher; \
324 rldicr reg,reg,32,31; \
Guenter Roeck7998eb32014-05-15 09:33:42 -0700325 oris reg,reg,(expr)@__AS_ATHIGH; \
Michael Neuling564aa5c2012-06-25 13:33:09 +0000326 ori reg,reg,(expr)@l;
Kumar Gala5f7c6902005-09-09 15:02:25 -0500327
David Gibsone58c3492006-01-13 14:56:25 +1100328#define LOAD_REG_ADDR(reg,name) \
Michael Neuling564aa5c2012-06-25 13:33:09 +0000329 ld reg,name@got(r2)
Kumar Gala5f7c6902005-09-09 15:02:25 -0500330
David Gibsone58c3492006-01-13 14:56:25 +1100331#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
332#define ADDROFF(name) 0
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000333
Paul Mackerrasf78541d2005-10-28 22:53:37 +1000334/* offsets for stack frame layout */
335#define LRSAVE 16
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000336
337#else /* 32-bit */
Stephen Rothwell70620182005-10-12 17:44:55 +1000338
David Gibsone58c3492006-01-13 14:56:25 +1100339#define LOAD_REG_IMMEDIATE(reg,expr) \
Michael Neuling564aa5c2012-06-25 13:33:09 +0000340 lis reg,(expr)@ha; \
341 addi reg,reg,(expr)@l;
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000342
David Gibsone58c3492006-01-13 14:56:25 +1100343#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
344
Michael Neuling564aa5c2012-06-25 13:33:09 +0000345#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
David Gibsone58c3492006-01-13 14:56:25 +1100346#define ADDROFF(name) name@l
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000347
Paul Mackerrasf78541d2005-10-28 22:53:37 +1000348/* offsets for stack frame layout */
349#define LRSAVE 4
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000350
Kumar Gala5f7c6902005-09-09 15:02:25 -0500351#endif
352
353/* various errata or part fixups */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354#ifdef CONFIG_PPC601_SYNC_FIX
355#define SYNC \
356BEGIN_FTR_SECTION \
357 sync; \
358 isync; \
359END_FTR_SECTION_IFSET(CPU_FTR_601)
360#define SYNC_601 \
361BEGIN_FTR_SECTION \
362 sync; \
363END_FTR_SECTION_IFSET(CPU_FTR_601)
364#define ISYNC_601 \
365BEGIN_FTR_SECTION \
366 isync; \
367END_FTR_SECTION_IFSET(CPU_FTR_601)
368#else
369#define SYNC
370#define SYNC_601
371#define ISYNC_601
372#endif
373
Scott Woodd52459c2013-07-23 20:21:11 -0500374#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000375#define MFTB(dest) \
Scott Woodbeb2dc02013-08-20 19:33:12 -050037690: mfspr dest, SPRN_TBRL; \
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000377BEGIN_FTR_SECTION_NESTED(96); \
378 cmpwi dest,0; \
379 beq- 90b; \
380END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
LEROY Christopheae2163b2013-11-22 17:57:31 +0100381#elif defined(CONFIG_8xx)
382#define MFTB(dest) mftb dest
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000383#else
Scott Woodbeb2dc02013-08-20 19:33:12 -0500384#define MFTB(dest) mfspr dest, SPRN_TBRL
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000385#endif
Kumar Gala5f7c6902005-09-09 15:02:25 -0500386
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387#ifndef CONFIG_SMP
388#define TLBSYNC
389#else /* CONFIG_SMP */
390/* tlbsync is not implemented on 601 */
391#define TLBSYNC \
392BEGIN_FTR_SECTION \
393 tlbsync; \
394 sync; \
395END_FTR_SECTION_IFCLR(CPU_FTR_601)
396#endif
397
Anton Blanchard694caf02012-04-18 02:21:52 +0000398#ifdef CONFIG_PPC64
399#define MTOCRF(FXM, RS) \
400 BEGIN_FTR_SECTION_NESTED(848); \
Michael Neuling86e32fd2012-06-25 13:33:16 +0000401 mtcrf (FXM), RS; \
Anton Blanchard694caf02012-04-18 02:21:52 +0000402 FTR_SECTION_ELSE_NESTED(848); \
Michael Neuling86e32fd2012-06-25 13:33:16 +0000403 mtocrf (FXM), RS; \
Anton Blanchard694caf02012-04-18 02:21:52 +0000404 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
405#endif
406
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407/*
408 * This instruction is not implemented on the PPC 603 or 601; however, on
409 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
410 * All of these instructions exist in the 8xx, they have magical powers,
411 * and they must be used.
412 */
413
414#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
415#define tlbia \
416 li r4,1024; \
417 mtctr r4; \
418 lis r4,KERNELBASE@h; \
Russell Curreye3824e42016-03-02 17:12:45 +1100419 .machine push; \
420 .machine "power4"; \
Linus Torvalds1da177e2005-04-16 15:20:36 -07004210: tlbie r4; \
Russell Curreye3824e42016-03-02 17:12:45 +1100422 .machine pop; \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423 addi r4,r4,0x1000; \
424 bdnz 0b
425#endif
426
Kumar Gala5f7c6902005-09-09 15:02:25 -0500427
Kumar Gala5f7c6902005-09-09 15:02:25 -0500428#ifdef CONFIG_IBM440EP_ERR42
429#define PPC440EP_ERR42 isync
430#else
431#define PPC440EP_ERR42
432#endif
433
Michael Neulinga5153482013-05-29 19:34:27 +0000434/* The following stops all load and store data streams associated with stream
435 * ID (ie. streams created explicitly). The embedded and server mnemonics for
436 * dcbt are different so we use machine "power4" here explicitly.
437 */
438#define DCBT_STOP_ALL_STREAM_IDS(scratch) \
439.machine push ; \
440.machine "power4" ; \
441 lis scratch,0x60000000@h; \
442 dcbt r0,scratch,0b01010; \
443.machine pop
444
Benjamin Herrenschmidt44c58cc2009-07-23 23:15:20 +0000445/*
446 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
447 * keep the address intact to be compatible with code shared with
448 * 32-bit classic.
449 *
450 * On the other hand, I find it useful to have them behave as expected
451 * by their name (ie always do the addition) on 64-bit BookE
452 */
453#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
Paul Mackerras63162222005-10-27 22:44:39 +1000454#define toreal(rd)
455#define fromreal(rd)
456
Roland McGrath2ca76332008-05-11 10:40:47 +1000457/*
458 * We use addis to ensure compatibility with the "classic" ppc versions of
459 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
460 * converting the address in r0, and so this version has to do that too
461 * (i.e. set register rd to 0 when rs == 0).
462 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463#define tophys(rd,rs) \
464 addis rd,rs,0
465
466#define tovirt(rd,rs) \
467 addis rd,rs,0
468
Kumar Gala5f7c6902005-09-09 15:02:25 -0500469#elif defined(CONFIG_PPC64)
Paul Mackerras63162222005-10-27 22:44:39 +1000470#define toreal(rd) /* we can access c000... in real mode */
471#define fromreal(rd)
472
Kumar Gala5f7c6902005-09-09 15:02:25 -0500473#define tophys(rd,rs) \
Paul Mackerras63162222005-10-27 22:44:39 +1000474 clrldi rd,rs,2
Kumar Gala5f7c6902005-09-09 15:02:25 -0500475
476#define tovirt(rd,rs) \
Paul Mackerras63162222005-10-27 22:44:39 +1000477 rotldi rd,rs,16; \
478 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
479 rotldi rd,rd,48
Kumar Gala5f7c6902005-09-09 15:02:25 -0500480#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481/*
482 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
483 * physical base address of RAM at compile time.
484 */
Paul Mackerras63162222005-10-27 22:44:39 +1000485#define toreal(rd) tophys(rd,rd)
486#define fromreal(rd) tovirt(rd,rd)
487
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488#define tophys(rd,rs) \
Dale Farnsworthccdcef72008-12-17 10:09:13 +00004890: addis rd,rs,-PAGE_OFFSET@h; \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490 .section ".vtop_fixup","aw"; \
491 .align 1; \
492 .long 0b; \
493 .previous
494
495#define tovirt(rd,rs) \
Dale Farnsworthccdcef72008-12-17 10:09:13 +00004960: addis rd,rs,PAGE_OFFSET@h; \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 .section ".ptov_fixup","aw"; \
498 .align 1; \
499 .long 0b; \
500 .previous
Kumar Gala5f7c6902005-09-09 15:02:25 -0500501#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502
Benjamin Herrenschmidt44c58cc2009-07-23 23:15:20 +0000503#ifdef CONFIG_PPC_BOOK3S_64
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000504#define RFI rfid
505#define MTMSRD(r) mtmsrd r
Benjamin Herrenschmidtb38c77d2012-07-04 14:49:12 +1000506#define MTMSR_EERI(reg) mtmsrd reg,1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508#ifndef CONFIG_40x
509#define RFI rfi
510#else
511#define RFI rfi; b . /* Prevent prefetch past rfi */
512#endif
513#define MTMSRD(r) mtmsr r
Benjamin Herrenschmidtb38c77d2012-07-04 14:49:12 +1000514#define MTMSR_EERI(reg) mtmsr reg
Matt Porterc9cf73a2005-07-31 22:34:52 -0700515#endif
516
Arnd Bergmann88ced032005-12-16 22:43:46 +0100517#endif /* __KERNEL__ */
518
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519/* The boring bits... */
520
521/* Condition Register Bit Fields */
522
523#define cr0 0
524#define cr1 1
525#define cr2 2
526#define cr3 3
527#define cr4 4
528#define cr5 5
529#define cr6 6
530#define cr7 7
531
532
Michael Neuling9a13a522012-06-25 13:33:12 +0000533/*
534 * General Purpose Registers (GPRs)
535 *
536 * The lower case r0-r31 should be used in preference to the upper
537 * case R0-R31 as they provide more error checking in the assembler.
538 * Use R0-31 only when really nessesary.
539 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540
Michael Neuling9a13a522012-06-25 13:33:12 +0000541#define r0 %r0
542#define r1 %r1
543#define r2 %r2
544#define r3 %r3
545#define r4 %r4
546#define r5 %r5
547#define r6 %r6
548#define r7 %r7
549#define r8 %r8
550#define r9 %r9
551#define r10 %r10
552#define r11 %r11
553#define r12 %r12
554#define r13 %r13
555#define r14 %r14
556#define r15 %r15
557#define r16 %r16
558#define r17 %r17
559#define r18 %r18
560#define r19 %r19
561#define r20 %r20
562#define r21 %r21
563#define r22 %r22
564#define r23 %r23
565#define r24 %r24
566#define r25 %r25
567#define r26 %r26
568#define r27 %r27
569#define r28 %r28
570#define r29 %r29
571#define r30 %r30
572#define r31 %r31
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573
574
575/* Floating Point Registers (FPRs) */
576
577#define fr0 0
578#define fr1 1
579#define fr2 2
580#define fr3 3
581#define fr4 4
582#define fr5 5
583#define fr6 6
584#define fr7 7
585#define fr8 8
586#define fr9 9
587#define fr10 10
588#define fr11 11
589#define fr12 12
590#define fr13 13
591#define fr14 14
592#define fr15 15
593#define fr16 16
594#define fr17 17
595#define fr18 18
596#define fr19 19
597#define fr20 20
598#define fr21 21
599#define fr22 22
600#define fr23 23
601#define fr24 24
602#define fr25 25
603#define fr26 26
604#define fr27 27
605#define fr28 28
606#define fr29 29
607#define fr30 30
608#define fr31 31
609
Kumar Gala5f7c6902005-09-09 15:02:25 -0500610/* AltiVec Registers (VPRs) */
611
Anton Blanchardc2ce6f92015-02-10 09:51:22 +1100612#define v0 0
613#define v1 1
614#define v2 2
615#define v3 3
616#define v4 4
617#define v5 5
618#define v6 6
619#define v7 7
620#define v8 8
621#define v9 9
622#define v10 10
623#define v11 11
624#define v12 12
625#define v13 13
626#define v14 14
627#define v15 15
628#define v16 16
629#define v17 17
630#define v18 18
631#define v19 19
632#define v20 20
633#define v21 21
634#define v22 22
635#define v23 23
636#define v24 24
637#define v25 25
638#define v26 26
639#define v27 27
640#define v28 28
641#define v29 29
642#define v30 30
643#define v31 31
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644
Michael Neuling72ffff52008-06-25 14:07:18 +1000645/* VSX Registers (VSRs) */
646
Anton Blancharddf99e6e2015-02-10 09:51:23 +1100647#define vs0 0
648#define vs1 1
649#define vs2 2
650#define vs3 3
651#define vs4 4
652#define vs5 5
653#define vs6 6
654#define vs7 7
655#define vs8 8
656#define vs9 9
657#define vs10 10
658#define vs11 11
659#define vs12 12
660#define vs13 13
661#define vs14 14
662#define vs15 15
663#define vs16 16
664#define vs17 17
665#define vs18 18
666#define vs19 19
667#define vs20 20
668#define vs21 21
669#define vs22 22
670#define vs23 23
671#define vs24 24
672#define vs25 25
673#define vs26 26
674#define vs27 27
675#define vs28 28
676#define vs29 29
677#define vs30 30
678#define vs31 31
679#define vs32 32
680#define vs33 33
681#define vs34 34
682#define vs35 35
683#define vs36 36
684#define vs37 37
685#define vs38 38
686#define vs39 39
687#define vs40 40
688#define vs41 41
689#define vs42 42
690#define vs43 43
691#define vs44 44
692#define vs45 45
693#define vs46 46
694#define vs47 47
695#define vs48 48
696#define vs49 49
697#define vs50 50
698#define vs51 51
699#define vs52 52
700#define vs53 53
701#define vs54 54
702#define vs55 55
703#define vs56 56
704#define vs57 57
705#define vs58 58
706#define vs59 59
707#define vs60 60
708#define vs61 61
709#define vs62 62
710#define vs63 63
Michael Neuling72ffff52008-06-25 14:07:18 +1000711
Kumar Gala5f7c6902005-09-09 15:02:25 -0500712/* SPE Registers (EVPRs) */
713
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714#define evr0 0
715#define evr1 1
716#define evr2 2
717#define evr3 3
718#define evr4 4
719#define evr5 5
720#define evr6 6
721#define evr7 7
722#define evr8 8
723#define evr9 9
724#define evr10 10
725#define evr11 11
726#define evr12 12
727#define evr13 13
728#define evr14 14
729#define evr15 15
730#define evr16 16
731#define evr17 17
732#define evr18 18
733#define evr19 19
734#define evr20 20
735#define evr21 21
736#define evr22 22
737#define evr23 23
738#define evr24 24
739#define evr25 25
740#define evr26 26
741#define evr27 27
742#define evr28 28
743#define evr29 29
744#define evr30 30
745#define evr31 31
746
747/* some stab codes */
748#define N_FUN 36
749#define N_RSYM 64
750#define N_SLINE 68
751#define N_SO 100
Kumar Gala5f7c6902005-09-09 15:02:25 -0500752
Benjamin Herrenschmidt5c0484e2013-09-23 12:04:45 +1000753/*
754 * Create an endian fixup trampoline
755 *
756 * This starts with a "tdi 0,0,0x48" instruction which is
757 * essentially a "trap never", and thus akin to a nop.
758 *
759 * The opcode for this instruction read with the wrong endian
760 * however results in a b . + 8
761 *
762 * So essentially we use that trick to execute the following
763 * trampoline in "reverse endian" if we are running with the
764 * MSR_LE bit set the "wrong" way for whatever endianness the
765 * kernel is built for.
766 */
Kumar Gala5f7c6902005-09-09 15:02:25 -0500767
Benjamin Herrenschmidt5c0484e2013-09-23 12:04:45 +1000768#ifdef CONFIG_PPC_BOOK3E
769#define FIXUP_ENDIAN
770#else
771#define FIXUP_ENDIAN \
772 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
773 b $+36; /* Skip trampoline if endian is good */ \
774 .long 0x05009f42; /* bcl 20,31,$+4 */ \
775 .long 0xa602487d; /* mflr r10 */ \
776 .long 0x1c004a39; /* addi r10,r10,28 */ \
777 .long 0xa600607d; /* mfmsr r11 */ \
778 .long 0x01006b69; /* xori r11,r11,1 */ \
779 .long 0xa6035a7d; /* mtsrr0 r10 */ \
780 .long 0xa6037b7d; /* mtsrr1 r11 */ \
781 .long 0x2400004c /* rfid */
782#endif /* !CONFIG_PPC_BOOK3E */
Michael Ellermane3f2c6c2016-10-14 15:58:28 +1100783
Benjamin Herrenschmidt5c0484e2013-09-23 12:04:45 +1000784#endif /* __ASSEMBLY__ */
Michael Ellermane3f2c6c2016-10-14 15:58:28 +1100785
Nicholas Piggin24bfa6a2016-10-13 16:42:53 +1100786/*
787 * Helper macro for exception table entries
788 */
789#define EX_TABLE(_fault, _target) \
790 stringify_in_c(.section __ex_table,"a";)\
Nicholas Piggin61a92f72016-10-14 16:47:31 +1100791 stringify_in_c(.balign 4;) \
792 stringify_in_c(.long (_fault) - . ;) \
793 stringify_in_c(.long (_target) - . ;) \
Nicholas Piggin24bfa6a2016-10-13 16:42:53 +1100794 stringify_in_c(.previous)
795
Kumar Gala5f7c6902005-09-09 15:02:25 -0500796#endif /* _ASM_POWERPC_PPC_ASM_H */