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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef _IMX_REGS_H
2#define _IMX_REGS_H
3/* ------------------------------------------------------------------------
4 * Motorola IMX system registers
5 * ------------------------------------------------------------------------
6 *
7 */
8
9/*
10 * Register BASEs, based on OFFSETs
11 *
12 */
13#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
14#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
15#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
16#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
17#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
18#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
19#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
20#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
21#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
22#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
23#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
24#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
25#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
26#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
27#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
28#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
29#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
30#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
31#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
32#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
33#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
34#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
35#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
36#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
37#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
38#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
39#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
40#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
41
42/* PLL registers */
43#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
44#define CSCR_SYSTEM_SEL (1<<16)
45
46#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
47#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
48#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
49#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
50#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
51
52#define CSCR_MPLL_RESTART (1<<21)
53
54/*
55 * GPIO Module and I/O Multiplexer
56 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
57 */
58#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
59#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
60#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
61#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
62#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
63#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
64#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
65#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
66#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
67#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
68#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
69#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
70#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
71#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
72#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
73#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
74#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
75
76#define GPIO_PIN_MASK 0x1f
77#define GPIO_PORT_MASK (0x3 << 5)
78
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +010079#define GPIO_PORT_SHIFT 5
Linus Torvalds1da177e2005-04-16 15:20:36 -070080#define GPIO_PORTA (0<<5)
81#define GPIO_PORTB (1<<5)
82#define GPIO_PORTC (2<<5)
83#define GPIO_PORTD (3<<5)
84
85#define GPIO_OUT (1<<7)
86#define GPIO_IN (0<<7)
87#define GPIO_PUEN (1<<8)
88
89#define GPIO_PF (0<<9)
90#define GPIO_AF (1<<9)
91
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +010092#define GPIO_OCR_SHIFT 10
Linus Torvalds1da177e2005-04-16 15:20:36 -070093#define GPIO_OCR_MASK (3<<10)
94#define GPIO_AIN (0<<10)
95#define GPIO_BIN (1<<10)
96#define GPIO_CIN (2<<10)
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +010097#define GPIO_DR (3<<10)
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +010099#define GPIO_AOUT_SHIFT 12
100#define GPIO_AOUT_MASK (3<<12)
101#define GPIO_AOUT (0<<12)
102#define GPIO_AOUT_ISR (1<<12)
103#define GPIO_AOUT_0 (2<<12)
104#define GPIO_AOUT_1 (3<<12)
105
106#define GPIO_BOUT_SHIFT 14
107#define GPIO_BOUT_MASK (3<<14)
108#define GPIO_BOUT (0<<14)
109#define GPIO_BOUT_ISR (1<<14)
110#define GPIO_BOUT_0 (2<<14)
111#define GPIO_BOUT_1 (3<<14)
112
113#define GPIO_GIUS (1<<16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
115/* assignements for GPIO alternate/primary functions */
116
117/* FIXME: This list is not completed. The correct directions are
118 * missing on some (many) pins
119 */
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +0100120#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +0100122#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
124#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
125#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
126#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
127#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
128#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
129#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
130#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
131#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
132#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
133#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
134#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
135#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
136#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
137#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
138#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
139#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +0100140#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
142#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
143#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
144#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
145#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
146#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
147#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
148#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
149#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
150#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
151#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
152#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
153#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
154#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
155#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
156#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
157#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
158#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
159#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
160#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
161#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
162#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
163#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
164#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
165#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
166#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
167#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
168#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
169#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 )
170#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
171#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 )
172#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
173#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
174#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
175#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
176#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
177#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
178#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
179#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
180#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
181#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
182#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
183#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
184#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
185#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
186#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
187#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
188#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
189#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
190#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
191#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
192#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
193#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
194#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
195#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
196#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
197#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
198#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
199#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
200#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
201#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
202#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
203#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
204#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
205#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
206#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
207#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +0100208#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
209#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
210#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
211#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
212#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
213#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
214#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
215#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
217#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
Sascha Hauer79d13b62005-10-10 10:17:43 +0100218#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +0100219#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
221#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +0100222#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
224#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +0100225#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
227#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +0100228#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
230#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
231#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
232#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
233#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
234#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
235#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
236#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
237#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
238#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
239#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
240#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
241#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
242#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
243#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
244#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
245#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
246#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
247#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
248#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
249#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
Sascha Hauer0a5b0aa2005-10-04 23:17:52 +0100250#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251
252/*
Sascha Hauerd7def6c2005-05-10 19:01:35 +0100253 * PWM controller
254 */
255#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */
256#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */
257#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */
258#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */
259
260#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */
261#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */
262#define PWMC_SWR (0x01<<16) /* Software Reset */
263#define PWMC_CLKSRC (0x01<<15) /* Clock Source */
264#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */
265#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */
266#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */
267#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */
268#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */
269#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */
270#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */
271
272#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */
273#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */
274#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */
275
276/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 * DMA Controller
278 */
279#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
280#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
281#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
282#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
283#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
284#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
285#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
286#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
287#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
288#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
289#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
290#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
291#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
292#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
293#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
294#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
295#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
296#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
297#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
298#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
299#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
300#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
301
302#define DCR_DRST (1<<1)
303#define DCR_DEN (1<<0)
304#define DBTOCR_EN (1<<15)
305#define DBTOCR_CNT(x) ((x) & 0x7fff )
306#define CNTR_CNT(x) ((x) & 0xffffff )
307#define CCR_DMOD_LINEAR ( 0x0 << 12 )
308#define CCR_DMOD_2D ( 0x1 << 12 )
309#define CCR_DMOD_FIFO ( 0x2 << 12 )
310#define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
311#define CCR_SMOD_LINEAR ( 0x0 << 10 )
312#define CCR_SMOD_2D ( 0x1 << 10 )
313#define CCR_SMOD_FIFO ( 0x2 << 10 )
314#define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
315#define CCR_MDIR_DEC (1<<9)
316#define CCR_MSEL_B (1<<8)
317#define CCR_DSIZ_32 ( 0x0 << 6 )
318#define CCR_DSIZ_8 ( 0x1 << 6 )
319#define CCR_DSIZ_16 ( 0x2 << 6 )
320#define CCR_SSIZ_32 ( 0x0 << 4 )
321#define CCR_SSIZ_8 ( 0x1 << 4 )
322#define CCR_SSIZ_16 ( 0x2 << 4 )
323#define CCR_REN (1<<3)
324#define CCR_RPT (1<<2)
325#define CCR_FRC (1<<1)
326#define CCR_CEN (1<<0)
327#define RTOR_EN (1<<15)
328#define RTOR_CLK (1<<14)
329#define RTOR_PSC (1<<13)
330
331/*
332 * Interrupt controller
333 */
334
335#define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00)
336#define INTCNTL_FIAD (1<<19)
337#define INTCNTL_NIAD (1<<20)
338
339#define IMX_NIMASK __REG(IMX_AITC_BASE+0x04)
340#define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08)
341#define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c)
342#define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10)
343#define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14)
344
345/*
346 * General purpose timers
347 */
348#define IMX_TCTL(x) __REG( 0x00 + (x))
349#define TCTL_SWR (1<<15)
350#define TCTL_FRR (1<<8)
351#define TCTL_CAP_RIS (1<<6)
352#define TCTL_CAP_FAL (2<<6)
353#define TCTL_CAP_RIS_FAL (3<<6)
354#define TCTL_OM (1<<5)
355#define TCTL_IRQEN (1<<4)
356#define TCTL_CLK_PCLK1 (1<<1)
357#define TCTL_CLK_PCLK1_16 (2<<1)
358#define TCTL_CLK_TIN (3<<1)
359#define TCTL_CLK_32 (4<<1)
360#define TCTL_TEN (1<<0)
361
362#define IMX_TPRER(x) __REG( 0x04 + (x))
363#define IMX_TCMP(x) __REG( 0x08 + (x))
364#define IMX_TCR(x) __REG( 0x0C + (x))
365#define IMX_TCN(x) __REG( 0x10 + (x))
366#define IMX_TSTAT(x) __REG( 0x14 + (x))
367#define TSTAT_CAPT (1<<1)
368#define TSTAT_COMP (1<<0)
369
370/*
371 * LCD Controller
372 */
373
374#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
375
376#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
377#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
378#define SIZE_YMAX(y) ( (y) & 0x1ff )
379
380#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
381#define VPW_VPW(x) ( (x) & 0x3ff )
382
383#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
384#define CPOS_CC1 (1<<31)
385#define CPOS_CC0 (1<<30)
386#define CPOS_OP (1<<28)
387#define CPOS_CXP(x) (((x) & 3ff) << 16)
388#define CPOS_CYP(y) ((y) & 0x1ff)
389
390#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
391#define LCWHB_BK_EN (1<<31)
392#define LCWHB_CW(w) (((w) & 0x1f) << 24)
393#define LCWHB_CH(h) (((h) & 0x1f) << 16)
394#define LCWHB_BD(x) ((x) & 0xff)
395
396#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
397#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
398#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
399#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
400
401#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
402#define PCR_TFT (1<<31)
403#define PCR_COLOR (1<<30)
404#define PCR_PBSIZ_1 (0<<28)
405#define PCR_PBSIZ_2 (1<<28)
406#define PCR_PBSIZ_4 (2<<28)
407#define PCR_PBSIZ_8 (3<<28)
408#define PCR_BPIX_1 (0<<25)
409#define PCR_BPIX_2 (1<<25)
410#define PCR_BPIX_4 (2<<25)
411#define PCR_BPIX_8 (3<<25)
412#define PCR_BPIX_12 (4<<25)
413#define PCR_BPIX_16 (4<<25)
414#define PCR_PIXPOL (1<<24)
415#define PCR_FLMPOL (1<<23)
416#define PCR_LPPOL (1<<22)
417#define PCR_CLKPOL (1<<21)
418#define PCR_OEPOL (1<<20)
419#define PCR_SCLKIDLE (1<<19)
420#define PCR_END_SEL (1<<18)
421#define PCR_END_BYTE_SWAP (1<<17)
422#define PCR_REV_VS (1<<16)
423#define PCR_ACD_SEL (1<<15)
424#define PCR_ACD(x) (((x) & 0x7f) << 8)
425#define PCR_SCLK_SEL (1<<7)
426#define PCR_SHARP (1<<6)
427#define PCR_PCD(x) ((x) & 0x3f)
428
429#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
430#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
431#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
432#define HCR_H_WAIT_2(x) ((x) & 0xff)
433
434#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
435#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
436#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
437#define VCR_V_WAIT_2(x) ((x) & 0xff)
438
439#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
440#define POS_POS(x) ((x) & 1f)
441
442#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
443#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
444#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
445#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
446#define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
447#define LSCR1_GRAY1(x) (((x) & 0xf))
448
449#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
450#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
451#define PWMR_LDMSK (1<<15)
452#define PWMR_SCR1 (1<<10)
453#define PWMR_SCR0 (1<<9)
454#define PWMR_CC_EN (1<<8)
455#define PWMR_PW(x) ((x) & 0xff)
456
457#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
458#define DMACR_BURST (1<<31)
459#define DMACR_HM(x) (((x) & 0xf) << 16)
460#define DMACR_TM(x) ((x) &0xf)
461
462#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
463#define RMCR_LCDC_EN (1<<1)
464#define RMCR_SELF_REF (1<<0)
465
466#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
467#define LCDICR_INT_SYN (1<<2)
468#define LCDICR_INT_CON (1)
469
470#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
471#define LCDISR_UDR_ERR (1<<3)
472#define LCDISR_ERR_RES (1<<2)
473#define LCDISR_EOF (1<<1)
474#define LCDISR_BOF (1<<0)
475
476/*
477 * UART Module. Takes the UART base address as argument
478 */
479#define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */
480#define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */
481#define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */
482#define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */
483#define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */
484#define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */
485#define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */
486#define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */
487#define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */
488#define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */
489#define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */
490#define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */
491#define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */
492#define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */
493#define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */
494#define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */
495#define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */
496#define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */
497#define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */
498#define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */
499#define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */
500#define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */
501#define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */
502
503/* UART Control Register Bit Fields.*/
504#define URXD_CHARRDY (1<<15)
505#define URXD_ERR (1<<14)
506#define URXD_OVRRUN (1<<13)
507#define URXD_FRMERR (1<<12)
508#define URXD_BRK (1<<11)
509#define URXD_PRERR (1<<10)
510#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
511#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
512#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
513#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
514#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
515#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
516#define UCR1_IREN (1<<7) /* Infrared interface enable */
517#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
518#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
519#define UCR1_SNDBRK (1<<4) /* Send break */
520#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
521#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
522#define UCR1_DOZE (1<<1) /* Doze */
523#define UCR1_UARTEN (1<<0) /* UART enabled */
524#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
525#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
526#define UCR2_CTSC (1<<13) /* CTS pin control */
527#define UCR2_CTS (1<<12) /* Clear to send */
528#define UCR2_ESCEN (1<<11) /* Escape enable */
529#define UCR2_PREN (1<<8) /* Parity enable */
530#define UCR2_PROE (1<<7) /* Parity odd/even */
531#define UCR2_STPB (1<<6) /* Stop */
532#define UCR2_WS (1<<5) /* Word size */
533#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
534#define UCR2_TXEN (1<<2) /* Transmitter enabled */
535#define UCR2_RXEN (1<<1) /* Receiver enabled */
536#define UCR2_SRST (1<<0) /* SW reset */
537#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
538#define UCR3_PARERREN (1<<12) /* Parity enable */
539#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
540#define UCR3_DSR (1<<10) /* Data set ready */
541#define UCR3_DCD (1<<9) /* Data carrier detect */
542#define UCR3_RI (1<<8) /* Ring indicator */
543#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
544#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
545#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
546#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
547#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
548#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
549#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
550#define UCR3_BPEN (1<<0) /* Preset registers enable */
551#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
552#define UCR4_INVR (1<<9) /* Inverted infrared reception */
553#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
554#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
555#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
556#define UCR4_IRSC (1<<5) /* IR special case */
557#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
558#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
559#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
560#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
561#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
562#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
563#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
564#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
565#define USR1_RTSS (1<<14) /* RTS pin status */
566#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
567#define USR1_RTSD (1<<12) /* RTS delta */
568#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
569#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
570#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
571#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
572#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
573#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
574#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
575#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
576#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
577#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
578#define USR2_IDLE (1<<12) /* Idle condition */
579#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
580#define USR2_WAKE (1<<7) /* Wake */
581#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
582#define USR2_TXDC (1<<3) /* Transmitter complete */
583#define USR2_BRCD (1<<2) /* Break condition */
584#define USR2_ORE (1<<1) /* Overrun error */
585#define USR2_RDR (1<<0) /* Recv data ready */
586#define UTS_FRCPERR (1<<13) /* Force parity error */
587#define UTS_LOOP (1<<12) /* Loop tx and rx */
588#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
589#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
590#define UTS_TXFULL (1<<4) /* TxFIFO full */
591#define UTS_RXFULL (1<<3) /* RxFIFO full */
592#define UTS_SOFTRST (1<<0) /* Software reset */
593
594#endif // _IMX_REGS_H