Shawn Guo | 1772311 | 2012-04-28 13:00:50 +0800 | [diff] [blame] | 1 | /* |
Paul Gortmaker | 37824c1 | 2016-06-25 22:46:51 -0400 | [diff] [blame] | 2 | * Freescale i.MX28 pinctrl driver |
| 3 | * |
| 4 | * Author: Shawn Guo <shawn.guo@linaro.org> |
Shawn Guo | 1772311 | 2012-04-28 13:00:50 +0800 | [diff] [blame] | 5 | * Copyright 2012 Freescale Semiconductor, Inc. |
| 6 | * |
| 7 | * The code contained herein is licensed under the GNU General Public |
| 8 | * License. You may obtain a copy of the GNU General Public License |
| 9 | * Version 2 or later at the following locations: |
| 10 | * |
| 11 | * http://www.opensource.org/licenses/gpl-license.html |
| 12 | * http://www.gnu.org/copyleft/gpl.html |
| 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
Shawn Guo | 1772311 | 2012-04-28 13:00:50 +0800 | [diff] [blame] | 16 | #include <linux/of_device.h> |
| 17 | #include <linux/pinctrl/pinctrl.h> |
| 18 | #include "pinctrl-mxs.h" |
| 19 | |
| 20 | enum imx28_pin_enum { |
| 21 | GPMI_D00 = PINID(0, 0), |
| 22 | GPMI_D01 = PINID(0, 1), |
| 23 | GPMI_D02 = PINID(0, 2), |
| 24 | GPMI_D03 = PINID(0, 3), |
| 25 | GPMI_D04 = PINID(0, 4), |
| 26 | GPMI_D05 = PINID(0, 5), |
| 27 | GPMI_D06 = PINID(0, 6), |
| 28 | GPMI_D07 = PINID(0, 7), |
| 29 | GPMI_CE0N = PINID(0, 16), |
| 30 | GPMI_CE1N = PINID(0, 17), |
| 31 | GPMI_CE2N = PINID(0, 18), |
| 32 | GPMI_CE3N = PINID(0, 19), |
| 33 | GPMI_RDY0 = PINID(0, 20), |
| 34 | GPMI_RDY1 = PINID(0, 21), |
| 35 | GPMI_RDY2 = PINID(0, 22), |
| 36 | GPMI_RDY3 = PINID(0, 23), |
| 37 | GPMI_RDN = PINID(0, 24), |
| 38 | GPMI_WRN = PINID(0, 25), |
| 39 | GPMI_ALE = PINID(0, 26), |
| 40 | GPMI_CLE = PINID(0, 27), |
| 41 | GPMI_RESETN = PINID(0, 28), |
| 42 | LCD_D00 = PINID(1, 0), |
| 43 | LCD_D01 = PINID(1, 1), |
| 44 | LCD_D02 = PINID(1, 2), |
| 45 | LCD_D03 = PINID(1, 3), |
| 46 | LCD_D04 = PINID(1, 4), |
| 47 | LCD_D05 = PINID(1, 5), |
| 48 | LCD_D06 = PINID(1, 6), |
| 49 | LCD_D07 = PINID(1, 7), |
| 50 | LCD_D08 = PINID(1, 8), |
| 51 | LCD_D09 = PINID(1, 9), |
| 52 | LCD_D10 = PINID(1, 10), |
| 53 | LCD_D11 = PINID(1, 11), |
| 54 | LCD_D12 = PINID(1, 12), |
| 55 | LCD_D13 = PINID(1, 13), |
| 56 | LCD_D14 = PINID(1, 14), |
| 57 | LCD_D15 = PINID(1, 15), |
| 58 | LCD_D16 = PINID(1, 16), |
| 59 | LCD_D17 = PINID(1, 17), |
| 60 | LCD_D18 = PINID(1, 18), |
| 61 | LCD_D19 = PINID(1, 19), |
| 62 | LCD_D20 = PINID(1, 20), |
| 63 | LCD_D21 = PINID(1, 21), |
| 64 | LCD_D22 = PINID(1, 22), |
| 65 | LCD_D23 = PINID(1, 23), |
| 66 | LCD_RD_E = PINID(1, 24), |
| 67 | LCD_WR_RWN = PINID(1, 25), |
| 68 | LCD_RS = PINID(1, 26), |
| 69 | LCD_CS = PINID(1, 27), |
| 70 | LCD_VSYNC = PINID(1, 28), |
| 71 | LCD_HSYNC = PINID(1, 29), |
| 72 | LCD_DOTCLK = PINID(1, 30), |
| 73 | LCD_ENABLE = PINID(1, 31), |
| 74 | SSP0_DATA0 = PINID(2, 0), |
| 75 | SSP0_DATA1 = PINID(2, 1), |
| 76 | SSP0_DATA2 = PINID(2, 2), |
| 77 | SSP0_DATA3 = PINID(2, 3), |
| 78 | SSP0_DATA4 = PINID(2, 4), |
| 79 | SSP0_DATA5 = PINID(2, 5), |
| 80 | SSP0_DATA6 = PINID(2, 6), |
| 81 | SSP0_DATA7 = PINID(2, 7), |
| 82 | SSP0_CMD = PINID(2, 8), |
| 83 | SSP0_DETECT = PINID(2, 9), |
| 84 | SSP0_SCK = PINID(2, 10), |
| 85 | SSP1_SCK = PINID(2, 12), |
| 86 | SSP1_CMD = PINID(2, 13), |
| 87 | SSP1_DATA0 = PINID(2, 14), |
| 88 | SSP1_DATA3 = PINID(2, 15), |
| 89 | SSP2_SCK = PINID(2, 16), |
| 90 | SSP2_MOSI = PINID(2, 17), |
| 91 | SSP2_MISO = PINID(2, 18), |
| 92 | SSP2_SS0 = PINID(2, 19), |
| 93 | SSP2_SS1 = PINID(2, 20), |
| 94 | SSP2_SS2 = PINID(2, 21), |
| 95 | SSP3_SCK = PINID(2, 24), |
| 96 | SSP3_MOSI = PINID(2, 25), |
| 97 | SSP3_MISO = PINID(2, 26), |
| 98 | SSP3_SS0 = PINID(2, 27), |
| 99 | AUART0_RX = PINID(3, 0), |
| 100 | AUART0_TX = PINID(3, 1), |
| 101 | AUART0_CTS = PINID(3, 2), |
| 102 | AUART0_RTS = PINID(3, 3), |
| 103 | AUART1_RX = PINID(3, 4), |
| 104 | AUART1_TX = PINID(3, 5), |
| 105 | AUART1_CTS = PINID(3, 6), |
| 106 | AUART1_RTS = PINID(3, 7), |
| 107 | AUART2_RX = PINID(3, 8), |
| 108 | AUART2_TX = PINID(3, 9), |
| 109 | AUART2_CTS = PINID(3, 10), |
| 110 | AUART2_RTS = PINID(3, 11), |
| 111 | AUART3_RX = PINID(3, 12), |
| 112 | AUART3_TX = PINID(3, 13), |
| 113 | AUART3_CTS = PINID(3, 14), |
| 114 | AUART3_RTS = PINID(3, 15), |
| 115 | PWM0 = PINID(3, 16), |
| 116 | PWM1 = PINID(3, 17), |
| 117 | PWM2 = PINID(3, 18), |
| 118 | SAIF0_MCLK = PINID(3, 20), |
| 119 | SAIF0_LRCLK = PINID(3, 21), |
| 120 | SAIF0_BITCLK = PINID(3, 22), |
| 121 | SAIF0_SDATA0 = PINID(3, 23), |
| 122 | I2C0_SCL = PINID(3, 24), |
| 123 | I2C0_SDA = PINID(3, 25), |
| 124 | SAIF1_SDATA0 = PINID(3, 26), |
| 125 | SPDIF = PINID(3, 27), |
| 126 | PWM3 = PINID(3, 28), |
| 127 | PWM4 = PINID(3, 29), |
| 128 | LCD_RESET = PINID(3, 30), |
| 129 | ENET0_MDC = PINID(4, 0), |
| 130 | ENET0_MDIO = PINID(4, 1), |
| 131 | ENET0_RX_EN = PINID(4, 2), |
| 132 | ENET0_RXD0 = PINID(4, 3), |
| 133 | ENET0_RXD1 = PINID(4, 4), |
| 134 | ENET0_TX_CLK = PINID(4, 5), |
| 135 | ENET0_TX_EN = PINID(4, 6), |
| 136 | ENET0_TXD0 = PINID(4, 7), |
| 137 | ENET0_TXD1 = PINID(4, 8), |
| 138 | ENET0_RXD2 = PINID(4, 9), |
| 139 | ENET0_RXD3 = PINID(4, 10), |
| 140 | ENET0_TXD2 = PINID(4, 11), |
| 141 | ENET0_TXD3 = PINID(4, 12), |
| 142 | ENET0_RX_CLK = PINID(4, 13), |
| 143 | ENET0_COL = PINID(4, 14), |
| 144 | ENET0_CRS = PINID(4, 15), |
| 145 | ENET_CLK = PINID(4, 16), |
| 146 | JTAG_RTCK = PINID(4, 20), |
| 147 | EMI_D00 = PINID(5, 0), |
| 148 | EMI_D01 = PINID(5, 1), |
| 149 | EMI_D02 = PINID(5, 2), |
| 150 | EMI_D03 = PINID(5, 3), |
| 151 | EMI_D04 = PINID(5, 4), |
| 152 | EMI_D05 = PINID(5, 5), |
| 153 | EMI_D06 = PINID(5, 6), |
| 154 | EMI_D07 = PINID(5, 7), |
| 155 | EMI_D08 = PINID(5, 8), |
| 156 | EMI_D09 = PINID(5, 9), |
| 157 | EMI_D10 = PINID(5, 10), |
| 158 | EMI_D11 = PINID(5, 11), |
| 159 | EMI_D12 = PINID(5, 12), |
| 160 | EMI_D13 = PINID(5, 13), |
| 161 | EMI_D14 = PINID(5, 14), |
| 162 | EMI_D15 = PINID(5, 15), |
| 163 | EMI_ODT0 = PINID(5, 16), |
| 164 | EMI_DQM0 = PINID(5, 17), |
| 165 | EMI_ODT1 = PINID(5, 18), |
| 166 | EMI_DQM1 = PINID(5, 19), |
| 167 | EMI_DDR_OPEN_FB = PINID(5, 20), |
| 168 | EMI_CLK = PINID(5, 21), |
| 169 | EMI_DQS0 = PINID(5, 22), |
| 170 | EMI_DQS1 = PINID(5, 23), |
| 171 | EMI_DDR_OPEN = PINID(5, 26), |
| 172 | EMI_A00 = PINID(6, 0), |
| 173 | EMI_A01 = PINID(6, 1), |
| 174 | EMI_A02 = PINID(6, 2), |
| 175 | EMI_A03 = PINID(6, 3), |
| 176 | EMI_A04 = PINID(6, 4), |
| 177 | EMI_A05 = PINID(6, 5), |
| 178 | EMI_A06 = PINID(6, 6), |
| 179 | EMI_A07 = PINID(6, 7), |
| 180 | EMI_A08 = PINID(6, 8), |
| 181 | EMI_A09 = PINID(6, 9), |
| 182 | EMI_A10 = PINID(6, 10), |
| 183 | EMI_A11 = PINID(6, 11), |
| 184 | EMI_A12 = PINID(6, 12), |
| 185 | EMI_A13 = PINID(6, 13), |
| 186 | EMI_A14 = PINID(6, 14), |
| 187 | EMI_BA0 = PINID(6, 16), |
| 188 | EMI_BA1 = PINID(6, 17), |
| 189 | EMI_BA2 = PINID(6, 18), |
| 190 | EMI_CASN = PINID(6, 19), |
| 191 | EMI_RASN = PINID(6, 20), |
| 192 | EMI_WEN = PINID(6, 21), |
| 193 | EMI_CE0N = PINID(6, 22), |
| 194 | EMI_CE1N = PINID(6, 23), |
| 195 | EMI_CKE = PINID(6, 24), |
| 196 | }; |
| 197 | |
| 198 | static const struct pinctrl_pin_desc imx28_pins[] = { |
| 199 | MXS_PINCTRL_PIN(GPMI_D00), |
| 200 | MXS_PINCTRL_PIN(GPMI_D01), |
| 201 | MXS_PINCTRL_PIN(GPMI_D02), |
| 202 | MXS_PINCTRL_PIN(GPMI_D03), |
| 203 | MXS_PINCTRL_PIN(GPMI_D04), |
| 204 | MXS_PINCTRL_PIN(GPMI_D05), |
| 205 | MXS_PINCTRL_PIN(GPMI_D06), |
| 206 | MXS_PINCTRL_PIN(GPMI_D07), |
| 207 | MXS_PINCTRL_PIN(GPMI_CE0N), |
| 208 | MXS_PINCTRL_PIN(GPMI_CE1N), |
| 209 | MXS_PINCTRL_PIN(GPMI_CE2N), |
| 210 | MXS_PINCTRL_PIN(GPMI_CE3N), |
| 211 | MXS_PINCTRL_PIN(GPMI_RDY0), |
| 212 | MXS_PINCTRL_PIN(GPMI_RDY1), |
| 213 | MXS_PINCTRL_PIN(GPMI_RDY2), |
| 214 | MXS_PINCTRL_PIN(GPMI_RDY3), |
| 215 | MXS_PINCTRL_PIN(GPMI_RDN), |
| 216 | MXS_PINCTRL_PIN(GPMI_WRN), |
| 217 | MXS_PINCTRL_PIN(GPMI_ALE), |
| 218 | MXS_PINCTRL_PIN(GPMI_CLE), |
| 219 | MXS_PINCTRL_PIN(GPMI_RESETN), |
| 220 | MXS_PINCTRL_PIN(LCD_D00), |
| 221 | MXS_PINCTRL_PIN(LCD_D01), |
| 222 | MXS_PINCTRL_PIN(LCD_D02), |
| 223 | MXS_PINCTRL_PIN(LCD_D03), |
| 224 | MXS_PINCTRL_PIN(LCD_D04), |
| 225 | MXS_PINCTRL_PIN(LCD_D05), |
| 226 | MXS_PINCTRL_PIN(LCD_D06), |
| 227 | MXS_PINCTRL_PIN(LCD_D07), |
| 228 | MXS_PINCTRL_PIN(LCD_D08), |
| 229 | MXS_PINCTRL_PIN(LCD_D09), |
| 230 | MXS_PINCTRL_PIN(LCD_D10), |
| 231 | MXS_PINCTRL_PIN(LCD_D11), |
| 232 | MXS_PINCTRL_PIN(LCD_D12), |
| 233 | MXS_PINCTRL_PIN(LCD_D13), |
| 234 | MXS_PINCTRL_PIN(LCD_D14), |
| 235 | MXS_PINCTRL_PIN(LCD_D15), |
| 236 | MXS_PINCTRL_PIN(LCD_D16), |
| 237 | MXS_PINCTRL_PIN(LCD_D17), |
| 238 | MXS_PINCTRL_PIN(LCD_D18), |
| 239 | MXS_PINCTRL_PIN(LCD_D19), |
| 240 | MXS_PINCTRL_PIN(LCD_D20), |
| 241 | MXS_PINCTRL_PIN(LCD_D21), |
| 242 | MXS_PINCTRL_PIN(LCD_D22), |
| 243 | MXS_PINCTRL_PIN(LCD_D23), |
| 244 | MXS_PINCTRL_PIN(LCD_RD_E), |
| 245 | MXS_PINCTRL_PIN(LCD_WR_RWN), |
| 246 | MXS_PINCTRL_PIN(LCD_RS), |
| 247 | MXS_PINCTRL_PIN(LCD_CS), |
| 248 | MXS_PINCTRL_PIN(LCD_VSYNC), |
| 249 | MXS_PINCTRL_PIN(LCD_HSYNC), |
| 250 | MXS_PINCTRL_PIN(LCD_DOTCLK), |
| 251 | MXS_PINCTRL_PIN(LCD_ENABLE), |
| 252 | MXS_PINCTRL_PIN(SSP0_DATA0), |
| 253 | MXS_PINCTRL_PIN(SSP0_DATA1), |
| 254 | MXS_PINCTRL_PIN(SSP0_DATA2), |
| 255 | MXS_PINCTRL_PIN(SSP0_DATA3), |
| 256 | MXS_PINCTRL_PIN(SSP0_DATA4), |
| 257 | MXS_PINCTRL_PIN(SSP0_DATA5), |
| 258 | MXS_PINCTRL_PIN(SSP0_DATA6), |
| 259 | MXS_PINCTRL_PIN(SSP0_DATA7), |
| 260 | MXS_PINCTRL_PIN(SSP0_CMD), |
| 261 | MXS_PINCTRL_PIN(SSP0_DETECT), |
| 262 | MXS_PINCTRL_PIN(SSP0_SCK), |
| 263 | MXS_PINCTRL_PIN(SSP1_SCK), |
| 264 | MXS_PINCTRL_PIN(SSP1_CMD), |
| 265 | MXS_PINCTRL_PIN(SSP1_DATA0), |
| 266 | MXS_PINCTRL_PIN(SSP1_DATA3), |
| 267 | MXS_PINCTRL_PIN(SSP2_SCK), |
| 268 | MXS_PINCTRL_PIN(SSP2_MOSI), |
| 269 | MXS_PINCTRL_PIN(SSP2_MISO), |
| 270 | MXS_PINCTRL_PIN(SSP2_SS0), |
| 271 | MXS_PINCTRL_PIN(SSP2_SS1), |
| 272 | MXS_PINCTRL_PIN(SSP2_SS2), |
| 273 | MXS_PINCTRL_PIN(SSP3_SCK), |
| 274 | MXS_PINCTRL_PIN(SSP3_MOSI), |
| 275 | MXS_PINCTRL_PIN(SSP3_MISO), |
| 276 | MXS_PINCTRL_PIN(SSP3_SS0), |
| 277 | MXS_PINCTRL_PIN(AUART0_RX), |
| 278 | MXS_PINCTRL_PIN(AUART0_TX), |
| 279 | MXS_PINCTRL_PIN(AUART0_CTS), |
| 280 | MXS_PINCTRL_PIN(AUART0_RTS), |
| 281 | MXS_PINCTRL_PIN(AUART1_RX), |
| 282 | MXS_PINCTRL_PIN(AUART1_TX), |
| 283 | MXS_PINCTRL_PIN(AUART1_CTS), |
| 284 | MXS_PINCTRL_PIN(AUART1_RTS), |
| 285 | MXS_PINCTRL_PIN(AUART2_RX), |
| 286 | MXS_PINCTRL_PIN(AUART2_TX), |
| 287 | MXS_PINCTRL_PIN(AUART2_CTS), |
| 288 | MXS_PINCTRL_PIN(AUART2_RTS), |
| 289 | MXS_PINCTRL_PIN(AUART3_RX), |
| 290 | MXS_PINCTRL_PIN(AUART3_TX), |
| 291 | MXS_PINCTRL_PIN(AUART3_CTS), |
| 292 | MXS_PINCTRL_PIN(AUART3_RTS), |
| 293 | MXS_PINCTRL_PIN(PWM0), |
| 294 | MXS_PINCTRL_PIN(PWM1), |
| 295 | MXS_PINCTRL_PIN(PWM2), |
| 296 | MXS_PINCTRL_PIN(SAIF0_MCLK), |
| 297 | MXS_PINCTRL_PIN(SAIF0_LRCLK), |
| 298 | MXS_PINCTRL_PIN(SAIF0_BITCLK), |
| 299 | MXS_PINCTRL_PIN(SAIF0_SDATA0), |
| 300 | MXS_PINCTRL_PIN(I2C0_SCL), |
| 301 | MXS_PINCTRL_PIN(I2C0_SDA), |
| 302 | MXS_PINCTRL_PIN(SAIF1_SDATA0), |
| 303 | MXS_PINCTRL_PIN(SPDIF), |
| 304 | MXS_PINCTRL_PIN(PWM3), |
| 305 | MXS_PINCTRL_PIN(PWM4), |
| 306 | MXS_PINCTRL_PIN(LCD_RESET), |
| 307 | MXS_PINCTRL_PIN(ENET0_MDC), |
| 308 | MXS_PINCTRL_PIN(ENET0_MDIO), |
| 309 | MXS_PINCTRL_PIN(ENET0_RX_EN), |
| 310 | MXS_PINCTRL_PIN(ENET0_RXD0), |
| 311 | MXS_PINCTRL_PIN(ENET0_RXD1), |
| 312 | MXS_PINCTRL_PIN(ENET0_TX_CLK), |
| 313 | MXS_PINCTRL_PIN(ENET0_TX_EN), |
| 314 | MXS_PINCTRL_PIN(ENET0_TXD0), |
| 315 | MXS_PINCTRL_PIN(ENET0_TXD1), |
| 316 | MXS_PINCTRL_PIN(ENET0_RXD2), |
| 317 | MXS_PINCTRL_PIN(ENET0_RXD3), |
| 318 | MXS_PINCTRL_PIN(ENET0_TXD2), |
| 319 | MXS_PINCTRL_PIN(ENET0_TXD3), |
| 320 | MXS_PINCTRL_PIN(ENET0_RX_CLK), |
| 321 | MXS_PINCTRL_PIN(ENET0_COL), |
| 322 | MXS_PINCTRL_PIN(ENET0_CRS), |
| 323 | MXS_PINCTRL_PIN(ENET_CLK), |
| 324 | MXS_PINCTRL_PIN(JTAG_RTCK), |
| 325 | MXS_PINCTRL_PIN(EMI_D00), |
| 326 | MXS_PINCTRL_PIN(EMI_D01), |
| 327 | MXS_PINCTRL_PIN(EMI_D02), |
| 328 | MXS_PINCTRL_PIN(EMI_D03), |
| 329 | MXS_PINCTRL_PIN(EMI_D04), |
| 330 | MXS_PINCTRL_PIN(EMI_D05), |
| 331 | MXS_PINCTRL_PIN(EMI_D06), |
| 332 | MXS_PINCTRL_PIN(EMI_D07), |
| 333 | MXS_PINCTRL_PIN(EMI_D08), |
| 334 | MXS_PINCTRL_PIN(EMI_D09), |
| 335 | MXS_PINCTRL_PIN(EMI_D10), |
| 336 | MXS_PINCTRL_PIN(EMI_D11), |
| 337 | MXS_PINCTRL_PIN(EMI_D12), |
| 338 | MXS_PINCTRL_PIN(EMI_D13), |
| 339 | MXS_PINCTRL_PIN(EMI_D14), |
| 340 | MXS_PINCTRL_PIN(EMI_D15), |
| 341 | MXS_PINCTRL_PIN(EMI_ODT0), |
| 342 | MXS_PINCTRL_PIN(EMI_DQM0), |
| 343 | MXS_PINCTRL_PIN(EMI_ODT1), |
| 344 | MXS_PINCTRL_PIN(EMI_DQM1), |
| 345 | MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB), |
| 346 | MXS_PINCTRL_PIN(EMI_CLK), |
| 347 | MXS_PINCTRL_PIN(EMI_DQS0), |
| 348 | MXS_PINCTRL_PIN(EMI_DQS1), |
| 349 | MXS_PINCTRL_PIN(EMI_DDR_OPEN), |
| 350 | MXS_PINCTRL_PIN(EMI_A00), |
| 351 | MXS_PINCTRL_PIN(EMI_A01), |
| 352 | MXS_PINCTRL_PIN(EMI_A02), |
| 353 | MXS_PINCTRL_PIN(EMI_A03), |
| 354 | MXS_PINCTRL_PIN(EMI_A04), |
| 355 | MXS_PINCTRL_PIN(EMI_A05), |
| 356 | MXS_PINCTRL_PIN(EMI_A06), |
| 357 | MXS_PINCTRL_PIN(EMI_A07), |
| 358 | MXS_PINCTRL_PIN(EMI_A08), |
| 359 | MXS_PINCTRL_PIN(EMI_A09), |
| 360 | MXS_PINCTRL_PIN(EMI_A10), |
| 361 | MXS_PINCTRL_PIN(EMI_A11), |
| 362 | MXS_PINCTRL_PIN(EMI_A12), |
| 363 | MXS_PINCTRL_PIN(EMI_A13), |
| 364 | MXS_PINCTRL_PIN(EMI_A14), |
| 365 | MXS_PINCTRL_PIN(EMI_BA0), |
| 366 | MXS_PINCTRL_PIN(EMI_BA1), |
| 367 | MXS_PINCTRL_PIN(EMI_BA2), |
| 368 | MXS_PINCTRL_PIN(EMI_CASN), |
| 369 | MXS_PINCTRL_PIN(EMI_RASN), |
| 370 | MXS_PINCTRL_PIN(EMI_WEN), |
| 371 | MXS_PINCTRL_PIN(EMI_CE0N), |
| 372 | MXS_PINCTRL_PIN(EMI_CE1N), |
| 373 | MXS_PINCTRL_PIN(EMI_CKE), |
| 374 | }; |
| 375 | |
Bhumika Goyal | ae9d7f8 | 2017-08-23 19:19:12 +0530 | [diff] [blame] | 376 | static const struct mxs_regs imx28_regs = { |
Shawn Guo | 1772311 | 2012-04-28 13:00:50 +0800 | [diff] [blame] | 377 | .muxsel = 0x100, |
| 378 | .drive = 0x300, |
| 379 | .pull = 0x600, |
| 380 | }; |
| 381 | |
| 382 | static struct mxs_pinctrl_soc_data imx28_pinctrl_data = { |
| 383 | .regs = &imx28_regs, |
| 384 | .pins = imx28_pins, |
| 385 | .npins = ARRAY_SIZE(imx28_pins), |
| 386 | }; |
| 387 | |
Greg Kroah-Hartman | 150632b | 2012-12-21 13:10:23 -0800 | [diff] [blame] | 388 | static int imx28_pinctrl_probe(struct platform_device *pdev) |
Shawn Guo | 1772311 | 2012-04-28 13:00:50 +0800 | [diff] [blame] | 389 | { |
| 390 | return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data); |
| 391 | } |
| 392 | |
Kiran Padwal | 5dfe10b | 2014-08-11 16:47:50 +0530 | [diff] [blame] | 393 | static const struct of_device_id imx28_pinctrl_of_match[] = { |
Shawn Guo | 1772311 | 2012-04-28 13:00:50 +0800 | [diff] [blame] | 394 | { .compatible = "fsl,imx28-pinctrl", }, |
| 395 | { /* sentinel */ } |
| 396 | }; |
Shawn Guo | 1772311 | 2012-04-28 13:00:50 +0800 | [diff] [blame] | 397 | |
| 398 | static struct platform_driver imx28_pinctrl_driver = { |
| 399 | .driver = { |
| 400 | .name = "imx28-pinctrl", |
Paul Gortmaker | 37824c1 | 2016-06-25 22:46:51 -0400 | [diff] [blame] | 401 | .suppress_bind_attrs = true, |
Shawn Guo | 1772311 | 2012-04-28 13:00:50 +0800 | [diff] [blame] | 402 | .of_match_table = imx28_pinctrl_of_match, |
| 403 | }, |
| 404 | .probe = imx28_pinctrl_probe, |
Shawn Guo | 1772311 | 2012-04-28 13:00:50 +0800 | [diff] [blame] | 405 | }; |
| 406 | |
| 407 | static int __init imx28_pinctrl_init(void) |
| 408 | { |
| 409 | return platform_driver_register(&imx28_pinctrl_driver); |
| 410 | } |
Shawn Guo | c43ba80 | 2012-07-19 16:41:10 +0800 | [diff] [blame] | 411 | postcore_initcall(imx28_pinctrl_init); |