Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 1 | Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. |
| 2 | |
| 3 | Reference |
| 4 | [1] Si5351A/B/C Data Sheet |
| 5 | http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf |
| 6 | |
Anatol Pomozov | f884ab1 | 2013-05-08 16:56:16 -0700 | [diff] [blame] | 7 | The Si5351a/b/c are programmable i2c clock generators with up to 8 output |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 8 | clocks. Si5351a also has a reduced pin-count package (MSOP10) where only |
| 9 | 3 output clocks are accessible. The internal structure of the clock |
| 10 | generators can be found in [1]. |
| 11 | |
| 12 | ==I2C device node== |
| 13 | |
| 14 | Required properties: |
| 15 | - compatible: shall be one of "silabs,si5351{a,a-msop,b,c}". |
| 16 | - reg: i2c device address, shall be 0x60 or 0x61. |
| 17 | - #clock-cells: from common clock binding; shall be set to 1. |
| 18 | - clocks: from common clock binding; list of parent clock |
| 19 | handles, shall be xtal reference clock or xtal and clkin for |
| 20 | si5351c only. |
| 21 | - #address-cells: shall be set to 1. |
| 22 | - #size-cells: shall be set to 0. |
| 23 | |
| 24 | Optional properties: |
| 25 | - silabs,pll-source: pair of (number, source) for each pll. Allows |
| 26 | to overwrite clock source of pll A (number=0) or B (number=1). |
| 27 | |
| 28 | ==Child nodes== |
| 29 | |
| 30 | Each of the clock outputs can be overwritten individually by |
| 31 | using a child node to the I2C device node. If a child node for a clock |
| 32 | output is not set, the eeprom configuration is not overwritten. |
| 33 | |
| 34 | Required child node properties: |
| 35 | - reg: number of clock output. |
| 36 | |
| 37 | Optional child node properties: |
| 38 | - silabs,clock-source: source clock of the output divider stage N, shall be |
| 39 | 0 = multisynth N |
| 40 | 1 = multisynth 0 for output clocks 0-3, else multisynth4 |
| 41 | 2 = xtal |
| 42 | 3 = clkin (si5351c only) |
| 43 | - silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. |
| 44 | - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth |
| 45 | divider. |
| 46 | - silabs,pll-master: boolean, multisynth can change pll frequency. |
Sebastian Hesselbarth | 1a0483d | 2013-05-03 07:33:27 +0200 | [diff] [blame] | 47 | - silabs,disable-state : clock output disable state, shall be |
| 48 | 0 = clock output is driven LOW when disabled |
| 49 | 1 = clock output is driven HIGH when disabled |
| 50 | 2 = clock output is FLOATING (HIGH-Z) when disabled |
| 51 | 3 = clock output is NEVER disabled |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 52 | |
| 53 | ==Example== |
| 54 | |
| 55 | /* 25MHz reference crystal */ |
| 56 | ref25: ref25M { |
| 57 | compatible = "fixed-clock"; |
| 58 | #clock-cells = <0>; |
| 59 | clock-frequency = <25000000>; |
| 60 | }; |
| 61 | |
| 62 | i2c-master-node { |
| 63 | |
| 64 | /* Si5351a msop10 i2c clock generator */ |
| 65 | si5351a: clock-generator@60 { |
| 66 | compatible = "silabs,si5351a-msop"; |
| 67 | reg = <0x60>; |
| 68 | #address-cells = <1>; |
| 69 | #size-cells = <0>; |
| 70 | #clock-cells = <1>; |
| 71 | |
| 72 | /* connect xtal input to 25MHz reference */ |
| 73 | clocks = <&ref25>; |
| 74 | |
| 75 | /* connect xtal input as source of pll0 and pll1 */ |
| 76 | silabs,pll-source = <0 0>, <1 0>; |
| 77 | |
| 78 | /* |
| 79 | * overwrite clkout0 configuration with: |
| 80 | * - 8mA output drive strength |
| 81 | * - pll0 as clock source of multisynth0 |
| 82 | * - multisynth0 as clock source of output divider |
| 83 | * - multisynth0 can change pll0 |
| 84 | * - set initial clock frequency of 74.25MHz |
| 85 | */ |
| 86 | clkout0 { |
| 87 | reg = <0>; |
| 88 | silabs,drive-strength = <8>; |
| 89 | silabs,multisynth-source = <0>; |
| 90 | silabs,clock-source = <0>; |
| 91 | silabs,pll-master; |
| 92 | clock-frequency = <74250000>; |
| 93 | }; |
| 94 | |
| 95 | /* |
| 96 | * overwrite clkout1 configuration with: |
| 97 | * - 4mA output drive strength |
| 98 | * - pll1 as clock source of multisynth1 |
| 99 | * - multisynth1 as clock source of output divider |
| 100 | * - multisynth1 can change pll1 |
| 101 | */ |
| 102 | clkout1 { |
| 103 | reg = <1>; |
| 104 | silabs,drive-strength = <4>; |
| 105 | silabs,multisynth-source = <1>; |
| 106 | silabs,clock-source = <0>; |
| 107 | pll-master; |
| 108 | }; |
| 109 | |
| 110 | /* |
| 111 | * overwrite clkout2 configuration with: |
| 112 | * - xtal as clock source of output divider |
| 113 | */ |
| 114 | clkout2 { |
| 115 | reg = <2>; |
| 116 | silabs,clock-source = <2>; |
| 117 | }; |
| 118 | }; |
| 119 | }; |