blob: 2a45d548d5ece5d9cd1cdad32d64fb3808b0c6fd [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +010034uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020035void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +010036uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020037void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +010039uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020040void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +010041uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020042void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
Alex Deucher37e9b6a2012-08-03 11:39:43 -040045void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -040046u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -040047void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -040048u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -040049
Jerome Glisse771fe6b2009-06-05 14:42:42 +020050/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +000051 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +020052 */
Daniel Vetter2b497502010-03-11 21:19:18 +000053struct r100_mc_save {
54 u32 GENMO_WT;
55 u32 CRTC_EXT_CNTL;
56 u32 CRTC_GEN_CNTL;
57 u32 CRTC2_GEN_CNTL;
58 u32 CUR_OFFSET;
59 u32 CUR2_OFFSET;
60};
61int r100_init(struct radeon_device *rdev);
62void r100_fini(struct radeon_device *rdev);
63int r100_suspend(struct radeon_device *rdev);
64int r100_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +100065void r100_vga_set_state(struct radeon_device *rdev, bool state);
Christian Könige32eb502011-10-23 12:56:27 +020066bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +000067int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +020068u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020069void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
Christian König7f90fc92014-06-04 15:29:57 +020070void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
Michel Dänzer77497f22014-07-17 19:01:07 +090071 uint64_t addr, uint32_t flags);
Alex Deucherf7128122012-02-23 17:53:45 -050072void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020073int r100_irq_set(struct radeon_device *rdev);
74int r100_irq_process(struct radeon_device *rdev);
75void r100_fence_ring_emit(struct radeon_device *rdev,
76 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +010077bool r100_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +020078 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +020079 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +020080 bool emit_wait);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020081int r100_cs_parse(struct radeon_cs_parser *p);
82void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
83uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
Christian König57d20a42014-09-04 20:01:53 +020084struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
85 uint64_t src_offset,
86 uint64_t dst_offset,
87 unsigned num_gpu_pages,
88 struct reservation_object *resv);
Dave Airliee024e112009-06-24 09:48:08 +100089int r100_set_surface_reg(struct radeon_device *rdev, int reg,
90 uint32_t tiling_flags, uint32_t pitch,
91 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +000092void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +020093void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +100094void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +020095int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher429770b2009-12-04 15:26:55 -050096void r100_hpd_init(struct radeon_device *rdev);
97void r100_hpd_fini(struct radeon_device *rdev);
98bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
99void r100_hpd_set_polarity(struct radeon_device *rdev,
100 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000101int r100_debugfs_rbbm_init(struct radeon_device *rdev);
102int r100_debugfs_cp_init(struct radeon_device *rdev);
103void r100_cp_disable(struct radeon_device *rdev);
104int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
105void r100_cp_fini(struct radeon_device *rdev);
106int r100_pci_gart_init(struct radeon_device *rdev);
107void r100_pci_gart_fini(struct radeon_device *rdev);
108int r100_pci_gart_enable(struct radeon_device *rdev);
109void r100_pci_gart_disable(struct radeon_device *rdev);
110int r100_debugfs_mc_info_init(struct radeon_device *rdev);
111int r100_gui_wait_for_idle(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500112int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Daniel Vetter2b497502010-03-11 21:19:18 +0000113void r100_irq_disable(struct radeon_device *rdev);
114void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
115void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
116void r100_vram_init_sizes(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000117int r100_cp_reset(struct radeon_device *rdev);
118void r100_vga_render_disable(struct radeon_device *rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000119void r100_restore_sanity(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000120int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
121 struct radeon_cs_packet *pkt,
122 struct radeon_bo *robj);
123int r100_cs_parse_packet0(struct radeon_cs_parser *p,
124 struct radeon_cs_packet *pkt,
125 const unsigned *auth, unsigned n,
126 radeon_packet0_check_t check);
127int r100_cs_packet_parse(struct radeon_cs_parser *p,
128 struct radeon_cs_packet *pkt,
129 unsigned idx);
130void r100_enable_bm(struct radeon_device *rdev);
131void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000132void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400133extern bool r100_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400134extern void r100_pm_misc(struct radeon_device *rdev);
135extern void r100_pm_prepare(struct radeon_device *rdev);
136extern void r100_pm_finish(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400137extern void r100_pm_init_profile(struct radeon_device *rdev);
138extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
Christian König157fa142014-05-27 16:49:20 +0200139extern void r100_page_flip(struct radeon_device *rdev, int crtc,
140 u64 crtc_base);
141extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500142extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500143extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucherbae6b5622010-04-22 13:38:05 -0400144
Alex Deucherea31bf62013-12-09 19:44:30 -0500145u32 r100_gfx_get_rptr(struct radeon_device *rdev,
146 struct radeon_ring *ring);
147u32 r100_gfx_get_wptr(struct radeon_device *rdev,
148 struct radeon_ring *ring);
149void r100_gfx_set_wptr(struct radeon_device *rdev,
150 struct radeon_ring *ring);
Michel Dänzer897eba82014-09-17 16:25:55 +0900151
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000152/*
153 * r200,rv250,rs300,rv280
154 */
Christian König57d20a42014-09-04 20:01:53 +0200155struct radeon_fence *r200_copy_dma(struct radeon_device *rdev,
156 uint64_t src_offset,
157 uint64_t dst_offset,
158 unsigned num_gpu_pages,
159 struct reservation_object *resv);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100160void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200161
162/*
163 * r300,r350,rv350,rv380
164 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200165extern int r300_init(struct radeon_device *rdev);
166extern void r300_fini(struct radeon_device *rdev);
167extern int r300_suspend(struct radeon_device *rdev);
168extern int r300_resume(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000169extern int r300_asic_reset(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500170extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200171extern void r300_fence_ring_emit(struct radeon_device *rdev,
172 struct radeon_fence *fence);
173extern int r300_cs_parse(struct radeon_cs_parser *p);
174extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
Christian König7f90fc92014-06-04 15:29:57 +0200175extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
Michel Dänzer77497f22014-07-17 19:01:07 +0900176 uint64_t addr, uint32_t flags);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200177extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500178extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100179extern void r300_set_reg_safe(struct radeon_device *rdev);
180extern void r300_mc_program(struct radeon_device *rdev);
181extern void r300_mc_init(struct radeon_device *rdev);
182extern void r300_clock_startup(struct radeon_device *rdev);
183extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
184extern int rv370_pcie_gart_init(struct radeon_device *rdev);
185extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
186extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
187extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500188extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000189
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200190/*
191 * r420,r423,rv410
192 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200193extern int r420_init(struct radeon_device *rdev);
194extern void r420_fini(struct radeon_device *rdev);
195extern int r420_suspend(struct radeon_device *rdev);
196extern int r420_resume(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400197extern void r420_pm_init_profile(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100198extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
199extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
200extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
201extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200202
203/*
204 * rs400,rs480
205 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200206extern int rs400_init(struct radeon_device *rdev);
207extern void rs400_fini(struct radeon_device *rdev);
208extern int rs400_suspend(struct radeon_device *rdev);
209extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200210void rs400_gart_tlb_flush(struct radeon_device *rdev);
Christian König7f90fc92014-06-04 15:29:57 +0200211void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
Michel Dänzer77497f22014-07-17 19:01:07 +0900212 uint64_t addr, uint32_t flags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200213uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
214void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100215int rs400_gart_init(struct radeon_device *rdev);
216int rs400_gart_enable(struct radeon_device *rdev);
217void rs400_gart_adjust_size(struct radeon_device *rdev);
218void rs400_gart_disable(struct radeon_device *rdev);
219void rs400_gart_fini(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500220extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100221
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200222/*
223 * rs600.
224 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000225extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200226extern int rs600_init(struct radeon_device *rdev);
227extern void rs600_fini(struct radeon_device *rdev);
228extern int rs600_suspend(struct radeon_device *rdev);
229extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200230int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200231int rs600_irq_process(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100232void rs600_irq_disable(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200233u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200234void rs600_gart_tlb_flush(struct radeon_device *rdev);
Christian König7f90fc92014-06-04 15:29:57 +0200235void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
Michel Dänzer77497f22014-07-17 19:01:07 +0900236 uint64_t addr, uint32_t flags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200237uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
238void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200239void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500240void rs600_hpd_init(struct radeon_device *rdev);
241void rs600_hpd_fini(struct radeon_device *rdev);
242bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
243void rs600_hpd_set_polarity(struct radeon_device *rdev,
244 enum radeon_hpd_id hpd);
Alex Deucher49e02b72010-04-23 17:57:27 -0400245extern void rs600_pm_misc(struct radeon_device *rdev);
246extern void rs600_pm_prepare(struct radeon_device *rdev);
247extern void rs600_pm_finish(struct radeon_device *rdev);
Christian König157fa142014-05-27 16:49:20 +0200248extern void rs600_page_flip(struct radeon_device *rdev, int crtc,
249 u64 crtc_base);
250extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100251void rs600_set_safe_registers(struct radeon_device *rdev);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500252extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500253extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500254
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200255/*
256 * rs690,rs740
257 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200258int rs690_init(struct radeon_device *rdev);
259void rs690_fini(struct radeon_device *rdev);
260int rs690_resume(struct radeon_device *rdev);
261int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200262uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
263void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200264void rs690_bandwidth_update(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100265void rs690_line_buffer_adjust(struct radeon_device *rdev,
266 struct drm_display_mode *mode1,
267 struct drm_display_mode *mode2);
Alex Deucher89e51812012-02-23 17:53:38 -0500268extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200269
270/*
271 * rv515
272 */
Daniel Vetter187f3da2010-11-28 19:06:09 +0100273struct rv515_mc_save {
Daniel Vetter187f3da2010-11-28 19:06:09 +0100274 u32 vga_render_control;
275 u32 vga_hdp_control;
Alex Deucher6253e4c2012-12-12 14:30:32 -0500276 bool crtc_enabled[2];
Daniel Vetter187f3da2010-11-28 19:06:09 +0100277};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400278
Jerome Glisse068a1172009-06-17 13:28:30 +0200279int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200280void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200281uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
282void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherf7128122012-02-23 17:53:45 -0500283void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glissec93bb852009-07-13 21:04:08 +0200284void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200285int rv515_resume(struct radeon_device *rdev);
286int rv515_suspend(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100287void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
288void rv515_vga_render_disable(struct radeon_device *rdev);
289void rv515_set_safe_registers(struct radeon_device *rdev);
290void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
291void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
292void rv515_clock_startup(struct radeon_device *rdev);
293void rv515_debugfs(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500294int rv515_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200295
296/*
297 * r520,rv530,rv560,rv570,r580
298 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200299int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200300int r520_resume(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500301int r520_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200302
303/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000304 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200305 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000306int r600_init(struct radeon_device *rdev);
307void r600_fini(struct radeon_device *rdev);
308int r600_suspend(struct radeon_device *rdev);
309int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000310void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000311int r600_wb_init(struct radeon_device *rdev);
312void r600_wb_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000313void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200314uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
315void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000316int r600_cs_parse(struct radeon_cs_parser *p);
Alex Deuchercf4ccd02011-11-18 10:19:47 -0500317int r600_dma_cs_parse(struct radeon_cs_parser *p);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000318void r600_fence_ring_emit(struct radeon_device *rdev,
319 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100320bool r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200321 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200322 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200323 bool emit_wait);
Alex Deucher4d756582012-09-27 15:08:35 -0400324void r600_dma_fence_ring_emit(struct radeon_device *rdev,
325 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100326bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher4d756582012-09-27 15:08:35 -0400327 struct radeon_ring *ring,
328 struct radeon_semaphore *semaphore,
329 bool emit_wait);
330void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
331bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher123bc182013-01-24 11:37:19 -0500332bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000333int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000334int r600_set_surface_reg(struct radeon_device *rdev, int reg,
335 uint32_t tiling_flags, uint32_t pitch,
336 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000337void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Alex Deucherf7128122012-02-23 17:53:45 -0500338int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher4d756582012-09-27 15:08:35 -0400339int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000340void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200341int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher4d756582012-09-27 15:08:35 -0400342int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Christian König57d20a42014-09-04 20:01:53 +0200343struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
344 uint64_t src_offset, uint64_t dst_offset,
345 unsigned num_gpu_pages,
346 struct reservation_object *resv);
347struct radeon_fence *r600_copy_dma(struct radeon_device *rdev,
348 uint64_t src_offset, uint64_t dst_offset,
349 unsigned num_gpu_pages,
350 struct reservation_object *resv);
Alex Deucher429770b2009-12-04 15:26:55 -0500351void r600_hpd_init(struct radeon_device *rdev);
352void r600_hpd_fini(struct radeon_device *rdev);
353bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
354void r600_hpd_set_polarity(struct radeon_device *rdev,
355 enum radeon_hpd_id hpd);
Michel Dänzer124764f2014-07-31 18:43:48 +0900356extern void r600_mmio_hdp_flush(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400357extern bool r600_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400358extern void r600_pm_misc(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400359extern void r600_pm_init_profile(struct radeon_device *rdev);
360extern void rs780_pm_init_profile(struct radeon_device *rdev);
Samuel Li65337e62013-04-05 17:50:53 -0400361extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
362extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherce8f5372010-05-07 15:10:16 -0400363extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500364extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
365extern int r600_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100366bool r600_card_posted(struct radeon_device *rdev);
367void r600_cp_stop(struct radeon_device *rdev);
368int r600_cp_start(struct radeon_device *rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200369void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100370int r600_cp_resume(struct radeon_device *rdev);
371void r600_cp_fini(struct radeon_device *rdev);
372int r600_count_pipe_bits(uint32_t val);
373int r600_mc_wait_for_idle(struct radeon_device *rdev);
374int r600_pcie_gart_init(struct radeon_device *rdev);
375void r600_scratch_init(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100376int r600_init_microcode(struct radeon_device *rdev);
Alex Deucherea31bf62013-12-09 19:44:30 -0500377u32 r600_gfx_get_rptr(struct radeon_device *rdev,
378 struct radeon_ring *ring);
379u32 r600_gfx_get_wptr(struct radeon_device *rdev,
380 struct radeon_ring *ring);
381void r600_gfx_set_wptr(struct radeon_device *rdev,
382 struct radeon_ring *ring);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100383/* r600 irq */
384int r600_irq_process(struct radeon_device *rdev);
385int r600_irq_init(struct radeon_device *rdev);
386void r600_irq_fini(struct radeon_device *rdev);
387void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
388int r600_irq_set(struct radeon_device *rdev);
389void r600_irq_suspend(struct radeon_device *rdev);
390void r600_disable_interrupts(struct radeon_device *rdev);
391void r600_rlc_stop(struct radeon_device *rdev);
392/* r600 audio */
393int r600_audio_init(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100394void r600_audio_fini(struct radeon_device *rdev);
Rafał Miłecki8f33a152014-05-16 11:36:24 +0200395void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
396void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
397 size_t size);
398void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
399void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100400int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
401void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
Alex Deuchera973bea2013-04-18 11:32:16 -0400402void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
403void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher89e51812012-02-23 17:53:38 -0500404int r600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher454d2e22013-02-14 10:04:02 -0500405u32 r600_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500406uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400407int rv6xx_get_temp(struct radeon_device *rdev);
Alex Deucher1b9ba702013-09-05 09:52:37 -0400408int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher98243912013-01-16 13:13:42 -0500409int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
410void r600_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deuchera4643ba2013-12-19 12:18:13 -0500411int r600_dpm_late_enable(struct radeon_device *rdev);
Christian König2e1e6da2013-08-13 11:56:52 +0200412/* r600 dma */
413uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
414 struct radeon_ring *ring);
415uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
416 struct radeon_ring *ring);
417void r600_dma_set_wptr(struct radeon_device *rdev,
418 struct radeon_ring *ring);
Alex Deucher4a6369e2013-04-12 14:04:10 -0400419/* rv6xx dpm */
420int rv6xx_dpm_init(struct radeon_device *rdev);
421int rv6xx_dpm_enable(struct radeon_device *rdev);
422void rv6xx_dpm_disable(struct radeon_device *rdev);
423int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
424void rv6xx_setup_asic(struct radeon_device *rdev);
425void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
426void rv6xx_dpm_fini(struct radeon_device *rdev);
427u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
428u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
429void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
430 struct radeon_ps *ps);
Alex Deucher242916a2013-06-28 14:20:53 -0400431void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
432 struct seq_file *m);
Alex Deucherf4f85a82013-07-25 20:07:25 -0400433int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
434 enum radeon_dpm_forced_level level);
Alex Deucher9d670062013-04-12 13:59:22 -0400435/* rs780 dpm */
436int rs780_dpm_init(struct radeon_device *rdev);
437int rs780_dpm_enable(struct radeon_device *rdev);
438void rs780_dpm_disable(struct radeon_device *rdev);
439int rs780_dpm_set_power_state(struct radeon_device *rdev);
440void rs780_dpm_setup_asic(struct radeon_device *rdev);
441void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
442void rs780_dpm_fini(struct radeon_device *rdev);
443u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
444u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
445void rs780_dpm_print_power_state(struct radeon_device *rdev,
446 struct radeon_ps *ps);
Alex Deucher444bddc2013-07-02 13:05:23 -0400447void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
448 struct seq_file *m);
Anthoine Bourgeois63580c32013-09-03 13:52:19 -0400449int rs780_dpm_force_performance_level(struct radeon_device *rdev,
450 enum radeon_dpm_forced_level level);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000451
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000452/*
453 * rv770,rv730,rv710,rv740
454 */
455int rv770_init(struct radeon_device *rdev);
456void rv770_fini(struct radeon_device *rdev);
457int rv770_suspend(struct radeon_device *rdev);
458int rv770_resume(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100459void rv770_pm_misc(struct radeon_device *rdev);
Christian König157fa142014-05-27 16:49:20 +0200460void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
461bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100462void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
463void r700_cp_stop(struct radeon_device *rdev);
464void r700_cp_fini(struct radeon_device *rdev);
Christian König57d20a42014-09-04 20:01:53 +0200465struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
466 uint64_t src_offset, uint64_t dst_offset,
467 unsigned num_gpu_pages,
468 struct reservation_object *resv);
Alex Deucher454d2e22013-02-14 10:04:02 -0500469u32 rv770_get_xclk(struct radeon_device *rdev);
Christian Königef0e6e62013-04-08 12:41:35 +0200470int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400471int rv770_get_temp(struct radeon_device *rdev);
Rafał Miłecki8f33a152014-05-16 11:36:24 +0200472/* hdmi */
473void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher66229b22013-06-26 00:11:19 -0400474/* rv7xx pm */
475int rv770_dpm_init(struct radeon_device *rdev);
476int rv770_dpm_enable(struct radeon_device *rdev);
Alex Deuchera3f11242013-12-19 13:48:36 -0500477int rv770_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher66229b22013-06-26 00:11:19 -0400478void rv770_dpm_disable(struct radeon_device *rdev);
479int rv770_dpm_set_power_state(struct radeon_device *rdev);
480void rv770_dpm_setup_asic(struct radeon_device *rdev);
481void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
482void rv770_dpm_fini(struct radeon_device *rdev);
483u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
484u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
485void rv770_dpm_print_power_state(struct radeon_device *rdev,
486 struct radeon_ps *ps);
Alex Deucherbd210d12013-06-28 10:06:26 -0400487void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
488 struct seq_file *m);
Alex Deucher8b5e6b72013-07-02 18:40:35 -0400489int rv770_dpm_force_performance_level(struct radeon_device *rdev,
490 enum radeon_dpm_forced_level level);
Alex Deucherb06195d2013-07-08 11:49:48 -0400491bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000492
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500493/*
494 * evergreen
495 */
Daniel Vetter3574dda2011-02-18 17:59:19 +0100496struct evergreen_mc_save {
Daniel Vetter3574dda2011-02-18 17:59:19 +0100497 u32 vga_render_control;
498 u32 vga_hdp_control;
Alex Deucher62444b72012-08-15 17:18:42 -0400499 bool crtc_enabled[RADEON_MAX_CRTCS];
Daniel Vetter3574dda2011-02-18 17:59:19 +0100500};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400501
Alex Deucher0fcdb612010-03-24 13:20:41 -0400502void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500503int evergreen_init(struct radeon_device *rdev);
504void evergreen_fini(struct radeon_device *rdev);
505int evergreen_suspend(struct radeon_device *rdev);
506int evergreen_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500507bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
508bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000509int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500510void evergreen_bandwidth_update(struct radeon_device *rdev);
Alex Deucher12920592011-02-02 12:37:40 -0500511void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500512void evergreen_hpd_init(struct radeon_device *rdev);
513void evergreen_hpd_fini(struct radeon_device *rdev);
514bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
515void evergreen_hpd_set_polarity(struct radeon_device *rdev,
516 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400517u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
518int evergreen_irq_set(struct radeon_device *rdev);
519int evergreen_irq_process(struct radeon_device *rdev);
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400520extern int evergreen_cs_parse(struct radeon_cs_parser *p);
Alex Deucherd2ead3e2012-12-13 09:55:45 -0500521extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
Alex Deucher49e02b72010-04-23 17:57:27 -0400522extern void evergreen_pm_misc(struct radeon_device *rdev);
523extern void evergreen_pm_prepare(struct radeon_device *rdev);
524extern void evergreen_pm_finish(struct radeon_device *rdev);
Alex Deuchera4c9e2e2011-11-04 10:09:41 -0400525extern void sumo_pm_init_profile(struct radeon_device *rdev);
Alex Deucher27810fb2012-10-01 19:25:11 -0400526extern void btc_pm_init_profile(struct radeon_device *rdev);
Alex Deucher23d33ba2013-04-08 12:41:32 +0200527int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deuchera8b49252013-04-08 12:41:33 +0200528int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Christian König157fa142014-05-27 16:49:20 +0200529extern void evergreen_page_flip(struct radeon_device *rdev, int crtc,
530 u64 crtc_base);
531extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500532extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100533void evergreen_disable_interrupt_state(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500534int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher233d1ad2012-12-04 15:25:59 -0500535void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
536 struct radeon_fence *fence);
537void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
538 struct radeon_ib *ib);
Christian König57d20a42014-09-04 20:01:53 +0200539struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev,
540 uint64_t src_offset, uint64_t dst_offset,
541 unsigned num_gpu_pages,
542 struct reservation_object *resv);
Alex Deuchera973bea2013-04-18 11:32:16 -0400543void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
544void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400545int evergreen_get_temp(struct radeon_device *rdev);
546int sumo_get_temp(struct radeon_device *rdev);
Alex Deucher29a15222012-12-14 11:57:36 -0500547int tn_get_temp(struct radeon_device *rdev);
Alex Deucherdc50ba72013-06-26 00:33:35 -0400548int cypress_dpm_init(struct radeon_device *rdev);
549void cypress_dpm_setup_asic(struct radeon_device *rdev);
550int cypress_dpm_enable(struct radeon_device *rdev);
551void cypress_dpm_disable(struct radeon_device *rdev);
552int cypress_dpm_set_power_state(struct radeon_device *rdev);
553void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
554void cypress_dpm_fini(struct radeon_device *rdev);
Alex Deucherd0b54bd2013-07-08 11:56:09 -0400555bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400556int btc_dpm_init(struct radeon_device *rdev);
557void btc_dpm_setup_asic(struct radeon_device *rdev);
558int btc_dpm_enable(struct radeon_device *rdev);
559void btc_dpm_disable(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500560int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400561int btc_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500562void btc_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400563void btc_dpm_fini(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500564u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
565u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
Alex Deuchera84301c2013-07-08 12:03:55 -0400566bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher9f3f63f2014-01-30 11:19:22 -0500567void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
568 struct seq_file *m);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400569int sumo_dpm_init(struct radeon_device *rdev);
570int sumo_dpm_enable(struct radeon_device *rdev);
Alex Deucher14ec9fa2013-12-19 11:56:52 -0500571int sumo_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400572void sumo_dpm_disable(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400573int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400574int sumo_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400575void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400576void sumo_dpm_setup_asic(struct radeon_device *rdev);
577void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
578void sumo_dpm_fini(struct radeon_device *rdev);
579u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
580u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
581void sumo_dpm_print_power_state(struct radeon_device *rdev,
582 struct radeon_ps *ps);
Alex Deucherfb701602013-06-28 10:47:56 -0400583void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
584 struct seq_file *m);
Alex Deucher5d5e5592013-07-02 18:50:09 -0400585int sumo_dpm_force_performance_level(struct radeon_device *rdev,
586 enum radeon_dpm_forced_level level);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100587
Alex Deuchere3487622011-03-02 20:07:36 -0500588/*
589 * cayman
590 */
Alex Deucherb40e7e12011-11-17 14:57:50 -0500591void cayman_fence_ring_emit(struct radeon_device *rdev,
592 struct radeon_fence *fence);
Alex Deuchere3487622011-03-02 20:07:36 -0500593void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
594int cayman_init(struct radeon_device *rdev);
595void cayman_fini(struct radeon_device *rdev);
596int cayman_suspend(struct radeon_device *rdev);
597int cayman_resume(struct radeon_device *rdev);
Alex Deuchere3487622011-03-02 20:07:36 -0500598int cayman_asic_reset(struct radeon_device *rdev);
Jerome Glisse721604a2012-01-05 22:11:05 -0500599void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
600int cayman_vm_init(struct radeon_device *rdev);
601void cayman_vm_fini(struct radeon_device *rdev);
Christian Königfaffaf62014-11-19 14:01:19 +0100602void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
603 unsigned vm_id, uint64_t pd_addr);
Christian König089a7862012-08-11 11:54:05 +0200604uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
Jerome Glisse721604a2012-01-05 22:11:05 -0500605int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deuchercd459e52012-12-13 12:17:38 -0500606int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500607void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
608 struct radeon_ib *ib);
Alex Deucher123bc182013-01-24 11:37:19 -0500609bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500610bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König03f62ab2014-07-30 21:05:17 +0200611
612void cayman_dma_vm_copy_pages(struct radeon_device *rdev,
613 struct radeon_ib *ib,
614 uint64_t pe, uint64_t src,
615 unsigned count);
616void cayman_dma_vm_write_pages(struct radeon_device *rdev,
617 struct radeon_ib *ib,
618 uint64_t pe,
619 uint64_t addr, unsigned count,
620 uint32_t incr, uint32_t flags);
621void cayman_dma_vm_set_pages(struct radeon_device *rdev,
622 struct radeon_ib *ib,
623 uint64_t pe,
624 uint64_t addr, unsigned count,
625 uint32_t incr, uint32_t flags);
626void cayman_dma_vm_pad_ib(struct radeon_ib *ib);
Christian König24c16432013-10-30 11:51:09 -0400627
Christian Königfaffaf62014-11-19 14:01:19 +0100628void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
629 unsigned vm_id, uint64_t pd_addr);
Alex Deucher45f9a392010-03-24 13:55:51 -0400630
Alex Deucherea31bf62013-12-09 19:44:30 -0500631u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
632 struct radeon_ring *ring);
633u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
634 struct radeon_ring *ring);
635void cayman_gfx_set_wptr(struct radeon_device *rdev,
636 struct radeon_ring *ring);
637uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
638 struct radeon_ring *ring);
639uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
640 struct radeon_ring *ring);
641void cayman_dma_set_wptr(struct radeon_device *rdev,
642 struct radeon_ring *ring);
643
Alex Deucher69e0b572013-04-12 16:42:42 -0400644int ni_dpm_init(struct radeon_device *rdev);
645void ni_dpm_setup_asic(struct radeon_device *rdev);
646int ni_dpm_enable(struct radeon_device *rdev);
647void ni_dpm_disable(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500648int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400649int ni_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500650void ni_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400651void ni_dpm_fini(struct radeon_device *rdev);
652u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
653u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
654void ni_dpm_print_power_state(struct radeon_device *rdev,
655 struct radeon_ps *ps);
Alex Deucherbdf0c4f2013-06-28 17:49:02 -0400656void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
657 struct seq_file *m);
Alex Deucher170a47f2013-07-02 18:43:53 -0400658int ni_dpm_force_performance_level(struct radeon_device *rdev,
659 enum radeon_dpm_forced_level level);
Alex Deucher76ad73e2013-07-08 12:09:41 -0400660bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400661int trinity_dpm_init(struct radeon_device *rdev);
662int trinity_dpm_enable(struct radeon_device *rdev);
Alex Deucherbda44c12013-12-19 12:03:35 -0500663int trinity_dpm_late_enable(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400664void trinity_dpm_disable(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500665int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400666int trinity_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500667void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400668void trinity_dpm_setup_asic(struct radeon_device *rdev);
669void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
670void trinity_dpm_fini(struct radeon_device *rdev);
671u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
672u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
673void trinity_dpm_print_power_state(struct radeon_device *rdev,
674 struct radeon_ps *ps);
Alex Deucher490ab932013-06-28 12:01:38 -0400675void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
676 struct seq_file *m);
Alex Deucher9b5de592013-07-02 18:52:10 -0400677int trinity_dpm_force_performance_level(struct radeon_device *rdev,
678 enum radeon_dpm_forced_level level);
Alex Deucher11877062013-09-09 19:19:52 -0400679void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
Alex Deucherd70229f2013-04-12 16:40:41 -0400680
Alex Deucher43b3cd92012-03-20 17:18:00 -0400681/* DCE6 - SI */
682void dce6_bandwidth_update(struct radeon_device *rdev);
Alex Deucherb5306022013-07-31 16:51:33 -0400683int dce6_audio_init(struct radeon_device *rdev);
684void dce6_audio_fini(struct radeon_device *rdev);
Alex Deucher43b3cd92012-03-20 17:18:00 -0400685
Alex Deucher02779c02012-03-20 17:18:25 -0400686/*
687 * si
688 */
689void si_fence_ring_emit(struct radeon_device *rdev,
690 struct radeon_fence *fence);
691void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
692int si_init(struct radeon_device *rdev);
693void si_fini(struct radeon_device *rdev);
694int si_suspend(struct radeon_device *rdev);
695int si_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500696bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
697bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher02779c02012-03-20 17:18:25 -0400698int si_asic_reset(struct radeon_device *rdev);
699void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
700int si_irq_set(struct radeon_device *rdev);
701int si_irq_process(struct radeon_device *rdev);
702int si_vm_init(struct radeon_device *rdev);
703void si_vm_fini(struct radeon_device *rdev);
Christian Königfaffaf62014-11-19 14:01:19 +0100704void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
705 unsigned vm_id, uint64_t pd_addr);
Alex Deucher02779c02012-03-20 17:18:25 -0400706int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Christian König57d20a42014-09-04 20:01:53 +0200707struct radeon_fence *si_copy_dma(struct radeon_device *rdev,
708 uint64_t src_offset, uint64_t dst_offset,
709 unsigned num_gpu_pages,
710 struct reservation_object *resv);
Christian König03f62ab2014-07-30 21:05:17 +0200711
712void si_dma_vm_copy_pages(struct radeon_device *rdev,
713 struct radeon_ib *ib,
714 uint64_t pe, uint64_t src,
715 unsigned count);
716void si_dma_vm_write_pages(struct radeon_device *rdev,
717 struct radeon_ib *ib,
718 uint64_t pe,
719 uint64_t addr, unsigned count,
720 uint32_t incr, uint32_t flags);
721void si_dma_vm_set_pages(struct radeon_device *rdev,
722 struct radeon_ib *ib,
723 uint64_t pe,
724 uint64_t addr, unsigned count,
725 uint32_t incr, uint32_t flags);
726
Christian Königfaffaf62014-11-19 14:01:19 +0100727void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
728 unsigned vm_id, uint64_t pd_addr);
Alex Deucher454d2e22013-02-14 10:04:02 -0500729u32 si_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500730uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
Christian König2539eb02013-04-08 12:41:34 +0200731int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400732int si_get_temp(struct radeon_device *rdev);
Alex Deuchera9e61412013-06-25 17:56:16 -0400733int si_dpm_init(struct radeon_device *rdev);
734void si_dpm_setup_asic(struct radeon_device *rdev);
735int si_dpm_enable(struct radeon_device *rdev);
Alex Deucher963c1152013-12-19 13:54:35 -0500736int si_dpm_late_enable(struct radeon_device *rdev);
Alex Deuchera9e61412013-06-25 17:56:16 -0400737void si_dpm_disable(struct radeon_device *rdev);
738int si_dpm_pre_set_power_state(struct radeon_device *rdev);
739int si_dpm_set_power_state(struct radeon_device *rdev);
740void si_dpm_post_set_power_state(struct radeon_device *rdev);
741void si_dpm_fini(struct radeon_device *rdev);
742void si_dpm_display_configuration_changed(struct radeon_device *rdev);
Alex Deucher79821282013-06-28 18:02:19 -0400743void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
744 struct seq_file *m);
Alex Deuchera160a6a2013-07-02 18:46:28 -0400745int si_dpm_force_performance_level(struct radeon_device *rdev,
746 enum radeon_dpm_forced_level level);
Alex Deucher02779c02012-03-20 17:18:25 -0400747
Alex Deucher0672e272013-04-09 16:22:31 -0400748/* DCE8 - CIK */
749void dce8_bandwidth_update(struct radeon_device *rdev);
750
Alex Deucher44fa3462012-12-18 22:17:00 -0500751/*
752 * cik
753 */
754uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher2c679122013-04-09 13:32:18 -0400755u32 cik_get_xclk(struct radeon_device *rdev);
Alex Deucher6e2c3c02013-04-03 19:28:32 -0400756uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
757void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Christian König87167bb2013-04-09 13:39:21 -0400758int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher5ad6bf92013-08-22 17:09:06 -0400759int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
Alex Deucher0672e272013-04-09 16:22:31 -0400760void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
761 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100762bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher0672e272013-04-09 16:22:31 -0400763 struct radeon_ring *ring,
764 struct radeon_semaphore *semaphore,
765 bool emit_wait);
766void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian König57d20a42014-09-04 20:01:53 +0200767struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,
768 uint64_t src_offset, uint64_t dst_offset,
769 unsigned num_gpu_pages,
770 struct reservation_object *resv);
771struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
772 uint64_t src_offset, uint64_t dst_offset,
773 unsigned num_gpu_pages,
774 struct reservation_object *resv);
Alex Deucher0672e272013-04-09 16:22:31 -0400775int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
776int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
777bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
778void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
779 struct radeon_fence *fence);
780void cik_fence_compute_ring_emit(struct radeon_device *rdev,
781 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100782bool cik_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher0672e272013-04-09 16:22:31 -0400783 struct radeon_ring *cp,
784 struct radeon_semaphore *semaphore,
785 bool emit_wait);
786void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
787int cik_init(struct radeon_device *rdev);
788void cik_fini(struct radeon_device *rdev);
789int cik_suspend(struct radeon_device *rdev);
790int cik_resume(struct radeon_device *rdev);
791bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
792int cik_asic_reset(struct radeon_device *rdev);
793void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
794int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
795int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
796int cik_irq_set(struct radeon_device *rdev);
797int cik_irq_process(struct radeon_device *rdev);
798int cik_vm_init(struct radeon_device *rdev);
799void cik_vm_fini(struct radeon_device *rdev);
Christian Königfaffaf62014-11-19 14:01:19 +0100800void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
801 unsigned vm_id, uint64_t pd_addr);
Christian König03f62ab2014-07-30 21:05:17 +0200802
803void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
804 struct radeon_ib *ib,
805 uint64_t pe, uint64_t src,
806 unsigned count);
807void cik_sdma_vm_write_pages(struct radeon_device *rdev,
808 struct radeon_ib *ib,
809 uint64_t pe,
810 uint64_t addr, unsigned count,
811 uint32_t incr, uint32_t flags);
812void cik_sdma_vm_set_pages(struct radeon_device *rdev,
813 struct radeon_ib *ib,
814 uint64_t pe,
815 uint64_t addr, unsigned count,
816 uint32_t incr, uint32_t flags);
817void cik_sdma_vm_pad_ib(struct radeon_ib *ib);
818
Christian Königfaffaf62014-11-19 14:01:19 +0100819void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
820 unsigned vm_id, uint64_t pd_addr);
Alex Deucher0672e272013-04-09 16:22:31 -0400821int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherea31bf62013-12-09 19:44:30 -0500822u32 cik_gfx_get_rptr(struct radeon_device *rdev,
823 struct radeon_ring *ring);
824u32 cik_gfx_get_wptr(struct radeon_device *rdev,
825 struct radeon_ring *ring);
826void cik_gfx_set_wptr(struct radeon_device *rdev,
827 struct radeon_ring *ring);
828u32 cik_compute_get_rptr(struct radeon_device *rdev,
829 struct radeon_ring *ring);
830u32 cik_compute_get_wptr(struct radeon_device *rdev,
831 struct radeon_ring *ring);
832void cik_compute_set_wptr(struct radeon_device *rdev,
833 struct radeon_ring *ring);
834u32 cik_sdma_get_rptr(struct radeon_device *rdev,
835 struct radeon_ring *ring);
836u32 cik_sdma_get_wptr(struct radeon_device *rdev,
837 struct radeon_ring *ring);
838void cik_sdma_set_wptr(struct radeon_device *rdev,
839 struct radeon_ring *ring);
Alex Deucher286d9cc2013-06-21 15:50:47 -0400840int ci_get_temp(struct radeon_device *rdev);
841int kv_get_temp(struct radeon_device *rdev);
Alex Deucher44fa3462012-12-18 22:17:00 -0500842
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400843int ci_dpm_init(struct radeon_device *rdev);
844int ci_dpm_enable(struct radeon_device *rdev);
Alex Deucher90208422013-12-19 13:59:46 -0500845int ci_dpm_late_enable(struct radeon_device *rdev);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400846void ci_dpm_disable(struct radeon_device *rdev);
847int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
848int ci_dpm_set_power_state(struct radeon_device *rdev);
849void ci_dpm_post_set_power_state(struct radeon_device *rdev);
850void ci_dpm_setup_asic(struct radeon_device *rdev);
851void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
852void ci_dpm_fini(struct radeon_device *rdev);
853u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
854u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
855void ci_dpm_print_power_state(struct radeon_device *rdev,
856 struct radeon_ps *ps);
Alex Deucher94b4adc2013-07-15 17:34:33 -0400857void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
858 struct seq_file *m);
Alex Deucher89536fd2013-07-15 18:14:24 -0400859int ci_dpm_force_performance_level(struct radeon_device *rdev,
860 enum radeon_dpm_forced_level level);
Alex Deucher54961312013-07-15 18:24:31 -0400861bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher942bdf72013-08-09 10:05:24 -0400862void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400863
Alex Deucher41a524a2013-08-14 01:01:40 -0400864int kv_dpm_init(struct radeon_device *rdev);
865int kv_dpm_enable(struct radeon_device *rdev);
Alex Deucherd8852c32013-12-19 14:03:36 -0500866int kv_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher41a524a2013-08-14 01:01:40 -0400867void kv_dpm_disable(struct radeon_device *rdev);
868int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
869int kv_dpm_set_power_state(struct radeon_device *rdev);
870void kv_dpm_post_set_power_state(struct radeon_device *rdev);
871void kv_dpm_setup_asic(struct radeon_device *rdev);
872void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
873void kv_dpm_fini(struct radeon_device *rdev);
874u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
875u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
876void kv_dpm_print_power_state(struct radeon_device *rdev,
877 struct radeon_ps *ps);
Alex Deucherae3e40e2013-07-18 16:39:53 -0400878void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
879 struct seq_file *m);
Alex Deucher2b4c8022013-07-18 16:48:46 -0400880int kv_dpm_force_performance_level(struct radeon_device *rdev,
881 enum radeon_dpm_forced_level level);
Alex Deucher77df5082013-08-09 10:02:40 -0400882void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Alex Deucherb7a5ae92013-09-09 19:33:08 -0400883void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
Alex Deucher41a524a2013-08-14 01:01:40 -0400884
Christian Könige409b122013-08-13 11:56:53 +0200885/* uvd v1.0 */
886uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
887 struct radeon_ring *ring);
888uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
889 struct radeon_ring *ring);
890void uvd_v1_0_set_wptr(struct radeon_device *rdev,
891 struct radeon_ring *ring);
Christian König856754c2013-04-16 22:11:22 +0200892int uvd_v1_0_resume(struct radeon_device *rdev);
Christian Könige409b122013-08-13 11:56:53 +0200893
894int uvd_v1_0_init(struct radeon_device *rdev);
895void uvd_v1_0_fini(struct radeon_device *rdev);
896int uvd_v1_0_start(struct radeon_device *rdev);
897void uvd_v1_0_stop(struct radeon_device *rdev);
898
899int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König856754c2013-04-16 22:11:22 +0200900void uvd_v1_0_fence_emit(struct radeon_device *rdev,
901 struct radeon_fence *fence);
Christian Könige409b122013-08-13 11:56:53 +0200902int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König1654b812013-11-12 12:58:05 +0100903bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
Christian Könige409b122013-08-13 11:56:53 +0200904 struct radeon_ring *ring,
905 struct radeon_semaphore *semaphore,
906 bool emit_wait);
907void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
908
909/* uvd v2.2 */
910int uvd_v2_2_resume(struct radeon_device *rdev);
911void uvd_v2_2_fence_emit(struct radeon_device *rdev,
912 struct radeon_fence *fence);
913
914/* uvd v3.1 */
Christian König1654b812013-11-12 12:58:05 +0100915bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
Christian Könige409b122013-08-13 11:56:53 +0200916 struct radeon_ring *ring,
917 struct radeon_semaphore *semaphore,
918 bool emit_wait);
919
920/* uvd v4.2 */
921int uvd_v4_2_resume(struct radeon_device *rdev);
922
Christian Königd93f7932013-05-23 12:10:04 +0200923/* vce v1.0 */
924uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
925 struct radeon_ring *ring);
926uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
927 struct radeon_ring *ring);
928void vce_v1_0_set_wptr(struct radeon_device *rdev,
929 struct radeon_ring *ring);
930int vce_v1_0_init(struct radeon_device *rdev);
931int vce_v1_0_start(struct radeon_device *rdev);
932
933/* vce v2.0 */
934int vce_v2_0_resume(struct radeon_device *rdev);
935
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200936#endif