arch/powerpc/boot/dts/mpc832x_mds.dts - LeafOS-Devices/android_kernel_samsung_gta4xl - Gitiles

 /*
  * MPC8323E EMDS Device Tree Source
  *
  * Copyright 2006 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.

  * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
  * this:
  *
  * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
  * 2) Solder a wire from U61-21 to P19A-23.  P19 is a grid of pins on the board
  *    next to the serial ports.
  * 3) Solder a wire from U61-22 to P19K-22.
  *
  * Note that there's a typo in the schematic.  The board labels the last column
  * of pins "P19K", but in the schematic, that column is called "P19J".  So if
  * you're going by the schematic, the pin is called "P19J-K22".
  */

 /dts-v1/;

 / {
 	model = "MPC8323EMDS";
 	compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
 	#address-cells = <1>;
 	#size-cells = <1>;

 	aliases {
 		ethernet0 = &enet0;
 		ethernet1 = &enet1;
 		serial0 = &serial0;
 		serial1 = &serial1;
 		pci0 = &pci0;
 	};

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		PowerPC,8323@0 {
 			device_type = "cpu";
 			reg = <0x0>;
 			d-cache-line-size = <32>;	// 32 bytes
 			i-cache-line-size = <32>;	// 32 bytes
 			d-cache-size = <16384>;		// L1, 16K
 			i-cache-size = <16384>;		// L1, 16K
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
 		};
 	};

 	memory {
 		device_type = "memory";
 		reg = <0x00000000 0x08000000>;
 	};

 	bcsr@f8000000 {
 		compatible = "fsl,mpc8323mds-bcsr";
 		reg = <0xf8000000 0x8000>;
 	};

 	soc8323@e0000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
 		compatible = "simple-bus";
 		ranges = <0x0 0xe0000000 0x00100000>;
 		reg = <0xe0000000 0x00000200>;
 		bus-frequency = <132000000>;

 		wdt@200 {
 			device_type = "watchdog";
 			compatible = "mpc83xx_wdt";
 			reg = <0x200 0x100>;
 		};

 		i2c@3000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			cell-index = <0>;
 			compatible = "fsl-i2c";
 			reg = <0x3000 0x100>;
 			interrupts = <14 0x8>;
 			interrupt-parent = <&ipic>;
 			dfsrr;

 			rtc@68 {
 				compatible = "dallas,ds1374";
 				reg = <0x68>;
 			};
 		};

 		serial0: serial@4500 {
 			cell-index = <0>;
 			device_type = "serial";
 			compatible = "ns16550";
 			reg = <0x4500 0x100>;
 			clock-frequency = <0>;
 			interrupts = <9 0x8>;
 			interrupt-parent = <&ipic>;
 		};

 		serial1: serial@4600 {
 			cell-index = <1>;
 			device_type = "serial";
 			compatible = "ns16550";
 			reg = <0x4600 0x100>;
 			clock-frequency = <0>;
 			interrupts = <10 0x8>;
 			interrupt-parent = <&ipic>;
 		};

 		dma@82a8 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
 			reg = <0x82a8 4>;
 			ranges = <0 0x8100 0x1a8>;
 			interrupt-parent = <&ipic>;
 			interrupts = <71 8>;
 			cell-index = <0>;
 			dma-channel@0 {
 				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 				reg = <0 0x80>;
 				cell-index = <0>;
 				interrupt-parent = <&ipic>;
 				interrupts = <71 8>;
 			};
 			dma-channel@80 {
 				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 				reg = <0x80 0x80>;
 				cell-index = <1>;
 				interrupt-parent = <&ipic>;
 				interrupts = <71 8>;
 			};
 			dma-channel@100 {
 				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 				reg = <0x100 0x80>;
 				cell-index = <2>;
 				interrupt-parent = <&ipic>;
 				interrupts = <71 8>;
 			};
 			dma-channel@180 {
 				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 				reg = <0x180 0x28>;
 				cell-index = <3>;
 				interrupt-parent = <&ipic>;
 				interrupts = <71 8>;
 			};
 		};

 		crypto@30000 {
 			compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 			reg = <0x30000 0x10000>;
 			interrupts = <11 0x8>;
 			interrupt-parent = <&ipic>;
 			fsl,num-channels = <1>;
 			fsl,channel-fifo-len = <24>;
 			fsl,exec-units-mask = <0x4c>;
 			fsl,descriptor-types-mask = <0x0122003f>;
 		};

 		ipic: pic@700 {
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x700 0x100>;
 			device_type = "ipic";
 		};

 		par_io@1400 {
 			reg = <0x1400 0x100>;
 			device_type = "par_io";
 			num-ports = <7>;

 			pio3: ucc_pin@03 {
 				pio-map = <
 			/* port  pin  dir  open_drain  assignment  has_irq */
 					3  4  3  0  2  0  /* MDIO */
 					3  5  1  0  2  0  /* MDC */
 					0 13  2  0  1  0 	/* RX_CLK (CLK9) */
 					3 24  2  0  1  0 	/* TX_CLK (CLK10) */
 					1  0  1  0  1  0 	/* TxD0 */
 					1  1  1  0  1  0 	/* TxD1 */
 					1  2  1  0  1  0 	/* TxD2 */
 					1  3  1  0  1  0 	/* TxD3 */
 					1  4  2  0  1  0 	/* RxD0 */
 					1  5  2  0  1  0 	/* RxD1 */
 					1  6  2  0  1  0 	/* RxD2 */
 					1  7  2  0  1  0 	/* RxD3 */
 					1  8  2  0  1  0 	/* RX_ER */
 					1  9  1  0  1  0 	/* TX_ER */
 					1 10  2  0  1  0 	/* RX_DV */
 					1 11  2  0  1  0 	/* COL */
 					1 12  1  0  1  0 	/* TX_EN */
 					1 13  2  0  1  0>;	/* CRS */
 			};
 			pio4: ucc_pin@04 {
 				pio-map = <
 			/* port  pin  dir  open_drain  assignment  has_irq */
 					3 31  2  0  1  0 	/* RX_CLK (CLK7) */
 					3  6  2  0  1  0 	/* TX_CLK (CLK8) */
 					1 18  1  0  1  0 	/* TxD0 */
 					1 19  1  0  1  0 	/* TxD1 */
 					1 20  1  0  1  0 	/* TxD2 */
 					1 21  1  0  1  0 	/* TxD3 */
 					1 22  2  0  1  0 	/* RxD0 */
 					1 23  2  0  1  0 	/* RxD1 */
 					1 24  2  0  1  0 	/* RxD2 */
 					1 25  2  0  1  0 	/* RxD3 */
 					1 26  2  0  1  0 	/* RX_ER */
 					1 27  1  0  1  0 	/* TX_ER */
 					1 28  2  0  1  0 	/* RX_DV */
 					1 29  2  0  1  0 	/* COL */
 					1 30  1  0  1  0 	/* TX_EN */
 					1 31  2  0  1  0>;	/* CRS */
 			};
 			pio5: ucc_pin@05 {
 				pio-map = <
 				/*
 				 *    		      open       has
 				 *   port  pin  dir  drain  sel  irq
 				 */
 					2    0    1      0    2    0  /* TxD5 */
 					2    8    2      0    2    0  /* RxD5 */

 					2   29    2      0    0    0  /* CTS5 */
 					2   31    1      0    2    0  /* RTS5 */

 					2   24    2      0    0    0  /* CD */

 				>;
 			};

 		};
 	};

 	qe@e0100000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "qe";
 		compatible = "fsl,qe";
 		ranges = <0x0 0xe0100000 0x00100000>;
 		reg = <0xe0100000 0x480>;
 		brg-frequency = <0>;
 		bus-frequency = <198000000>;

 		muram@10000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "fsl,qe-muram", "fsl,cpm-muram";
 			ranges = <0x0 0x00010000 0x00004000>;

 			data-only@0 {
 				compatible = "fsl,qe-muram-data",
 					     "fsl,cpm-muram-data";
 				reg = <0x0 0x4000>;
 			};
 		};

 		spi@4c0 {
 			cell-index = <0>;
 			compatible = "fsl,spi";
 			reg = <0x4c0 0x40>;
 			interrupts = <2>;
 			interrupt-parent = <&qeic>;
 			mode = "cpu";
 		};

 		spi@500 {
 			cell-index = <1>;
 			compatible = "fsl,spi";
 			reg = <0x500 0x40>;
 			interrupts = <1>;
 			interrupt-parent = <&qeic>;
 			mode = "cpu";
 		};

 		usb@6c0 {
 			compatible = "qe_udc";
 			reg = <0x6c0 0x40 0x8b00 0x100>;
 			interrupts = <11>;
 			interrupt-parent = <&qeic>;
 			mode = "slave";
 		};

 		enet0: ucc@2200 {
 			device_type = "network";
 			compatible = "ucc_geth";
 			cell-index = <3>;
 			reg = <0x2200 0x200>;
 			interrupts = <34>;
 			interrupt-parent = <&qeic>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			rx-clock-name = "clk9";
 			tx-clock-name = "clk10";
 			phy-handle = <&phy3>;
 			pio-handle = <&pio3>;
 		};

 		enet1: ucc@3200 {
 			device_type = "network";
 			compatible = "ucc_geth";
 			cell-index = <4>;
 			reg = <0x3200 0x200>;
 			interrupts = <35>;
 			interrupt-parent = <&qeic>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			rx-clock-name = "clk7";
 			tx-clock-name = "clk8";
 			phy-handle = <&phy4>;
 			pio-handle = <&pio4>;
 		};

 		ucc@2400 {
 			device_type = "serial";
 			compatible = "ucc_uart";
 			cell-index = <5>;	/* The UCC number, 1-7*/
 			port-number = <0>;	/* Which ttyQEx device */
 			soft-uart;		/* We need Soft-UART */
 			reg = <0x2400 0x200>;
 			interrupts = <40>;	/* From Table 18-12 */
 			interrupt-parent = < &qeic >;
 			/*
 			 * For Soft-UART, we need to set TX to 1X, which
 			 * means specifying separate clock sources.
 			 */
 			rx-clock-name = "brg5";
 			tx-clock-name = "brg6";
 			pio-handle = < &pio5 >;
 		};


 		mdio@2320 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x2320 0x18>;
 			compatible = "fsl,ucc-mdio";

 			phy3: ethernet-phy@03 {
 				interrupt-parent = <&ipic>;
 				interrupts = <17 0x8>;
 				reg = <0x3>;
 				device_type = "ethernet-phy";
 			};
 			phy4: ethernet-phy@04 {
 				interrupt-parent = <&ipic>;
 				interrupts = <18 0x8>;
 				reg = <0x4>;
 				device_type = "ethernet-phy";
 			};
 		};

 		qeic: interrupt-controller@80 {
 			interrupt-controller;
 			compatible = "fsl,qe-ic";
 			#address-cells = <0>;
 			#interrupt-cells = <1>;
 			reg = <0x80 0x80>;
 			big-endian;
 			interrupts = <32 0x8 33 0x8>; //high:32 low:33
 			interrupt-parent = <&ipic>;
 		};
 	};

 	pci0: pci@e0008500 {
 		cell-index = <1>;
 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 				/* IDSEL 0x11 AD17 */
 				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
 				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
 				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
 				 0x8800 0x0 0x0 0x4 &ipic 23 0x8

 				/* IDSEL 0x12 AD18 */
 				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
 				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
 				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
 				 0x9000 0x0 0x0 0x4 &ipic 21 0x8

 				/* IDSEL 0x13 AD19 */
 				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
 				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
 				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
 				 0x9800 0x0 0x0 0x4 &ipic 22 0x8

 				/* IDSEL 0x15 AD21*/
 				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
 				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
 				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
 				 0xa800 0x0 0x0 0x4 &ipic 23 0x8

 				/* IDSEL 0x16 AD22*/
 				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
 				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
 				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
 				 0xb000 0x0 0x0 0x4 &ipic 22 0x8

 				/* IDSEL 0x17 AD23*/
 				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
 				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
 				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
 				 0xb800 0x0 0x0 0x4 &ipic 21 0x8

 				/* IDSEL 0x18 AD24*/
 				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
 				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
 				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
 				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 		interrupt-parent = <&ipic>;
 		interrupts = <66 0x8>;
 		bus-range = <0x0 0x0>;
 		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 			  0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
 		clock-frequency = <0>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
 		reg = <0xe0008500 0x100		/* internal registers */
 		       0xe0008300 0x8>;		/* config space access registers */
 		compatible = "fsl,mpc8349-pci";
 		device_type = "pci";
 	};
 };
	/*
	* MPC8323E EMDS Device Tree Source
	*
	* Copyright 2006 Freescale Semiconductor Inc.
	*
	* This program is free software; you can redistribute it and/or modify it
	* under the terms of the GNU General Public License as published by the
	* Free Software Foundation; either version 2 of the License, or (at your
	* option) any later version.

	* To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
	* this:
	*
	* 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
	* 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
	* next to the serial ports.
	* 3) Solder a wire from U61-22 to P19K-22.
	*
	* Note that there's a typo in the schematic. The board labels the last column
	* of pins "P19K", but in the schematic, that column is called "P19J". So if
	* you're going by the schematic, the pin is called "P19J-K22".
	*/

	/dts-v1/;

	/ {
	model = "MPC8323EMDS";
	compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
	ethernet0 = &enet0;
	ethernet1 = &enet1;
	serial0 = &serial0;
	serial1 = &serial1;
	pci0 = &pci0;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	PowerPC,8323@0 {
	device_type = "cpu";
	reg = <0x0>;
	d-cache-line-size = <32>; // 32 bytes
	i-cache-line-size = <32>; // 32 bytes
	d-cache-size = <16384>; // L1, 16K
	i-cache-size = <16384>; // L1, 16K
	timebase-frequency = <0>;
	bus-frequency = <0>;
	clock-frequency = <0>;
	};
	};

	memory {
	device_type = "memory";
	reg = <0x00000000 0x08000000>;
	};

	bcsr@f8000000 {
	compatible = "fsl,mpc8323mds-bcsr";
	reg = <0xf8000000 0x8000>;
	};

	soc8323@e0000000 {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	compatible = "simple-bus";
	ranges = <0x0 0xe0000000 0x00100000>;
	reg = <0xe0000000 0x00000200>;
	bus-frequency = <132000000>;

	wdt@200 {
	device_type = "watchdog";
	compatible = "mpc83xx_wdt";
	reg = <0x200 0x100>;
	};

	i2c@3000 {
	#address-cells = <1>;
	#size-cells = <0>;
	cell-index = <0>;
	compatible = "fsl-i2c";
	reg = <0x3000 0x100>;
	interrupts = <14 0x8>;
	interrupt-parent = <&ipic>;
	dfsrr;

	rtc@68 {
	compatible = "dallas,ds1374";
	reg = <0x68>;
	};
	};

	serial0: serial@4500 {
	cell-index = <0>;
	device_type = "serial";
	compatible = "ns16550";
	reg = <0x4500 0x100>;
	clock-frequency = <0>;
	interrupts = <9 0x8>;
	interrupt-parent = <&ipic>;
	};

	serial1: serial@4600 {
	cell-index = <1>;
	device_type = "serial";
	compatible = "ns16550";
	reg = <0x4600 0x100>;
	clock-frequency = <0>;
	interrupts = <10 0x8>;
	interrupt-parent = <&ipic>;
	};

	dma@82a8 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
	reg = <0x82a8 4>;
	ranges = <0 0x8100 0x1a8>;
	interrupt-parent = <&ipic>;
	interrupts = <71 8>;
	cell-index = <0>;
	dma-channel@0 {
	compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
	reg = <0 0x80>;
	cell-index = <0>;
	interrupt-parent = <&ipic>;
	interrupts = <71 8>;
	};
	dma-channel@80 {
	compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
	reg = <0x80 0x80>;
	cell-index = <1>;
	interrupt-parent = <&ipic>;
	interrupts = <71 8>;
	};
	dma-channel@100 {
	compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
	reg = <0x100 0x80>;
	cell-index = <2>;
	interrupt-parent = <&ipic>;
	interrupts = <71 8>;
	};
	dma-channel@180 {
	compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
	reg = <0x180 0x28>;
	cell-index = <3>;
	interrupt-parent = <&ipic>;
	interrupts = <71 8>;
	};
	};

	crypto@30000 {
	compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
	reg = <0x30000 0x10000>;
	interrupts = <11 0x8>;
	interrupt-parent = <&ipic>;
	fsl,num-channels = <1>;
	fsl,channel-fifo-len = <24>;
	fsl,exec-units-mask = <0x4c>;
	fsl,descriptor-types-mask = <0x0122003f>;
	};

	ipic: pic@700 {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <2>;
	reg = <0x700 0x100>;
	device_type = "ipic";
	};

	par_io@1400 {
	reg = <0x1400 0x100>;
	device_type = "par_io";
	num-ports = <7>;

	pio3: ucc_pin@03 {
	pio-map = <
	/* port pin dir open_drain assignment has_irq */
	3 4 3 0 2 0 /* MDIO */
	3 5 1 0 2 0 /* MDC */
	0 13 2 0 1 0 /* RX_CLK (CLK9) */
	3 24 2 0 1 0 /* TX_CLK (CLK10) */
	1 0 1 0 1 0 /* TxD0 */
	1 1 1 0 1 0 /* TxD1 */
	1 2 1 0 1 0 /* TxD2 */
	1 3 1 0 1 0 /* TxD3 */
	1 4 2 0 1 0 /* RxD0 */
	1 5 2 0 1 0 /* RxD1 */
	1 6 2 0 1 0 /* RxD2 */
	1 7 2 0 1 0 /* RxD3 */
	1 8 2 0 1 0 /* RX_ER */
	1 9 1 0 1 0 /* TX_ER */
	1 10 2 0 1 0 /* RX_DV */
	1 11 2 0 1 0 /* COL */
	1 12 1 0 1 0 /* TX_EN */
	1 13 2 0 1 0>; /* CRS */
	};
	pio4: ucc_pin@04 {
	pio-map = <
	/* port pin dir open_drain assignment has_irq */
	3 31 2 0 1 0 /* RX_CLK (CLK7) */
	3 6 2 0 1 0 /* TX_CLK (CLK8) */
	1 18 1 0 1 0 /* TxD0 */
	1 19 1 0 1 0 /* TxD1 */
	1 20 1 0 1 0 /* TxD2 */
	1 21 1 0 1 0 /* TxD3 */
	1 22 2 0 1 0 /* RxD0 */
	1 23 2 0 1 0 /* RxD1 */
	1 24 2 0 1 0 /* RxD2 */
	1 25 2 0 1 0 /* RxD3 */
	1 26 2 0 1 0 /* RX_ER */
	1 27 1 0 1 0 /* TX_ER */
	1 28 2 0 1 0 /* RX_DV */
	1 29 2 0 1 0 /* COL */
	1 30 1 0 1 0 /* TX_EN */
	1 31 2 0 1 0>; /* CRS */
	};
	pio5: ucc_pin@05 {
	pio-map = <
	/*
	* open has
	* port pin dir drain sel irq
	*/
	2 0 1 0 2 0 /* TxD5 */
	2 8 2 0 2 0 /* RxD5 */

	2 29 2 0 0 0 /* CTS5 */
	2 31 1 0 2 0 /* RTS5 */

	2 24 2 0 0 0 /* CD */

	>;
	};

	};
	};

	qe@e0100000 {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "qe";
	compatible = "fsl,qe";
	ranges = <0x0 0xe0100000 0x00100000>;
	reg = <0xe0100000 0x480>;
	brg-frequency = <0>;
	bus-frequency = <198000000>;

	muram@10000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,qe-muram", "fsl,cpm-muram";
	ranges = <0x0 0x00010000 0x00004000>;

	data-only@0 {
	compatible = "fsl,qe-muram-data",
	"fsl,cpm-muram-data";
	reg = <0x0 0x4000>;
	};
	};

	spi@4c0 {
	cell-index = <0>;
	compatible = "fsl,spi";
	reg = <0x4c0 0x40>;
	interrupts = <2>;
	interrupt-parent = <&qeic>;
	mode = "cpu";
	};

	spi@500 {
	cell-index = <1>;
	compatible = "fsl,spi";
	reg = <0x500 0x40>;
	interrupts = <1>;
	interrupt-parent = <&qeic>;
	mode = "cpu";
	};

	usb@6c0 {
	compatible = "qe_udc";
	reg = <0x6c0 0x40 0x8b00 0x100>;
	interrupts = <11>;
	interrupt-parent = <&qeic>;
	mode = "slave";
	};

	enet0: ucc@2200 {
	device_type = "network";
	compatible = "ucc_geth";
	cell-index = <3>;
	reg = <0x2200 0x200>;
	interrupts = <34>;
	interrupt-parent = <&qeic>;
	local-mac-address = [ 00 00 00 00 00 00 ];
	rx-clock-name = "clk9";
	tx-clock-name = "clk10";
	phy-handle = <&phy3>;
	pio-handle = <&pio3>;
	};

	enet1: ucc@3200 {
	device_type = "network";
	compatible = "ucc_geth";
	cell-index = <4>;
	reg = <0x3200 0x200>;
	interrupts = <35>;
	interrupt-parent = <&qeic>;
	local-mac-address = [ 00 00 00 00 00 00 ];
	rx-clock-name = "clk7";
	tx-clock-name = "clk8";
	phy-handle = <&phy4>;
	pio-handle = <&pio4>;
	};

	ucc@2400 {
	device_type = "serial";
	compatible = "ucc_uart";
	cell-index = <5>; /* The UCC number, 1-7*/
	port-number = <0>; /* Which ttyQEx device */
	soft-uart; /* We need Soft-UART */
	reg = <0x2400 0x200>;
	interrupts = <40>; /* From Table 18-12 */
	interrupt-parent = < &qeic >;
	/*
	* For Soft-UART, we need to set TX to 1X, which
	* means specifying separate clock sources.
	*/
	rx-clock-name = "brg5";
	tx-clock-name = "brg6";
	pio-handle = < &pio5 >;
	};


	mdio@2320 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x2320 0x18>;
	compatible = "fsl,ucc-mdio";

	phy3: ethernet-phy@03 {
	interrupt-parent = <&ipic>;
	interrupts = <17 0x8>;
	reg = <0x3>;
	device_type = "ethernet-phy";
	};
	phy4: ethernet-phy@04 {
	interrupt-parent = <&ipic>;
	interrupts = <18 0x8>;
	reg = <0x4>;
	device_type = "ethernet-phy";
	};
	};

	qeic: interrupt-controller@80 {
	interrupt-controller;
	compatible = "fsl,qe-ic";
	#address-cells = <0>;
	#interrupt-cells = <1>;
	reg = <0x80 0x80>;
	big-endian;
	interrupts = <32 0x8 33 0x8>; //high:32 low:33
	interrupt-parent = <&ipic>;
	};
	};

	pci0: pci@e0008500 {
	cell-index = <1>;
	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	interrupt-map = <
	/* IDSEL 0x11 AD17 */
	0x8800 0x0 0x0 0x1 &ipic 20 0x8
	0x8800 0x0 0x0 0x2 &ipic 21 0x8
	0x8800 0x0 0x0 0x3 &ipic 22 0x8
	0x8800 0x0 0x0 0x4 &ipic 23 0x8

	/* IDSEL 0x12 AD18 */
	0x9000 0x0 0x0 0x1 &ipic 22 0x8
	0x9000 0x0 0x0 0x2 &ipic 23 0x8
	0x9000 0x0 0x0 0x3 &ipic 20 0x8
	0x9000 0x0 0x0 0x4 &ipic 21 0x8

	/* IDSEL 0x13 AD19 */
	0x9800 0x0 0x0 0x1 &ipic 23 0x8
	0x9800 0x0 0x0 0x2 &ipic 20 0x8
	0x9800 0x0 0x0 0x3 &ipic 21 0x8
	0x9800 0x0 0x0 0x4 &ipic 22 0x8

	/* IDSEL 0x15 AD21*/
	0xa800 0x0 0x0 0x1 &ipic 20 0x8
	0xa800 0x0 0x0 0x2 &ipic 21 0x8
	0xa800 0x0 0x0 0x3 &ipic 22 0x8
	0xa800 0x0 0x0 0x4 &ipic 23 0x8

	/* IDSEL 0x16 AD22*/
	0xb000 0x0 0x0 0x1 &ipic 23 0x8
	0xb000 0x0 0x0 0x2 &ipic 20 0x8
	0xb000 0x0 0x0 0x3 &ipic 21 0x8
	0xb000 0x0 0x0 0x4 &ipic 22 0x8

	/* IDSEL 0x17 AD23*/
	0xb800 0x0 0x0 0x1 &ipic 22 0x8
	0xb800 0x0 0x0 0x2 &ipic 23 0x8
	0xb800 0x0 0x0 0x3 &ipic 20 0x8
	0xb800 0x0 0x0 0x4 &ipic 21 0x8

	/* IDSEL 0x18 AD24*/
	0xc000 0x0 0x0 0x1 &ipic 21 0x8
	0xc000 0x0 0x0 0x2 &ipic 22 0x8
	0xc000 0x0 0x0 0x3 &ipic 23 0x8
	0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
	interrupt-parent = <&ipic>;
	interrupts = <66 0x8>;
	bus-range = <0x0 0x0>;
	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
	clock-frequency = <0>;
	#interrupt-cells = <1>;
	#size-cells = <2>;
	#address-cells = <3>;
	reg = <0xe0008500 0x100 /* internal registers */
	0xe0008300 0x8>; /* config space access registers */
	compatible = "fsl,mpc8349-pci";
	device_type = "pci";
	};
	};