| /dts-v1/; |
| |
| /memreserve/ 0x00000000 0x00001000; // reserved |
| /memreserve/ 0x00001000 0x000ef000; // ROM data |
| /memreserve/ 0x000f0000 0x004cc000; // reserved |
| |
| #include <dt-bindings/interrupt-controller/mips-gic.h> |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "mti,sead-3"; |
| interrupt-parent = <&gic>; |
| |
| cpus { |
| cpu@0 { |
| compatible = "mti,mips14KEc", "mti,mips14Kc"; |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <0x0 0x08000000>; |
| }; |
| |
| cpu_intc: interrupt-controller { |
| compatible = "mti,cpu-interrupt-controller"; |
| |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| |
| gic: interrupt-controller@1b1c0000 { |
| compatible = "mti,gic"; |
| reg = <0x1b1c0000 0x20000>; |
| |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| |
| /* |
| * Declare the interrupt-parent even though the mti,gic |
| * binding doesn't require it, such that the kernel can |
| * figure out that cpu_intc is the root interrupt |
| * controller & should be probed first. |
| */ |
| interrupt-parent = <&cpu_intc>; |
| |
| timer { |
| compatible = "mti,gic-timer"; |
| interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; |
| }; |
| }; |
| }; |