arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts

/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * Device Tree file for MACCHIATOBin Armada 8040 community board platform
 */

#include "armada-8040.dtsi"

/ {
	model = "Marvell 8040 MACHIATOBin";
	compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
			"marvell,armada-ap806-quad", "marvell,armada-ap806";

	memory@00000000 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	/* Regulator labels correspond with schematics */
	v_3_3: regulator-3-3v {
		compatible = "regulator-fixed";
		regulator-name = "v_3_3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		status = "okay";
	};

	v_vddo_h: regulator-1-8v {
		compatible = "regulator-fixed";
		regulator-name = "v_vddo_h";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		status = "okay";
	};

	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
		compatible = "regulator-fixed";
		regulator-name = "v_5v0_usb3_hst_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		/* actually GPIO controlled, but 8k has no GPIO support yet */
		regulator-always-on;
		status = "okay";
	};

	usb3h0_phy: usb3_phy0 {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&v_5v0_usb3_hst_vbus>;
	};
};

&uart0 {
	status = "okay";
};

&ap_sdhci0 {
	bus-width = <8>;
	/*
	 * Not stable in HS modes - phy needs "more calibration", so add
	 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
	 */
	marvell,xenon-phy-slow-mode;
	no-1-8-v;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
	vqmmc-supply = <&v_vddo_h>;
};

&cpm_i2c0 {
	clock-frequency = <100000>;
	status = "okay";
};

&cpm_mdio {
	status = "okay";

	ge_phy: ethernet-phy@0 {
		reg = <0>;
	};
};

&cpm_sata0 {
	/* CPM Lane 0 - U29 */
	status = "okay";
};

&cpm_sdhci0 {
	/* U6 */
	broken-cd;
	bus-width = <4>;
	status = "okay";
	vqmmc-supply = <&v_3_3>;
};

&cpm_usb3_0 {
	/* J38? - USB2.0 only */
	status = "okay";
};

&cpm_usb3_1 {
	/* J38? - USB2.0 only */
	status = "okay";
};

&cps_ethernet {
	status = "okay";
};

&cps_eth1 {
	/* CPS Lane 0 - J5 (Gigabit RJ45) */
	status = "okay";
	phy = <&ge_phy>;
	phy-mode = "sgmii";
};

&cps_sata0 {
	/* CPS Lane 1 - U32 */
	/* CPS Lane 3 - U31 */
	status = "okay";
};

&cps_spi1 {
	status = "okay";

	spi-flash@0 {
		compatible = "st,w25q32";
		spi-max-frequency = <50000000>;
		reg = <0>;
	};
};

&cps_usb3_0 {
	/* CPS Lane 2 - CON7 */
	usb-phy = <&usb3h0_phy>;
	status = "okay";
};