| #include "../cmucal.h" |
| #include "cmucal-node.h" |
| #include "cmucal-sfr.h" |
| |
| /*=================CMUCAL version: S5E9610================================*/ |
| |
| /*====================The section of PLL rate tables===================*/ |
| struct cmucal_pll_table pll_shared0_rate_table[] = { |
| PLL_RATE_MPS(1599000000, 246, 4, 0), |
| }; |
| |
| struct cmucal_pll_table pll_shared1_rate_table[] = { |
| PLL_RATE_MPS(1332500000, 205, 4, 0), |
| }; |
| |
| struct cmucal_pll_table pll_mmc_rate_table[] = { |
| PLL_RATE_MPSK(799999878, 31, 1, 0, -15124), |
| }; |
| |
| struct cmucal_pll_table pll_cpucl0_rate_table[] = { |
| PLL_RATE_MPS(1049750000, 323, 4, 1), |
| PLL_RATE_MPS(1449500000, 223, 4, 0), |
| PLL_RATE_MPS(1850333252, 427, 6, 0), |
| PLL_RATE_MPS(300083344, 277, 6, 2), |
| PLL_RATE_MPS(600166687, 277, 6, 1), |
| }; |
| |
| struct cmucal_pll_table pll_cpucl1_rate_table[] = { |
| PLL_RATE_MPS(1499333374, 346, 3, 1), |
| PLL_RATE_MPS(1898000000, 292, 4, 0), |
| PLL_RATE_MPS(2400666748, 277, 3, 0), |
| PLL_RATE_MPS(549899963, 423, 5, 2), |
| PLL_RATE_MPS(850200012, 327, 5, 1), |
| }; |
| |
| struct cmucal_pll_table pll_aud_rate_table[] = { |
| PLL_RATE_MPSK(1179648071, 45, 1, 0, 24319), |
| PLL_RATE_MPSK(1083801600, 42, 1, 0, -20665), |
| }; |
| |
| struct cmucal_pll_table pll_g3d_rate_table[] = { |
| PLL_RATE_MPS(750000000, 375, 13, 0), |
| PLL_RATE_MPS(1000000061, 500, 13, 0), |
| PLL_RATE_MPS(1200000000, 600, 13, 0), |
| PLL_RATE_MPS(300000000, 600, 13, 2), |
| PLL_RATE_MPS(550000000, 550, 13, 1), |
| }; |
| |
| struct cmucal_pll_table pll_mif_rate_table[] = { |
| PLL_RATE_MPS(4264000000, 492, 3, 0), |
| PLL_RATE_MPS(1399666626, 323, 3, 1), |
| PLL_RATE_MPS(1332500000, 410, 4, 1), |
| }; |
| |
| struct cmucal_pll_table pll_mif1_rate_table[] = { |
| PLL_RATE_MPS(100000000, 0, 0, 0), |
| }; |
| |
| /*====================The section of PLLs===================*/ |
| unsigned int cmucal_pll_size = 9; |
| |
| struct cmucal_pll cmucal_pll_list[] = { |
| CLK_PLL(PLL_1051X, PLL_SHARED0, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED0_ENABLE, PLL_CON0_PLL_SHARED0_STABLE, PLL_CON0_PLL_SHARED0_DIV_P, PLL_CON0_PLL_SHARED0_DIV_M, PLL_CON0_PLL_SHARED0_DIV_S, EMPTY_CAL_ID, pll_shared0_rate_table, 150, 0), |
| CLK_PLL(PLL_1051X, PLL_SHARED1, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED1_ENABLE, PLL_CON0_PLL_SHARED1_STABLE, PLL_CON0_PLL_SHARED1_DIV_P, PLL_CON0_PLL_SHARED1_DIV_M, PLL_CON0_PLL_SHARED1_DIV_S, EMPTY_CAL_ID, pll_shared1_rate_table, 150, 0), |
| CLK_PLL(PLL_1061X, PLL_MMC, OSCCLK_CMU, PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, PLL_CON0_PLL_MMC_ENABLE, PLL_CON0_PLL_MMC_STABLE, PLL_CON0_PLL_MMC_DIV_P, PLL_CON0_PLL_MMC_DIV_M, PLL_CON0_PLL_MMC_DIV_S, PLL_CON3_PLL_MMC_DIV_K, pll_mmc_rate_table, 150, 1500), |
| CLK_PLL(PLL_1051X, PLL_CPUCL0, OSCCLK_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON0_PLL_CPUCL0_ENABLE, PLL_CON0_PLL_CPUCL0_STABLE, PLL_CON0_PLL_CPUCL0_DIV_P, PLL_CON0_PLL_CPUCL0_DIV_M, PLL_CON0_PLL_CPUCL0_DIV_S, EMPTY_CAL_ID, pll_cpucl0_rate_table, 150, 0), |
| CLK_PLL(PLL_1054X, PLL_CPUCL1, OSCCLK_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON0_PLL_CPUCL1_ENABLE, PLL_CON0_PLL_CPUCL1_STABLE, PLL_CON0_PLL_CPUCL1_DIV_P, PLL_CON0_PLL_CPUCL1_DIV_M, PLL_CON0_PLL_CPUCL1_DIV_S, EMPTY_CAL_ID, pll_cpucl1_rate_table, 0, 0), |
| CLK_PLL(PLL_1061X, PLL_AUD, OSCCLK_DISPAUD, PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, PLL_CON0_PLL_AUD_ENABLE, PLL_CON0_PLL_AUD_STABLE, PLL_CON0_PLL_AUD_DIV_P, PLL_CON0_PLL_AUD_DIV_M, PLL_CON0_PLL_AUD_DIV_S, PLL_CON3_PLL_AUD_DIV_K, pll_aud_rate_table, 150, 1500), |
| CLK_PLL(PLL_1052X, PLL_G3D, OSCCLK_G3D, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, PLL_CON0_PLL_G3D_ENABLE, PLL_CON0_PLL_G3D_STABLE, PLL_CON0_PLL_G3D_DIV_P, PLL_CON0_PLL_G3D_DIV_M, PLL_CON0_PLL_G3D_DIV_S, EMPTY_CAL_ID, pll_g3d_rate_table, 150, 0), |
| CLK_PLL(PLL_1050X, PLL_MIF, OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, PLL_CON0_PLL_MIF_ENABLE, PLL_CON0_PLL_MIF_STABLE, PLL_CON0_PLL_MIF_DIV_P, PLL_CON0_PLL_MIF_DIV_M, PLL_CON0_PLL_MIF_DIV_S, EMPTY_CAL_ID, pll_mif_rate_table, 150, 0), |
| CLK_PLL(PLL_1050X, PLL_MIF1, OSCCLK_MIF1, PLL_LOCKTIME_PLL_MIF1_PLL_LOCK_TIME, PLL_CON0_PLL_MIF1_ENABLE, PLL_CON0_PLL_MIF1_STABLE, PLL_CON0_PLL_MIF1_DIV_P, PLL_CON0_PLL_MIF1_DIV_M, PLL_CON0_PLL_MIF1_DIV_S, EMPTY_CAL_ID, pll_mif1_rate_table, 150, 0), |
| }; |
| |
| /*====================The section of MUXs' parents===================*/ |
| enum clk_id cmucal_mux_clk_apm_bus_parents[] = { |
| MUX_CLKCMU_APM_BUS_USER, |
| MUX_DLL_USER, |
| }; |
| enum clk_id cmucal_mux_clkcmu_shub_bus_parents[] = { |
| MUX_CLKCMU_APM_BUS_USER, |
| MUX_DLL_USER, |
| }; |
| enum clk_id cmucal_mux_clk_cmgp_usi01_parents[] = { |
| OSCCLK_RCO_CMGP, |
| CLKCMU_CMGP_BUS, |
| }; |
| enum clk_id cmucal_mux_clk_cmgp_i2c_parents[] = { |
| OSCCLK_RCO_CMGP, |
| CLKCMU_CMGP_BUS, |
| }; |
| enum clk_id cmucal_mux_clk_cmgp_usi00_parents[] = { |
| OSCCLK_RCO_CMGP, |
| CLKCMU_CMGP_BUS, |
| }; |
| enum clk_id cmucal_mux_clk_cmgp_usi04_parents[] = { |
| OSCCLK_RCO_CMGP, |
| CLKCMU_CMGP_BUS, |
| }; |
| enum clk_id cmucal_mux_clk_cmgp_usi02_parents[] = { |
| OSCCLK_RCO_CMGP, |
| CLKCMU_CMGP_BUS, |
| }; |
| enum clk_id cmucal_mux_clk_cmgp_usi03_parents[] = { |
| OSCCLK_RCO_CMGP, |
| CLKCMU_CMGP_BUS, |
| }; |
| enum clk_id cmucal_mux_clk_cmgp_adc_parents[] = { |
| OSCCLK_CMGP, |
| DIV_CLK_CMGP_ADC, |
| }; |
| enum clk_id cmucal_mux_clkcmu_g2d_mscl_parents[] = { |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_dispaud_disp_parents[] = { |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_bus_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_mmc_embd_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_MMC, |
| OSCCLK_CMU, |
| OSCCLK_CMU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_bus_parents[] = { |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_ip_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| OSCCLK_CMU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_mmc_card_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_MMC, |
| OSCCLK_CMU, |
| OSCCLK_CMU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cis_clk0_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cis_clk1_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cis_clk2_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_cmu_cmuref_parents[] = { |
| OSCCLK_CMU, |
| DIV_CLK_CMU_CMUREF, |
| }; |
| enum clk_id cmucal_mux_clk_cmu_cmuref_parents[] = { |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_apm_bus_parents[] = { |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_core_cci_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_MMC_DIV2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_core_g3d_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_MMC_DIV2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_core_bus_parents[] = { |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED0_DIV4, |
| PLL_MMC_DIV2, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mif_busp_parents[] = { |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| PLL_MMC_DIV2, |
| OSCCLK_CMU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_ufs_embd_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| OSCCLK_CMU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cam_bus_parents[] = { |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_vipx1_bus_parents[] = { |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_isp_bus_parents[] = { |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_isp_vra_parents[] = { |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_isp_gdc_parents[] = { |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_g2d_g2d_parents[] = { |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cpucl0_switch_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cpucl1_switch_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| }; |
| enum clk_id cmucal_mux_clkcmu_g3d_switch_parents[] = { |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| }; |
| enum clk_id cmucal_mux_clkcmu_dispaud_cpu_parents[] = { |
| PLL_SHARED1, |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_MMC, |
| OSCCLK_CMU, |
| OSCCLK_CMU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mif_switch_parents[] = { |
| PLL_SHARED0, |
| PLL_SHARED1, |
| PLL_SHARED0_DIV2, |
| PLL_MMC, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_parents[] = { |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_usb_bus_parents[] = { |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_usb_usb30drd_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| OSCCLK_CMU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_usb_dpgtc_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| OSCCLK_CMU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_dispaud_aud_parents[] = { |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mfc_mfc_parents[] = { |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mfc_wfd_parents[] = { |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_hpm_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV2, |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_MMC_DIV2, |
| OSCCLK_CMU, |
| OSCCLK_CMU, |
| OSCCLK_CMU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_uart_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| PLL_SHARED1_DIV4, |
| OSCCLK_CMU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_vipx2_bus_parents[] = { |
| PLL_SHARED1_DIV2, |
| PLL_SHARED0_DIV3, |
| PLL_SHARED1_DIV3, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cis_clk3_parents[] = { |
| OSCCLK_CMU, |
| PLL_SHARED0_DIV4, |
| }; |
| enum clk_id cmucal_mux_clk_core_gic_parents[] = { |
| DIV_CLK_CORE_BUSP, |
| OSCCLK_CORE, |
| }; |
| enum clk_id cmucal_mux_clk_cpucl0_pll_parents[] = { |
| PLL_CPUCL0, |
| MUX_CLKCMU_CPUCL0_SWITCH_USER, |
| }; |
| enum clk_id cmucal_mux_clk_cpucl1_pll_parents[] = { |
| PLL_CPUCL1, |
| MUX_CLKCMU_CPUCL1_SWITCH_USER, |
| }; |
| enum clk_id cmucal_mux_clk_aud_cpu_parents[] = { |
| DIV_CLK_AUD_CPU, |
| MUX_CLKCMU_DISPAUD_CPU_USER, |
| }; |
| enum clk_id cmucal_mux_clk_aud_uaif0_parents[] = { |
| DIV_CLK_AUD_UAIF0, |
| IOCLK_AUDIOCDCLK0, |
| }; |
| enum clk_id cmucal_mux_clk_aud_uaif2_parents[] = { |
| DIV_CLK_AUD_UAIF2, |
| IOCLK_AUDIOCDCLK2, |
| }; |
| enum clk_id cmucal_mux_clk_aud_uaif1_parents[] = { |
| DIV_CLK_AUD_UAIF1, |
| IOCLK_AUDIOCDCLK1, |
| }; |
| enum clk_id cmucal_mux_clk_aud_cpu_hch_parents[] = { |
| MUX_CLK_AUD_CPU, |
| OSCCLK_DISPAUD, |
| }; |
| enum clk_id cmucal_mux_clk_aud_fm_parents[] = { |
| OSCCLK_DISPAUD, |
| DIV_CLK_AUD_FM_SPDY, |
| }; |
| enum clk_id cmucal_mux_clk_aud_bus_parents[] = { |
| DIV_CLK_AUD_BUS, |
| MUX_CLKCMU_DISPAUD_AUD_USER, |
| }; |
| enum clk_id cmucal_mux_clk_g3d_busd_parents[] = { |
| PLL_G3D, |
| MUX_CLKCMU_G3D_SWITCH_USER, |
| }; |
| enum clk_id cmucal_mux_clk_mif_ddrphy_clk2x_parents[] = { |
| PLL_MIF, |
| CLKCMU_MIF_SWITCH, |
| }; |
| enum clk_id cmucal_mux_mif_cmuref_parents[] = { |
| OSCCLK_MIF, |
| MUX_CLKCMU_MIF_BUSP_USER, |
| }; |
| enum clk_id cmucal_mux_clk_mif1_ddrphy_clk2x_parents[] = { |
| PLL_MIF1, |
| CLKCMU_MIF_SWITCH, |
| }; |
| enum clk_id cmucal_mux_mif1_cmuref_parents[] = { |
| OSCCLK_MIF1, |
| MUX_CLKCMU_MIF1_BUSP_USER, |
| }; |
| enum clk_id cmucal_mux_clk_shub_usi00_parents[] = { |
| OSCCLK_RCO_SHUB__ALV, |
| MUX_CLKCMU_SHUB_BUS_USER, |
| }; |
| enum clk_id cmucal_mux_clk_shub_usi01_parents[] = { |
| OSCCLK_RCO_SHUB__ALV, |
| MUX_CLKCMU_SHUB_BUS_USER, |
| }; |
| enum clk_id cmucal_mux_clk_shub_i2c_parents[] = { |
| OSCCLK_RCO_SHUB__ALV, |
| MUX_CLKCMU_SHUB_BUS_USER, |
| }; |
| enum clk_id cmucal_mux_clkcmu_apm_bus_user_parents[] = { |
| OSCCLK_RCO_APM, |
| CLKCMU_APM_BUS, |
| }; |
| enum clk_id cmucal_mux_dll_user_parents[] = { |
| OSCCLK_RCO_APM, |
| CLK_DLL_DCO, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cam_bus_user_parents[] = { |
| OSCCLK_CAM, |
| CLKCMU_CAM_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_core_bus_user_parents[] = { |
| OSCCLK_CORE, |
| CLKCMU_CORE_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_core_cci_user_parents[] = { |
| OSCCLK_CORE, |
| CLKCMU_CORE_CCI, |
| }; |
| enum clk_id cmucal_mux_clkcmu_core_g3d_user_parents[] = { |
| OSCCLK_CORE, |
| CLKCMU_CORE_G3D, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cpucl0_switch_user_parents[] = { |
| OSCCLK_CPUCL0, |
| CLKCMU_CPUCL0_SWITCH, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_user_parents[] = { |
| OSCCLK_CPUCL0, |
| CLKCMU_CPUCL0_DBG, |
| }; |
| enum clk_id cmucal_mux_clkcmu_cpucl1_switch_user_parents[] = { |
| OSCCLK_CPUCL1, |
| CLKCMU_CPUCL1_SWITCH, |
| }; |
| enum clk_id cmucal_mux_clkcmu_dispaud_cpu_user_parents[] = { |
| OSCCLK_DISPAUD, |
| CLKCMU_DISPAUD_CPU, |
| }; |
| enum clk_id cmucal_mux_clkcmu_dispaud_disp_user_parents[] = { |
| OSCCLK_DISPAUD, |
| CLKCMU_DISPAUD_DISP, |
| }; |
| enum clk_id cmucal_mux_clkcmu_dispaud_aud_user_parents[] = { |
| OSCCLK_DISPAUD, |
| CLKCMU_DISPAUD_AUD, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_bus_user_parents[] = { |
| OSCCLK_FSYS, |
| CLKCMU_FSYS_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_mmc_card_user_parents[] = { |
| OSCCLK_FSYS, |
| CLKCMU_FSYS_MMC_CARD, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_mmc_embd_user_parents[] = { |
| OSCCLK_FSYS, |
| CLKCMU_FSYS_MMC_EMBD, |
| }; |
| enum clk_id cmucal_mux_clkcmu_fsys_ufs_embd_user_parents[] = { |
| OSCCLK_FSYS, |
| CLKCMU_FSYS_UFS_EMBD, |
| }; |
| enum clk_id cmucal_mux_clkcmu_g2d_mscl_user_parents[] = { |
| OSCCLK_G2D, |
| CLKCMU_G2D_MSCL, |
| }; |
| enum clk_id cmucal_mux_clkcmu_g2d_g2d_user_parents[] = { |
| OSCCLK_G2D, |
| CLKCMU_G2D_G2D, |
| }; |
| enum clk_id cmucal_mux_clkcmu_g3d_switch_user_parents[] = { |
| OSCCLK_G3D, |
| CLKCMU_G3D_SWITCH, |
| }; |
| enum clk_id cmucal_mux_clkcmu_isp_bus_user_parents[] = { |
| OSCCLK_ISP, |
| CLKCMU_ISP_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_isp_vra_user_parents[] = { |
| OSCCLK_ISP, |
| CLKCMU_ISP_VRA, |
| }; |
| enum clk_id cmucal_mux_clkcmu_isp_gdc_user_parents[] = { |
| OSCCLK_ISP, |
| CLKCMU_ISP_GDC, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mfc_wfd_user_parents[] = { |
| OSCCLK_MFC, |
| CLKCMU_MFC_WFD, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mfc_mfc_user_parents[] = { |
| OSCCLK_MFC, |
| CLKCMU_MFC_MFC, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mif_busp_user_parents[] = { |
| OSCCLK_MIF, |
| CLKCMU_MIF_BUSP, |
| }; |
| enum clk_id cmucal_mux_clkcmu_mif1_busp_user_parents[] = { |
| OSCCLK_MIF1, |
| CLKCMU_MIF_BUSP, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_bus_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_ip_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_IP, |
| }; |
| enum clk_id cmucal_mux_clkcmu_peri_uart_user_parents[] = { |
| OSCCLK_PERI, |
| CLKCMU_PERI_UART, |
| }; |
| enum clk_id cmucal_mux_clkcmu_shub_bus_user_parents[] = { |
| OSCCLK_RCO_SHUB__ALV, |
| CLKCMU_SHUB_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_usb_bus_user_parents[] = { |
| OSCCLK_USB, |
| CLKCMU_USB_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_usb_usb30drd_user_parents[] = { |
| OSCCLK_USB, |
| CLKCMU_USB_USB30DRD, |
| }; |
| enum clk_id cmucal_mux_clkcmu_usb_dpgtc_user_parents[] = { |
| OSCCLK_USB, |
| CLKCMU_USB_DPGTC, |
| }; |
| enum clk_id cmucal_mux_clkcmu_vipx1_bus_user_parents[] = { |
| OSCCLK_VIPX1, |
| CLKCMU_VIPX1_BUS, |
| }; |
| enum clk_id cmucal_mux_clkcmu_vipx2_bus_user_parents[] = { |
| OSCCLK_VIPX2, |
| CLKCMU_VIPX2_BUS, |
| }; |
| |
| |
| /*====================The section of MUXs===================*/ |
| unsigned int cmucal_mux_size = 124; |
| |
| |
| struct cmucal_mux cmucal_mux_list[] = { |
| CLK_MUX(MUX_CLK_APM_BUS, cmucal_mux_clk_apm_bus_parents, CLK_CON_MUX_MUX_CLK_APM_BUS_SELECT, CLK_CON_MUX_MUX_CLK_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_SHUB_BUS, cmucal_mux_clkcmu_shub_bus_parents, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CMGP_USI01, cmucal_mux_clk_cmgp_usi01_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI01_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI01_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI01_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CMGP_I2C, cmucal_mux_clk_cmgp_i2c_parents, CLK_CON_MUX_MUX_CLK_CMGP_I2C_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CMGP_USI00, cmucal_mux_clk_cmgp_usi00_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI00_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI00_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI00_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CMGP_USI04, cmucal_mux_clk_cmgp_usi04_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI04_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI04_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI04_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CMGP_USI02, cmucal_mux_clk_cmgp_usi02_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI02_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI02_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI02_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CMGP_USI03, cmucal_mux_clk_cmgp_usi03_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI03_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI03_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI03_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CMGP_ADC, cmucal_mux_clk_cmgp_adc_parents, CLK_CON_MUX_MUX_CLK_CMGP_ADC_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_ADC_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_G2D_MSCL, cmucal_mux_clkcmu_g2d_mscl_parents, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_SELECT, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_DISPAUD_DISP, cmucal_mux_clkcmu_dispaud_disp_parents, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_SELECT, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_BUS, cmucal_mux_clkcmu_fsys_bus_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_MMC_EMBD, cmucal_mux_clkcmu_fsys_mmc_embd_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_BUS, cmucal_mux_clkcmu_peri_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_IP, cmucal_mux_clkcmu_peri_ip_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_MMC_CARD, cmucal_mux_clkcmu_fsys_mmc_card_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CIS_CLK0, cmucal_mux_clkcmu_cis_clk0_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CIS_CLK1, cmucal_mux_clkcmu_cis_clk1_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CIS_CLK2, cmucal_mux_clkcmu_cis_clk2_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CMU_CMUREF, cmucal_mux_cmu_cmuref_parents, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CMU_CMUREF, cmucal_mux_clk_cmu_cmuref_parents, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_APM_BUS, cmucal_mux_clkcmu_apm_bus_parents, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CORE_CCI, cmucal_mux_clkcmu_core_cci_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CORE_G3D, cmucal_mux_clkcmu_core_g3d_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CORE_BUS, cmucal_mux_clkcmu_core_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MIF_BUSP, cmucal_mux_clkcmu_mif_busp_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_UFS_EMBD, cmucal_mux_clkcmu_fsys_ufs_embd_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CAM_BUS, cmucal_mux_clkcmu_cam_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_VIPX1_BUS, cmucal_mux_clkcmu_vipx1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_ISP_BUS, cmucal_mux_clkcmu_isp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_ISP_VRA, cmucal_mux_clkcmu_isp_vra_parents, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_ISP_GDC, cmucal_mux_clkcmu_isp_gdc_parents, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_G2D_G2D, cmucal_mux_clkcmu_g2d_g2d_parents, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH, cmucal_mux_clkcmu_cpucl0_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH, cmucal_mux_clkcmu_cpucl1_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_G3D_SWITCH, cmucal_mux_clkcmu_g3d_switch_parents, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_DISPAUD_CPU, cmucal_mux_clkcmu_dispaud_cpu_parents, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MIF_SWITCH, cmucal_mux_clkcmu_mif_switch_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CPUCL0_DBG, cmucal_mux_clkcmu_cpucl0_dbg_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_USB_BUS, cmucal_mux_clkcmu_usb_bus_parents, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_USB_USB30DRD, cmucal_mux_clkcmu_usb_usb30drd_parents, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_USB_DPGTC, cmucal_mux_clkcmu_usb_dpgtc_parents, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_DISPAUD_AUD, cmucal_mux_clkcmu_dispaud_aud_parents, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_SELECT, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MFC_MFC, cmucal_mux_clkcmu_mfc_mfc_parents, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MFC_WFD, cmucal_mux_clkcmu_mfc_wfd_parents, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_HPM, cmucal_mux_clkcmu_hpm_parents, CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_UART, cmucal_mux_clkcmu_peri_uart_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_VIPX2_BUS, cmucal_mux_clkcmu_vipx2_bus_parents, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CIS_CLK3, cmucal_mux_clkcmu_cis_clk3_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CORE_GIC, cmucal_mux_clk_core_gic_parents, CLK_CON_MUX_MUX_CLK_CORE_GIC_SELECT, CLK_CON_MUX_MUX_CLK_CORE_GIC_BUSY, CLK_CON_MUX_MUX_CLK_CORE_GIC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CPUCL0_PLL, cmucal_mux_clk_cpucl0_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_CPUCL1_PLL, cmucal_mux_clk_cpucl1_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_CPU, cmucal_mux_clk_aud_cpu_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_UAIF0, cmucal_mux_clk_aud_uaif0_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_UAIF2, cmucal_mux_clk_aud_uaif2_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_UAIF1, cmucal_mux_clk_aud_uaif1_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_CPU_HCH, cmucal_mux_clk_aud_cpu_hch_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_FM, cmucal_mux_clk_aud_fm_parents, CLK_CON_MUX_MUX_CLK_AUD_FM_SELECT, CLK_CON_MUX_MUX_CLK_AUD_FM_BUSY, CLK_CON_MUX_MUX_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_AUD_BUS, cmucal_mux_clk_aud_bus_parents, CLK_CON_MUX_MUX_CLK_AUD_BUS_SELECT, CLK_CON_MUX_MUX_CLK_AUD_BUS_BUSY, CLK_CON_MUX_MUX_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_G3D_BUSD, cmucal_mux_clk_g3d_busd_parents, CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_MIF_DDRPHY_CLK2X, cmucal_mux_clk_mif_ddrphy_clk2x_parents, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_SELECT, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_BUSY, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_MIF_CMUREF, cmucal_mux_mif_cmuref_parents, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_MIF1_DDRPHY_CLK2X, cmucal_mux_clk_mif1_ddrphy_clk2x_parents, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_SELECT, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_BUSY, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_MIF1_CMUREF, cmucal_mux_mif1_cmuref_parents, CLK_CON_MUX_MUX_MIF1_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF1_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF1_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_SHUB_USI00, cmucal_mux_clk_shub_usi00_parents, CLK_CON_MUX_MUX_CLK_SHUB_USI00_SELECT, CLK_CON_MUX_MUX_CLK_SHUB_USI00_BUSY, CLK_CON_MUX_MUX_CLK_SHUB_USI00_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_SHUB_USI01, cmucal_mux_clk_shub_usi01_parents, CLK_CON_MUX_MUX_CLK_SHUB_USI01_SELECT, CLK_CON_MUX_MUX_CLK_SHUB_USI01_BUSY, CLK_CON_MUX_MUX_CLK_SHUB_USI01_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLK_SHUB_I2C, cmucal_mux_clk_shub_i2c_parents, CLK_CON_MUX_MUX_CLK_SHUB_I2C_SELECT, CLK_CON_MUX_MUX_CLK_SHUB_I2C_BUSY, CLK_CON_MUX_MUX_CLK_SHUB_I2C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX2(APM_CMU_APM_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(CAM_CMU_CAM_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(CMGP_CMU_CMGP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(CMU_CMU_TOP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(CORE_CMU_CORE_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(CPUCL0_CMU_CPUCL0_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(CPUCL1_CMU_CPUCL1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(DISPAUD_CMU_DISPAUD_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(FSYS_CMU_FSYS_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(G2D_CMU_G2D_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(G3D_CMU_G3D_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(ISP_CMU_ISP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(MFC_CMU_MFC_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(MIF_CMU_MIF_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(MIF1_CMU_MIF1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(PERI_CMU_PERI_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(SHUB_CMU_SHUB_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(USB_CMU_USB_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(VIPX1_CMU_VIPX1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX2(VIPX2_CMU_VIPX2_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), |
| CLK_MUX(MUX_CLKCMU_APM_BUS_USER, cmucal_mux_clkcmu_apm_bus_user_parents, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_DLL_USER, cmucal_mux_dll_user_parents, PLL_CON0_MUX_DLL_USER_MUX_SEL, PLL_CON0_MUX_DLL_USER_BUSY, PLL_CON2_MUX_DLL_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CAM_BUS_USER, cmucal_mux_clkcmu_cam_bus_user_parents, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CAM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CORE_BUS_USER, cmucal_mux_clkcmu_core_bus_user_parents, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CORE_CCI_USER, cmucal_mux_clkcmu_core_cci_user_parents, PLL_CON0_MUX_CLKCMU_CORE_CCI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_CCI_USER_BUSY, PLL_CON2_MUX_CLKCMU_CORE_CCI_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CORE_G3D_USER, cmucal_mux_clkcmu_core_g3d_user_parents, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_BUSY, PLL_CON2_MUX_CLKCMU_CORE_G3D_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH_USER, cmucal_mux_clkcmu_cpucl0_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_USER, cmucal_mux_clkcmu_cpucl0_dbg_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH_USER, cmucal_mux_clkcmu_cpucl1_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_DISPAUD_CPU_USER, cmucal_mux_clkcmu_dispaud_cpu_user_parents, PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER_BUSY, PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_DISPAUD_DISP_USER, cmucal_mux_clkcmu_dispaud_disp_user_parents, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER_BUSY, PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_DISPAUD_AUD_USER, cmucal_mux_clkcmu_dispaud_aud_user_parents, PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER_BUSY, PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_BUS_USER, cmucal_mux_clkcmu_fsys_bus_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_MMC_CARD_USER, cmucal_mux_clkcmu_fsys_mmc_card_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_MMC_EMBD_USER, cmucal_mux_clkcmu_fsys_mmc_embd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_FSYS_UFS_EMBD_USER, cmucal_mux_clkcmu_fsys_ufs_embd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_G2D_MSCL_USER, cmucal_mux_clkcmu_g2d_mscl_user_parents, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_BUSY, PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_G2D_G2D_USER, cmucal_mux_clkcmu_g2d_g2d_user_parents, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_G3D_SWITCH_USER, cmucal_mux_clkcmu_g3d_switch_user_parents, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_ISP_BUS_USER, cmucal_mux_clkcmu_isp_bus_user_parents, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_ISP_VRA_USER, cmucal_mux_clkcmu_isp_vra_user_parents, PLL_CON0_MUX_CLKCMU_ISP_VRA_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISP_VRA_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISP_VRA_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_ISP_GDC_USER, cmucal_mux_clkcmu_isp_gdc_user_parents, PLL_CON0_MUX_CLKCMU_ISP_GDC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISP_GDC_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISP_GDC_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MFC_WFD_USER, cmucal_mux_clkcmu_mfc_wfd_user_parents, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFC_WFD_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MFC_MFC_USER, cmucal_mux_clkcmu_mfc_mfc_user_parents, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFC_MFC_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MIF_BUSP_USER, cmucal_mux_clkcmu_mif_busp_user_parents, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_MIF1_BUSP_USER, cmucal_mux_clkcmu_mif1_busp_user_parents, PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER_BUSY, PLL_CON2_MUX_CLKCMU_MIF1_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_BUS_USER, cmucal_mux_clkcmu_peri_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_IP_USER, cmucal_mux_clkcmu_peri_ip_user_parents, PLL_CON0_MUX_CLKCMU_PERI_IP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_IP_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_IP_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_PERI_UART_USER, cmucal_mux_clkcmu_peri_uart_user_parents, PLL_CON0_MUX_CLKCMU_PERI_UART_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_UART_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERI_UART_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_SHUB_BUS_USER, cmucal_mux_clkcmu_shub_bus_user_parents, PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_SHUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_USB_BUS_USER, cmucal_mux_clkcmu_usb_bus_user_parents, PLL_CON0_MUX_CLKCMU_USB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_USB_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_USB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_USB_USB30DRD_USER, cmucal_mux_clkcmu_usb_usb30drd_user_parents, PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER_BUSY, PLL_CON2_MUX_CLKCMU_USB_USB30DRD_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_USB_DPGTC_USER, cmucal_mux_clkcmu_usb_dpgtc_user_parents, PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER_BUSY, PLL_CON2_MUX_CLKCMU_USB_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_VIPX1_BUS_USER, cmucal_mux_clkcmu_vipx1_bus_user_parents, PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_VIPX1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_MUX(MUX_CLKCMU_VIPX2_BUS_USER, cmucal_mux_clkcmu_vipx2_bus_user_parents, PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_VIPX2_BUS_USER_ENABLE_AUTOMATIC_CLKGATING), |
| }; |
| |
| /*====================The section of DIVs===================*/ |
| unsigned int cmucal_div_size = 98; |
| |
| |
| struct cmucal_div cmucal_div_list[] = { |
| CLK_DIV(DIV_CLK_APM_BUS, MUX_CLK_APM_BUS, CLK_CON_DIV_DIV_CLK_APM_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_BUS_BUSY, CLK_CON_DIV_DIV_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_SHUB_BUS, GATE_CLKCMU_SHUB_BUS, CLK_CON_DIV_CLKCMU_SHUB_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_SHUB_BUS_BUSY, CLK_CON_DIV_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CAM_BUSP, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_DIV_DIV_CLK_CAM_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CAM_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CAM_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CMGP_USI03, MUX_CLK_CMGP_USI03, CLK_CON_DIV_DIV_CLK_CMGP_USI03_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI03_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI03_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CMGP_USI00, MUX_CLK_CMGP_USI00, CLK_CON_DIV_DIV_CLK_CMGP_USI00_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI00_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI00_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CMGP_I2C, MUX_CLK_CMGP_I2C, CLK_CON_DIV_DIV_CLK_CMGP_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CMGP_USI01, MUX_CLK_CMGP_USI01, CLK_CON_DIV_DIV_CLK_CMGP_USI01_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI01_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI01_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CMGP_USI04, MUX_CLK_CMGP_USI04, CLK_CON_DIV_DIV_CLK_CMGP_USI04_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI04_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI04_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CMGP_USI02, MUX_CLK_CMGP_USI02, CLK_CON_DIV_DIV_CLK_CMGP_USI02_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI02_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI02_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CMGP_ADC, CLKCMU_CMGP_BUS, CLK_CON_DIV_DIV_CLK_CMGP_ADC_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_ADC_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_DISPAUD_DISP, GATE_CLKCMU_DISPAUD_DISP, CLK_CON_DIV_CLKCMU_DISPAUD_DISP_DIVRATIO, CLK_CON_DIV_CLKCMU_DISPAUD_DISP_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_FSYS_BUS, GATE_CLKCMU_FSYS_BUS, CLK_CON_DIV_CLKCMU_FSYS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_BUS_BUSY, CLK_CON_DIV_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_G2D_MSCL, GATE_CLKCMU_G2D_MSCL, CLK_CON_DIV_CLKCMU_G2D_MSCL_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_MSCL_BUSY, CLK_CON_DIV_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(AP2CP_SHARED0_PLL_CLK, GATE_CLKCMU_MODEM_SHARED0, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_DIVRATIO, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_BUSY, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_BUS, GATE_CLKCMU_PERI_BUS, CLK_CON_DIV_CLKCMU_PERI_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_IP, GATE_CLKCMU_PERI_IP, CLK_CON_DIV_CLKCMU_PERI_IP_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_IP_BUSY, CLK_CON_DIV_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_APM_BUS, GATE_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_FSYS_MMC_CARD, GATE_CLKCMU_FSYS_MMC_CARD, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CIS_CLK0, GATE_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CIS_CLK1, GATE_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CIS_CLK2, GATE_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_FSYS_MMC_EMBD, GATE_CLKCMU_FSYS_MMC_EMBD, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(AP2CP_SHARED1_PLL_CLK, GATE_CLKCMU_MODEM_SHARED1, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_DIVRATIO, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_BUSY, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CMU_CMUREF, MUX_CLK_CMU_CMUREF, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CORE_BUS, GATE_CLKCMU_CORE_BUS, CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED0_DIV3, PLL_SHARED0, CLK_CON_DIV_PLL_SHARED0_DIV3_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV3_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CPUCL0_DBG, GATE_CLKCMU_CPUCL0_DBG, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED0_DIV2, PLL_SHARED0, CLK_CON_DIV_PLL_SHARED0_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED0_DIV4, PLL_SHARED0_DIV2, CLK_CON_DIV_PLL_SHARED0_DIV4_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV4_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED1_DIV2, PLL_SHARED1, CLK_CON_DIV_PLL_SHARED1_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED1_DIV4, PLL_SHARED1_DIV2, CLK_CON_DIV_PLL_SHARED1_DIV4_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV4_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CORE_CCI, GATE_CLKCMU_CORE_CCI, CLK_CON_DIV_CLKCMU_CORE_CCI_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_CCI_BUSY, CLK_CON_DIV_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CORE_G3D, GATE_CLKCMU_CORE_G3D, CLK_CON_DIV_CLKCMU_CORE_G3D_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_G3D_BUSY, CLK_CON_DIV_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_MIF_BUSP, GATE_CLKCMU_MIF_BUSP, CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_SHARED1_DIV3, PLL_SHARED1, CLK_CON_DIV_PLL_SHARED1_DIV3_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV3_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_FSYS_UFS_EMBD, GATE_CLKCMU_FSYS_UFS_EMBD, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CAM_BUS, GATE_CLKCMU_CAM_BUS, CLK_CON_DIV_CLKCMU_CAM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CAM_BUS_BUSY, CLK_CON_DIV_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_VIPX1_BUS, GATE_CLKCMU_VIPX1_BUS, CLK_CON_DIV_CLKCMU_VIPX1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_VIPX1_BUS_BUSY, CLK_CON_DIV_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_ISP_BUS, GATE_CLKCMU_ISP_BUS, CLK_CON_DIV_CLKCMU_ISP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ISP_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_ISP_VRA, GATE_CLKCMU_ISP_VRA, CLK_CON_DIV_CLKCMU_ISP_VRA_DIVRATIO, CLK_CON_DIV_CLKCMU_ISP_VRA_BUSY, CLK_CON_DIV_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_ISP_GDC, GATE_CLKCMU_ISP_GDC, CLK_CON_DIV_CLKCMU_ISP_GDC_DIVRATIO, CLK_CON_DIV_CLKCMU_ISP_GDC_BUSY, CLK_CON_DIV_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_G2D_G2D, GATE_CLKCMU_G2D_G2D, CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CPUCL0_SWITCH, GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CPUCL1_SWITCH, GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_DISPAUD_CPU, GATE_CLKCMU_DISPAUD_CPU, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_DIVRATIO, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_USB_BUS, GATE_CLKCMU_USB_BUS, CLK_CON_DIV_CLKCMU_USB_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_USB_BUS_BUSY, CLK_CON_DIV_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_USB_USB30DRD, GATE_CLKCMU_USB_USB30DRD, CLK_CON_DIV_CLKCMU_USB_USB30DRD_DIVRATIO, CLK_CON_DIV_CLKCMU_USB_USB30DRD_BUSY, CLK_CON_DIV_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_USB_DPGTC, GATE_CLKCMU_USB_DPGTC, CLK_CON_DIV_CLKCMU_USB_DPGTC_DIVRATIO, CLK_CON_DIV_CLKCMU_USB_DPGTC_BUSY, CLK_CON_DIV_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_DISPAUD_AUD, GATE_CLKCMU_DISPAUD_AUD, CLK_CON_DIV_CLKCMU_DISPAUD_AUD_DIVRATIO, CLK_CON_DIV_CLKCMU_DISPAUD_AUD_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_MFC_MFC, GATE_CLKCMU_MFC_MFC, CLK_CON_DIV_CLKCMU_MFC_MFC_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_MFC_BUSY, CLK_CON_DIV_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_MFC_WFD, GATE_CLKCMU_MFC_WFD, CLK_CON_DIV_CLKCMU_MFC_WFD_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_WFD_BUSY, CLK_CON_DIV_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_HPM, GATE_CLKCMU_HPM, CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, CLK_CON_DIV_CLKCMU_HPM_BUSY, CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_PERI_UART, GATE_CLKCMU_PERI_UART, CLK_CON_DIV_CLKCMU_PERI_UART_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_UART_BUSY, CLK_CON_DIV_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_VIPX2_BUS, GATE_CLKCMU_VIPX2_BUS, CLK_CON_DIV_CLKCMU_VIPX2_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_VIPX2_BUS_BUSY, CLK_CON_DIV_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(CLKCMU_CIS_CLK3, GATE_CLKCMU_CIS_CLK3, CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(PLL_MMC_DIV2, PLL_MMC, CLK_CON_DIV_PLL_MMC_DIV2_DIVRATIO, CLK_CON_DIV_PLL_MMC_DIV2_BUSY, CLK_CON_DIV_PLL_MMC_DIV2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CORE_BUSP, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL0_PCLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL0_CMUREF, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CLUSTER0_ACLK, GATE_CLK_CLUSTER0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CLUSTER0_PCLKDBG, GATE_CLK_CLUSTER0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CLUSTER0_CNTCLK, GATE_CLK_CLUSTER0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL0_CPU, MUX_CLK_CPUCL0_PLL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_PCLK, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_CMUREF, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CLUSTER1_ACLK, GATE_CLK_CLUSTER1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_CPU, MUX_CLK_CPUCL1_PLL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CLUSTER1_CNTCLK, GATE_CLK_CLUSTER1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_CPUCL1_PCLKDBG, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_CPU, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_CPU_PCLKDBG, MUX_CLK_AUD_CPU_HCH, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_CPU_ACLK, MUX_CLK_AUD_CPU_HCH, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_UAIF0, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_AUDIF, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_UAIF2, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_UAIF1, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_DISPAUD_BUSP, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_DSIF, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_FM_SPDY, TICK_USB, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_FM, MUX_CLK_AUD_FM, CLK_CON_DIV_DIV_CLK_AUD_FM_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_AUD_BUS, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_G2D_BUSP, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_DIV_DIV_CLK_G2D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G2D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G2D_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_G3D_BUSP, MUX_CLK_G3D_BUSD, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_G3D_BUSD, MUX_CLK_G3D_BUSD, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_ISP_BUSP, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_DIV_DIV_CLK_ISP_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ISP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISP_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_MFC_BUSP, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_PERI_I2C, GATE_CLK_PERI_I2C, CLK_CON_DIV_DIV_CLK_PERI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERI_I2C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_PERI_SPI0, GATE_CLK_PERI_SPI0, CLK_CON_DIV_DIV_CLK_PERI_SPI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_SPI0_BUSY, CLK_CON_DIV_DIV_CLK_PERI_SPI0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_PERI_SPI1, GATE_CLK_PERI_SPI1, CLK_CON_DIV_DIV_CLK_PERI_SPI1_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_SPI1_BUSY, CLK_CON_DIV_DIV_CLK_PERI_SPI1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_PERI_USI_I2C, GATE_CLK_PERI_USI_I2C, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_PERI_USI_USI, GATE_CLK_PERI_USI_USI, CLK_CON_DIV_DIV_CLK_PERI_USI_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI_USI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_PERI_SPI2, GATE_CLK_PERI_SPI2, CLK_CON_DIV_DIV_CLK_PERI_SPI2_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_SPI2_BUSY, CLK_CON_DIV_DIV_CLK_PERI_SPI2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_SHUB_USI01, MUX_CLK_SHUB_USI01, CLK_CON_DIV_DIV_CLK_SHUB_USI01_DIVRATIO, CLK_CON_DIV_DIV_CLK_SHUB_USI01_BUSY, CLK_CON_DIV_DIV_CLK_SHUB_USI01_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_SHUB_I2C, MUX_CLK_SHUB_I2C, CLK_CON_DIV_DIV_CLK_SHUB_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_SHUB_I2C_BUSY, CLK_CON_DIV_DIV_CLK_SHUB_I2C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_SHUB_USI00, MUX_CLK_SHUB_USI00, CLK_CON_DIV_DIV_CLK_SHUB_USI00_DIVRATIO, CLK_CON_DIV_DIV_CLK_SHUB_USI00_BUSY, CLK_CON_DIV_DIV_CLK_SHUB_USI00_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_VIPX1_BUSP, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_DIV(DIV_CLK_VIPX2_BUSP, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| }; |
| |
| /*====================The section of GATEs===================*/ |
| unsigned int cmucal_gate_size = 647; |
| |
| |
| struct cmucal_gate cmucal_gate_list[] = { |
| CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_RSTnSYNC_CLK_APM_BUS_IPCLKPORT_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_SHUB_BUS, MUX_CLKCMU_SHUB_BUS, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLKCMU_CMGP_BUS, DIV_CLK_APM_BUS, CLK_CON_GAT_CLKCMU_CMGP_BUS_CG_VAL, CLK_CON_GAT_CLKCMU_CMGP_BUS_MANUAL, CLK_CON_GAT_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_RSTnSYNC_CLK_APM_GREBE_IPCLKPORT_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_APM_UID_RSTnSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK, OSCCLK_APM, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_APM_UID_RSTnSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_APM, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CAM_UID_RSTnSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK, OSCCLK_CAM, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_XIU_D_CAM, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_PCLK_PPMU_CAM, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_PPMU_CAM, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_SMMU_CAM, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_3AA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS2, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_CSIS3, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_DMA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_RDMA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CAM_UID_is6p10p0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK, DIV_CLK_CMGP_USI00, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK, DIV_CLK_CMGP_USI01, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK, DIV_CLK_CMGP_USI02, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK, DIV_CLK_CMGP_USI03, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK, DIV_CLK_CMGP_USI04, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI00, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI01, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI02, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI03, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI04, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_CMGP, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK, CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_G2D_MSCL, MUX_CLKCMU_G2D_MSCL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_DISPAUD_DISP, MUX_CLKCMU_DISPAUD_DISP, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_FSYS_MMC_EMBD, MUX_CLKCMU_FSYS_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_FSYS_BUS, MUX_CLKCMU_FSYS_BUS, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MODEM_SHARED0, PLL_SHARED0_DIV2, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_BUS, MUX_CLKCMU_PERI_BUS, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_IP, MUX_CLKCMU_PERI_IP, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_APM_BUS, MUX_CLKCMU_APM_BUS, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_FSYS_MMC_CARD, MUX_CLKCMU_FSYS_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CIS_CLK0, MUX_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CIS_CLK1, MUX_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CIS_CLK2, MUX_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MODEM_SHARED1, PLL_SHARED1_DIV2, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CORE_BUS, MUX_CLKCMU_CORE_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CPUCL0_DBG, MUX_CLKCMU_CPUCL0_DBG, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CORE_CCI, MUX_CLKCMU_CORE_CCI, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CORE_G3D, MUX_CLKCMU_CORE_G3D, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MIF_BUSP, MUX_CLKCMU_MIF_BUSP, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_FSYS_UFS_EMBD, MUX_CLKCMU_FSYS_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CAM_BUS, MUX_CLKCMU_CAM_BUS, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_VIPX1_BUS, MUX_CLKCMU_VIPX1_BUS, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_ISP_BUS, MUX_CLKCMU_ISP_BUS, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_ISP_VRA, MUX_CLKCMU_ISP_VRA, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_ISP_GDC, MUX_CLKCMU_ISP_GDC, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CPUCL0_SWITCH, MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CPUCL1_SWITCH, MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_G3D_SWITCH, MUX_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_DISPAUD_CPU, MUX_CLKCMU_DISPAUD_CPU, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLKCMU_MIF_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_USB_BUS, MUX_CLKCMU_USB_BUS, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_USB_USB30DRD, MUX_CLKCMU_USB_USB30DRD, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_USB_DPGTC, MUX_CLKCMU_USB_DPGTC, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_DISPAUD_AUD, MUX_CLKCMU_DISPAUD_AUD, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MFC_MFC, MUX_CLKCMU_MFC_MFC, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_MFC_WFD, MUX_CLKCMU_MFC_WFD, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_HPM, MUX_CLKCMU_HPM, CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_PERI_UART, MUX_CLKCMU_PERI_UART, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK, CLKCMU_OTP, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_VIPX2_BUS, MUX_CLKCMU_VIPX2_BUS, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLKCMU_CIS_CLK3, MUX_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM, MUX_CLK_CORE_GIC, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK, MUX_CLK_CORE_GIC, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_CCI_IPCLKPORT_CLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_G3D_IPCLKPORT_CLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_GIC_IPCLKPORT_CLK, MUX_CLK_CORE_GIC, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK, OSCCLK_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_i_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_i_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE, MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_DIT_IPCLKPORT_iClkL2A, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_AXI_US_A40_64to128_DIT_IPCLKPORT_aclk, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, OSCCLK_CPUCL0, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLK_CLUSTER0_CPU, DIV_CLK_CPUCL0_CPU, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk, MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK, OSCCLK_CPUCL1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER1_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM, DIV_CLK_CPUCL1_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL1_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLK_CLUSTER1_CPU, DIV_CLK_CPUCL1_CPU, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER1_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_AXI_US_32to128_IPCLKPORT_aclk, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK, MUX_CLK_AUD_CPU_HCH, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_DISPAUD_UID_RSTnSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK, OSCCLK_DISPAUD, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK, DIV_CLK_AUD_AUDIF, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY, DIV_CLK_AUD_FM, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK, DIV_CLK_AUD_DSIF, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, DIV_CLK_AUD_DSIF, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY, MUX_CLK_AUD_FM, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, MUX_CLK_AUD_UAIF0, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, MUX_CLK_AUD_UAIF1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, MUX_CLK_AUD_UAIF2, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF0, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_DISPAUD_UID_RSTnSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF2, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK, MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK, DIV_CLK_DISPAUD_BUSP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7, MUX_CLK_AUD_CPU_HCH, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK, MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_RSTnSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_FSYS_UID_RSTnSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK, OSCCLK_FSYS, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK, MUX_CLKCMU_FSYS_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_FSYS_MMC_CARD_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_FSYS_MMC_EMBD_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, MUX_CLKCMU_FSYS_UFS_EMBD_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_G2D_UID_RSTnSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK, OSCCLK_G2D, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_G2D_IPCLKPORT_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_G3D_UID_RSTnSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, OSCCLK_G3D, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_ISP_UID_RSTnSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK, OSCCLK_ISP, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_RSTnSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_RSTnSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_RSTnSYNC_CLK_ISP_GDC_IPCLKPORT_CLK, MUX_CLKCMU_ISP_GDC_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_RSTnSYNC_CLK_ISP_VRA_IPCLKPORT_CLK, MUX_CLKCMU_ISP_VRA_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_PCLK_PPMU_ISP1, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA, MUX_CLKCMU_ISP_VRA_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC, MUX_CLKCMU_ISP_GDC_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_PPMU_ISP0, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_PCLK_PPMU_ISP0, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_SMMU_ISP0, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_GDC, MUX_CLKCMU_ISP_GDC_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_ISP, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_VRA, MUX_CLKCMU_ISP_VRA_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC, MUX_CLKCMU_ISP_GDC_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA, MUX_CLKCMU_ISP_VRA_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_PPMU_ISP1, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_SMMU_ISP1, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_XIU_D_ISP, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_ACLK_MCSC, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_is6p10p0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_MFC_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_WFD_IPCLKPORT_CLK, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MFC_UID_RSTnSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK, OSCCLK_MFC, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC_WFD_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_RSTnSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, OSCCLK_MIF, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK, CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK, CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK, CLK_MIF1_BUSD, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_PERI_UID_RSTnSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK, OSCCLK_PERI, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_BUS_IPCLKPORT_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_UART_IPCLKPORT_CLK, MUX_CLKCMU_PERI_UART_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLK_PERI_I2C, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_I2C_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_I2C_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_I2C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLK_PERI_SPI0, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_SPI0_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_SPI0_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_SPI0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLK_PERI_SPI1, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_SPI1_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_SPI1_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_SPI1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLK_PERI_USI_USI, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_USI_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_USI_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_USI_USI_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLK_PERI_USI_I2C, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GATE_CLK_PERI_SPI2, MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GATE_CLK_PERI_SPI2_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_SPI2_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_SPI2_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_I2C_IPCLKPORT_CLK, DIV_CLK_PERI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK, DIV_CLK_PERI_SPI0, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK, DIV_CLK_PERI_SPI1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK, DIV_CLK_PERI_USI_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_RSTnSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK, DIV_CLK_PERI_SPI2, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK, MUX_CLKCMU_PERI_UART_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK, DIV_CLK_PERI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK, DIV_CLK_PERI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK, DIV_CLK_PERI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK, DIV_CLK_PERI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK, DIV_CLK_PERI_SPI0, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK, DIV_CLK_PERI_SPI1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK, DIV_CLK_PERI_SPI2, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_i_PCLK_S0, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_RSTnSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_RSTnSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK, DIV_CLK_SHUB_I2C, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_SHUB_UID_RSTnSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK, OSCCLK_RCO_SHUB__ALV, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_SHUB_UID_RSTnSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK, RTCCLK_SHUB__ALV, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_RSTnSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK, DIV_CLK_SHUB_USI00, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK, DIV_CLK_SHUB_I2C, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK, DIV_CLK_SHUB_USI00, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK, MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_bus_clk_early, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK, MUX_CLKCMU_USB_DPGTC_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_RSTnSYNC_CLK_USB_BUS_IPCLKPORT_CLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_USB_UID_RSTnSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK, OSCCLK_USB, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_aclk, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_ref_clk, MUX_CLKCMU_USB_USB30DRD_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK, MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_RSTnSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_RSTnSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_VIPX1_UID_RSTnSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK, OSCCLK_VIPX1, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK, DIV_CLK_VIPX1_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_RSTnSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(GOUT_BLK_VIPX2_UID_RSTnSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK, DIV_CLK_VIPX2_BUSP, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_GATE(CLK_BLK_VIPX2_UID_RSTnSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK, OSCCLK_VIPX2, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), |
| }; |
| |
| /*====================The section of FIXED RATEs===================*/ |
| unsigned int cmucal_fixed_rate_size = 41; |
| |
| |
| struct cmucal_clk_fixed_rate cmucal_fixed_rate_list[] = { |
| FIXEDRATE(OSCCLK_RCO_APM, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(CLK_DLL_DCO, 104005000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_APM, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_CAM, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_RCO_CMGP, 30000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_CMGP, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_CMU, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_CORE, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_CPUCL0, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_EMBEDDED_CPUCL0, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(CLK_CLUSTER0_DIV_ACLK, 100000000, EMPTY_CAL_ID), |
| FIXEDRATE(CLK_CLUSTER0_DIV_PCLKDBG, 100000000, EMPTY_CAL_ID), |
| FIXEDRATE(CLK_CLUSTER0_DIV_CNTCLK, 100000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_CPUCL1, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_EMBEDDED_CPUCL1, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_DISPAUD, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(IOCLK_AUDIOCDCLK0, 10000000, EMPTY_CAL_ID), |
| FIXEDRATE(IOCLK_AUDIOCDCLK2, 10000000, EMPTY_CAL_ID), |
| FIXEDRATE(IOCLK_AUDIOCDCLK1, 100000000, EMPTY_CAL_ID), |
| FIXEDRATE(CLK_DEBUG_DECON, 100000000, EMPTY_CAL_ID), |
| FIXEDRATE(TICK_USB, 60000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_FSYS, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_G2D, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_G3D, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_ISP, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_MFC, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(CLKCMU_MIF_SWITCH_CLKOUT, 1600000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_MIF, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_MIF1, 100000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_PERI, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_RCO_SHUB__ALV, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(RTCCLK_SHUB__ALV, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_USB, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(RTC_CLK_USB__ALV, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(O_USB20_PHY_CLOCK, 60000000, EMPTY_CAL_ID), |
| FIXEDRATE(O_USB30_PHY_RX0CLK_0, 250000000, EMPTY_CAL_ID), |
| FIXEDRATE(O_USB30_PHY_RX0CLK_1, 250000000, EMPTY_CAL_ID), |
| FIXEDRATE(O_USB30_PIPE_PCLK_0, 125000000, EMPTY_CAL_ID), |
| FIXEDRATE(O_USB30_PIPE_PCLK_1, 125000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_VIPX1, 26000000, EMPTY_CAL_ID), |
| FIXEDRATE(OSCCLK_VIPX2, 26000000, EMPTY_CAL_ID), |
| }; |
| |
| /*====================The section of FIXED FACTORs===================*/ |
| unsigned int cmucal_fixed_factor_size = 3; |
| |
| |
| struct cmucal_clk_fixed_factor cmucal_fixed_factor_list[] = { |
| FIXEDFACTOR(CLKCMU_OTP, OSCCLK_CMU, 7, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING), |
| FIXEDFACTOR(CLK_MIF_BUSD, MUX_CLK_MIF_DDRPHY_CLK2X, 7, CLK_CON_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING), |
| FIXEDFACTOR(CLK_MIF1_BUSD, MUX_CLK_MIF1_DDRPHY_CLK2X, 7, CLK_CON_DIV_CLK_MIF1_BUSD_ENABLE_AUTOMATIC_CLKGATING), |
| }; |