| #ifndef __ASM_CPU_SH4_DMA_H |
| #define __ASM_CPU_SH4_DMA_H |
| /* SH7751/7760/7780 DMA IRQ sources */ |
| #define DMAOR_INIT (DMAOR_DME) |
| #define CHCR_TS_MASK 0x18 |
| #include <cpu/dma-sh4a.h> |
| #else /* CONFIG_CPU_SH4A */ |
| #define DMAOR_INIT (0x8000|DMAOR_DME) |
| #define SH_DMAC_BASE0 0xffa00000 |
| #define SH_DMAC_BASE1 0xffa00070 |
| /* Definitions for the SuperH DMAC */ |
| #define TM_BURST 0x00000080 |
| #define CHCR_TS_MASK 0x70 |
| #define DMAOR_COD 0x00000008 |
| * The SuperH DMAC supports a number of transmit sizes, we list them here, |
| * with their respective values as they appear in the CHCR registers. |
| * Defaults to a 64-bit transfer size. |
| * The DMA count is defined as the number of bytes to transfer. |
| static unsigned int ts_shift[] __maybe_unused = { |
| #endif /* __ASM_CPU_SH4_DMA_H */ |