| * ARM architected timer |
| |
| ARM cores may have a per-core architected timer, which provides per-cpu timers, |
| or a memory mapped architected timer, which provides up to 8 frames with a |
| physical and optional virtual timer per frame. |
| |
| The per-core architected timer is attached to a GIC to deliver its |
| per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC |
| to deliver its interrupts via SPIs. |
| |
| ** CP15 Timer node properties: |
| |
| - compatible : Should at least contain one of |
| "arm,armv7-timer" |
| "arm,armv8-timer" |
| |
| - interrupts : Interrupt list for secure, non-secure, virtual and |
| hypervisor timers, in that order. |
| |
| - clock-frequency : The frequency of the main counter, in Hz. Should be present |
| only where necessary to work around broken firmware which does not configure |
| CNTFRQ on all CPUs to a uniform correct value. Use of this property is |
| strongly discouraged; fix your firmware unless absolutely impossible. |
| |
| - always-on : a boolean property. If present, the timer is powered through an |
| always-on power domain, therefore it never loses context. |
| |
| - fsl,erratum-a008585 : A boolean property. Indicates the presence of |
| QorIQ erratum A-008585, which says that reading the counter is |
| unreliable unless the same value is returned by back-to-back reads. |
| This also affects writes to the tval register, due to the implicit |
| counter read. |
| |
| - hisilicon,erratum-161010101 : A boolean property. Indicates the |
| presence of Hisilicon erratum 161010101, which says that reading the |
| counters is unreliable in some cases, and reads may return a value 32 |
| beyond the correct value. This also affects writes to the tval |
| registers, due to the implicit counter read. |
| |
| ** Optional properties: |
| |
| - arm,cpu-registers-not-fw-configured : Firmware does not initialize |
| any of the generic timer CPU registers, which contain their |
| architecturally-defined reset values. Only supported for 32-bit |
| systems which follow the ARMv7 architected reset values. |
| |
| - arm,no-tick-in-suspend : The main counter does not tick when the system is in |
| low-power system suspend on some SoCs. This behavior does not match the |
| Architecture Reference Manual's specification that the system counter "must |
| be implemented in an always-on power domain." |
| |
| |
| Example: |
| |
| timer { |
| compatible = "arm,cortex-a15-timer", |
| "arm,armv7-timer"; |
| interrupts = <1 13 0xf08>, |
| <1 14 0xf08>, |
| <1 11 0xf08>, |
| <1 10 0xf08>; |
| clock-frequency = <100000000>; |
| }; |
| |
| ** Memory mapped timer node properties: |
| |
| - compatible : Should at least contain "arm,armv7-timer-mem". |
| |
| - clock-frequency : The frequency of the main counter, in Hz. Should be present |
| only when firmware has not configured the MMIO CNTFRQ registers. |
| |
| - reg : The control frame base address. |
| |
| Note that #address-cells, #size-cells, and ranges shall be present to ensure |
| the CPU can address a frame's registers. |
| |
| A timer node has up to 8 frame sub-nodes, each with the following properties: |
| |
| - frame-number: 0 to 7. |
| |
| - interrupts : Interrupt list for physical and virtual timers in that order. |
| The virtual timer interrupt is optional. |
| |
| - reg : The first and second view base addresses in that order. The second view |
| base address is optional. |
| |
| - status : "disabled" indicates the frame is not available for use. Optional. |
| |
| Example: |
| |
| timer@f0000000 { |
| compatible = "arm,armv7-timer-mem"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| reg = <0xf0000000 0x1000>; |
| clock-frequency = <50000000>; |
| |
| frame@f0001000 { |
| frame-number = <0> |
| interrupts = <0 13 0x8>, |
| <0 14 0x8>; |
| reg = <0xf0001000 0x1000>, |
| <0xf0002000 0x1000>; |
| }; |
| |
| frame@f0003000 { |
| frame-number = <1> |
| interrupts = <0 15 0x8>; |
| reg = <0xf0003000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |