arch/arm/boot/dts/kirkwood.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "marvell,kirkwood";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,feroceon";
			clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
			clock-names = "cpu_clk", "ddrclk", "powersave";
		};
	};

	aliases {
	       gpio0 = &gpio0;
	       gpio1 = &gpio1;
	};
	intc: interrupt-controller {
		compatible = "marvell,orion-intc", "marvell,intc";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0xf1020204 0x04>,
		      <0xf1020214 0x04>;
	};

	ocp@f1000000 {
		compatible = "simple-bus";
		ranges = <0x00000000 0xf1000000 0x0100000
		          0xe0000000 0xe0000000 0x8100000 /* PCIE */
		          0xf4000000 0xf4000000 0x0000400
		          0xf5000000 0xf5000000 0x0000400>;
		#address-cells = <1>;
		#size-cells = <1>;

		core_clk: core-clocks@10030 {
			compatible = "marvell,kirkwood-core-clock";
			reg = <0x10030 0x4>;
	        	#clock-cells = <1>;
		};

		gpio0: gpio@10100 {
			compatible = "marvell,orion-gpio";
			#gpio-cells = <2>;
			gpio-controller;
			reg = <0x10100 0x40>;
			ngpios = <32>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <35>, <36>, <37>, <38>;
			clocks = <&gate_clk 7>;
		};

		gpio1: gpio@10140 {
			compatible = "marvell,orion-gpio";
			#gpio-cells = <2>;
			gpio-controller;
			reg = <0x10140 0x40>;
			ngpios = <18>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <39>, <40>, <41>;
			clocks = <&gate_clk 7>;
		};

		serial@12000 {
			compatible = "ns16550a";
			reg = <0x12000 0x100>;
			reg-shift = <2>;
			interrupts = <33>;
			clocks = <&gate_clk 7>;
			status = "disabled";
		};

		serial@12100 {
			compatible = "ns16550a";
			reg = <0x12100 0x100>;
			reg-shift = <2>;
			interrupts = <34>;
			clocks = <&gate_clk 7>;
			status = "disabled";
		};

		spi@10600 {
			compatible = "marvell,orion-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			interrupts = <23>;
			reg = <0x10600 0x28>;
			clocks = <&gate_clk 7>;
			status = "disabled";
		};

		gate_clk: clock-gating-control@2011c {
			compatible = "marvell,kirkwood-gating-clock";
			reg = <0x2011c 0x4>;
			clocks = <&core_clk 0>;
			#clock-cells = <1>;
		};

		wdt@20300 {
			compatible = "marvell,orion-wdt";
			reg = <0x20300 0x28>;
			clocks = <&gate_clk 7>;
			status = "okay";
		};

		xor@60800 {
			compatible = "marvell,orion-xor";
			reg = <0x60800 0x100
			       0x60A00 0x100>;
			status = "okay";
			clocks = <&gate_clk 8>;

			xor00 {
			      interrupts = <5>;
			      dmacap,memcpy;
			      dmacap,xor;
			};
			xor01 {
			      interrupts = <6>;
			      dmacap,memcpy;
			      dmacap,xor;
			      dmacap,memset;
			};
		};

		xor@60900 {
			compatible = "marvell,orion-xor";
			reg = <0x60900 0x100
			       0xd0B00 0x100>;
			status = "okay";
			clocks = <&gate_clk 16>;

			xor00 {
			      interrupts = <7>;
			      dmacap,memcpy;
			      dmacap,xor;
			};
			xor01 {
			      interrupts = <8>;
			      dmacap,memcpy;
			      dmacap,xor;
			      dmacap,memset;
			};
		};

		ehci@50000 {
			compatible = "marvell,orion-ehci";
			reg = <0x50000 0x1000>;
			interrupts = <19>;
			clocks = <&gate_clk 3>;
			status = "okay";
		};

		nand@3000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cle = <0>;
			ale = <1>;
			bank-width = <1>;
			compatible = "marvell,orion-nand";
			reg = <0xf4000000 0x400>;
			chip-delay = <25>;
			/* set partition map and/or chip-delay in board dts */
			clocks = <&gate_clk 7>;
			status = "disabled";
		};

		i2c@11000 {
			compatible = "marvell,mv64xxx-i2c";
			reg = <0x11000 0x20>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <29>;
			clock-frequency = <100000>;
			clocks = <&gate_clk 7>;
			status = "disabled";
		};

		crypto@30000 {
			compatible = "marvell,orion-crypto";
			reg = <0x30000 0x10000>,
			      <0xf5000000 0x800>;
			reg-names = "regs", "sram";
			interrupts = <22>;
			clocks = <&gate_clk 17>;
			status = "okay";
		};
	};
};