| #ifndef __ASM_BARRIER_H |
| #define __ASM_BARRIER_H |
| |
| #ifndef __ASSEMBLY__ |
| |
| #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); |
| |
| #if __LINUX_ARM_ARCH__ >= 7 || \ |
| (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K)) |
| #define sev() __asm__ __volatile__ ("sev" : : : "memory") |
| #define wfe() __asm__ __volatile__ ("wfe" : : : "memory") |
| #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") |
| #endif |
| |
| #if __LINUX_ARM_ARCH__ >= 7 |
| #define isb() __asm__ __volatile__ ("isb" : : : "memory") |
| #define dsb() __asm__ __volatile__ ("dsb" : : : "memory") |
| #define dmb() __asm__ __volatile__ ("dmb" : : : "memory") |
| #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 |
| #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ |
| : : "r" (0) : "memory") |
| #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ |
| : : "r" (0) : "memory") |
| #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ |
| : : "r" (0) : "memory") |
| #elif defined(CONFIG_CPU_FA526) |
| #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ |
| : : "r" (0) : "memory") |
| #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ |
| : : "r" (0) : "memory") |
| #define dmb() __asm__ __volatile__ ("" : : : "memory") |
| #else |
| #define isb() __asm__ __volatile__ ("" : : : "memory") |
| #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ |
| : : "r" (0) : "memory") |
| #define dmb() __asm__ __volatile__ ("" : : : "memory") |
| #endif |
| |
| #ifdef CONFIG_ARCH_HAS_BARRIERS |
| #include <mach/barriers.h> |
| #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) |
| #include <asm/outercache.h> |
| #define mb() do { dsb(); outer_sync(); } while (0) |
| #define rmb() dsb() |
| #define wmb() mb() |
| #else |
| #include <asm/memory.h> |
| #define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) |
| #define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) |
| #define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) |
| #endif |
| |
| #ifndef CONFIG_SMP |
| #define smp_mb() barrier() |
| #define smp_rmb() barrier() |
| #define smp_wmb() barrier() |
| #else |
| #define smp_mb() dmb() |
| #define smp_rmb() dmb() |
| #define smp_wmb() dmb() |
| #endif |
| |
| #define read_barrier_depends() do { } while(0) |
| #define smp_read_barrier_depends() do { } while(0) |
| |
| #define set_mb(var, value) do { var = value; smp_mb(); } while (0) |
| |
| #endif /* !__ASSEMBLY__ */ |
| #endif /* __ASM_BARRIER_H */ |