drivers/mmc/host/sdhci.h - LeafOS-Devices/android_kernel_samsung_gta4xl - Gitiles

 /*
  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
  *
  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or (at
  * your option) any later version.
  */

 #include <linux/scatterlist.h>
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <linux/io.h>

 /*
  * Controller registers
  */

 #define SDHCI_DMA_ADDRESS	0x00

 #define SDHCI_BLOCK_SIZE	0x04
 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))

 #define SDHCI_BLOCK_COUNT	0x06

 #define SDHCI_ARGUMENT		0x08

 #define SDHCI_TRANSFER_MODE	0x0C
 #define  SDHCI_TRNS_DMA		0x01
 #define  SDHCI_TRNS_BLK_CNT_EN	0x02
 #define  SDHCI_TRNS_ACMD12	0x04
 #define  SDHCI_TRNS_READ	0x10
 #define  SDHCI_TRNS_MULTI	0x20

 #define SDHCI_COMMAND		0x0E
 #define  SDHCI_CMD_RESP_MASK	0x03
 #define  SDHCI_CMD_CRC		0x08
 #define  SDHCI_CMD_INDEX	0x10
 #define  SDHCI_CMD_DATA		0x20

 #define  SDHCI_CMD_RESP_NONE	0x00
 #define  SDHCI_CMD_RESP_LONG	0x01
 #define  SDHCI_CMD_RESP_SHORT	0x02
 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03

 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))

 #define SDHCI_RESPONSE		0x10

 #define SDHCI_BUFFER		0x20

 #define SDHCI_PRESENT_STATE	0x24
 #define  SDHCI_CMD_INHIBIT	0x00000001
 #define  SDHCI_DATA_INHIBIT	0x00000002
 #define  SDHCI_DOING_WRITE	0x00000100
 #define  SDHCI_DOING_READ	0x00000200
 #define  SDHCI_SPACE_AVAILABLE	0x00000400
 #define  SDHCI_DATA_AVAILABLE	0x00000800
 #define  SDHCI_CARD_PRESENT	0x00010000
 #define  SDHCI_WRITE_PROTECT	0x00080000

 #define SDHCI_HOST_CONTROL 	0x28
 #define  SDHCI_CTRL_LED		0x01
 #define  SDHCI_CTRL_4BITBUS	0x02
 #define  SDHCI_CTRL_HISPD	0x04
 #define  SDHCI_CTRL_DMA_MASK	0x18
 #define   SDHCI_CTRL_SDMA	0x00
 #define   SDHCI_CTRL_ADMA1	0x08
 #define   SDHCI_CTRL_ADMA32	0x10
 #define   SDHCI_CTRL_ADMA64	0x18

 #define SDHCI_POWER_CONTROL	0x29
 #define  SDHCI_POWER_ON		0x01
 #define  SDHCI_POWER_180	0x0A
 #define  SDHCI_POWER_300	0x0C
 #define  SDHCI_POWER_330	0x0E

 #define SDHCI_BLOCK_GAP_CONTROL	0x2A

 #define SDHCI_WAKE_UP_CONTROL	0x2B

 #define SDHCI_CLOCK_CONTROL	0x2C
 #define  SDHCI_DIVIDER_SHIFT	8
 #define  SDHCI_CLOCK_CARD_EN	0x0004
 #define  SDHCI_CLOCK_INT_STABLE	0x0002
 #define  SDHCI_CLOCK_INT_EN	0x0001

 #define SDHCI_TIMEOUT_CONTROL	0x2E

 #define SDHCI_SOFTWARE_RESET	0x2F
 #define  SDHCI_RESET_ALL	0x01
 #define  SDHCI_RESET_CMD	0x02
 #define  SDHCI_RESET_DATA	0x04

 #define SDHCI_INT_STATUS	0x30
 #define SDHCI_INT_ENABLE	0x34
 #define SDHCI_SIGNAL_ENABLE	0x38
 #define  SDHCI_INT_RESPONSE	0x00000001
 #define  SDHCI_INT_DATA_END	0x00000002
 #define  SDHCI_INT_DMA_END	0x00000008
 #define  SDHCI_INT_SPACE_AVAIL	0x00000010
 #define  SDHCI_INT_DATA_AVAIL	0x00000020
 #define  SDHCI_INT_CARD_INSERT	0x00000040
 #define  SDHCI_INT_CARD_REMOVE	0x00000080
 #define  SDHCI_INT_CARD_INT	0x00000100
 #define  SDHCI_INT_ERROR	0x00008000
 #define  SDHCI_INT_TIMEOUT	0x00010000
 #define  SDHCI_INT_CRC		0x00020000
 #define  SDHCI_INT_END_BIT	0x00040000
 #define  SDHCI_INT_INDEX	0x00080000
 #define  SDHCI_INT_DATA_TIMEOUT	0x00100000
 #define  SDHCI_INT_DATA_CRC	0x00200000
 #define  SDHCI_INT_DATA_END_BIT	0x00400000
 #define  SDHCI_INT_BUS_POWER	0x00800000
 #define  SDHCI_INT_ACMD12ERR	0x01000000
 #define  SDHCI_INT_ADMA_ERROR	0x02000000

 #define  SDHCI_INT_NORMAL_MASK	0x00007FFF
 #define  SDHCI_INT_ERROR_MASK	0xFFFF8000

 #define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 #define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 		SDHCI_INT_DATA_END_BIT | SDHCI_ADMA_ERROR)
 #define SDHCI_INT_ALL_MASK	((unsigned int)-1)

 #define SDHCI_ACMD12_ERR	0x3C

 /* 3E-3F reserved */

 #define SDHCI_CAPABILITIES	0x40
 #define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 #define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
 #define  SDHCI_CLOCK_BASE_MASK	0x00003F00
 #define  SDHCI_CLOCK_BASE_SHIFT	8
 #define  SDHCI_MAX_BLOCK_MASK	0x00030000
 #define  SDHCI_MAX_BLOCK_SHIFT  16
 #define  SDHCI_CAN_DO_ADMA2	0x00080000
 #define  SDHCI_CAN_DO_ADMA1	0x00100000
 #define  SDHCI_CAN_DO_HISPD	0x00200000
 #define  SDHCI_CAN_DO_DMA	0x00400000
 #define  SDHCI_CAN_VDD_330	0x01000000
 #define  SDHCI_CAN_VDD_300	0x02000000
 #define  SDHCI_CAN_VDD_180	0x04000000
 #define  SDHCI_CAN_64BIT	0x10000000

 /* 44-47 reserved for more caps */

 #define SDHCI_MAX_CURRENT	0x48

 /* 4C-4F reserved for more max current */

 #define SDHCI_SET_ACMD12_ERROR	0x50
 #define SDHCI_SET_INT_ERROR	0x52

 #define SDHCI_ADMA_ERROR	0x54

 /* 55-57 reserved */

 #define SDHCI_ADMA_ADDRESS	0x58

 /* 60-FB reserved */

 #define SDHCI_SLOT_INT_STATUS	0xFC

 #define SDHCI_HOST_VERSION	0xFE
 #define  SDHCI_VENDOR_VER_MASK	0xFF00
 #define  SDHCI_VENDOR_VER_SHIFT	8
 #define  SDHCI_SPEC_VER_MASK	0x00FF
 #define  SDHCI_SPEC_VER_SHIFT	0
 #define   SDHCI_SPEC_100	0
 #define   SDHCI_SPEC_200	1

 struct sdhci_ops;

 struct sdhci_host {
 	/* Data set by hardware interface driver */
 	const char		*hw_name;	/* Hardware bus name */

 	unsigned int		quirks;		/* Deviations from spec. */

 /* Controller doesn't honor resets unless we touch the clock register */
 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET			(1<<0)
 /* Controller has bad caps bits, but really supports DMA */
 #define SDHCI_QUIRK_FORCE_DMA				(1<<1)
 /* Controller doesn't like to be reset when there is no card inserted. */
 #define SDHCI_QUIRK_NO_CARD_NO_RESET			(1<<2)
 /* Controller doesn't like clearing the power reg before a change */
 #define SDHCI_QUIRK_SINGLE_POWER_WRITE			(1<<3)
 /* Controller has flaky internal state so reset it on each ios change */
 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS		(1<<4)
 /* Controller has an unusable DMA engine */
 #define SDHCI_QUIRK_BROKEN_DMA				(1<<5)
 /* Controller has an unusable ADMA engine */
 #define SDHCI_QUIRK_BROKEN_ADMA				(1<<6)
 /* Controller can only DMA from 32-bit aligned addresses */
 #define SDHCI_QUIRK_32BIT_DMA_ADDR			(1<<7)
 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
 #define SDHCI_QUIRK_32BIT_DMA_SIZE			(1<<8)
 /* Controller can only ADMA chunks that are a multiple of 32 bits */
 #define SDHCI_QUIRK_32BIT_ADMA_SIZE			(1<<9)
 /* Controller needs to be reset after each request to stay stable */
 #define SDHCI_QUIRK_RESET_AFTER_REQUEST			(1<<10)
 /* Controller needs voltage and power writes to happen separately */
 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER		(1<<11)
 /* Controller provides an incorrect timeout value for transfers */
 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL			(1<<12)
 /* Controller has an issue with buffer bits for small transfers */
 #define SDHCI_QUIRK_BROKEN_SMALL_PIO			(1<<13)
 /* Controller does not provide transfer-complete interrupt when not busy */
 #define SDHCI_QUIRK_NO_BUSY_IRQ				(1<<14)
 /* Controller has unreliable card detection */
 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION		(1<<15)
 /* Controller reports inverted write-protect state */
 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT		(1<<16)
 /* Controller has nonstandard clock management */
 #define SDHCI_QUIRK_NONSTANDARD_CLOCK			(1<<17)
 /* Controller does not like fast PIO transfers */
 #define SDHCI_QUIRK_PIO_NEEDS_DELAY			(1<<18)
 /* Controller losing signal/interrupt enable states after reset */
 #define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET		(1<<19)
 /* Controller has to be forced to use block size of 2048 bytes */
 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048			(1<<20)
 /* Controller cannot do multi-block transfers */
 #define SDHCI_QUIRK_NO_MULTIBLOCK			(1<<21)
 /* Controller can only handle 1-bit data transfers */
 #define SDHCI_QUIRK_FORCE_1_BIT_DATA			(1<<22)
 /* Controller needs 10ms delay between applying power and clock */
 #define SDHCI_QUIRK_DELAY_AFTER_POWER			(1<<23)

 	int			irq;		/* Device IRQ */
 	void __iomem *		ioaddr;		/* Mapped address */

 	const struct sdhci_ops	*ops;		/* Low level hw interface */

 	/* Internal data */
 	struct mmc_host		*mmc;		/* MMC structure */
 	u64			dma_mask;	/* custom DMA mask */

 #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
 	struct led_classdev	led;		/* LED control */
 	char   led_name[32];
 #endif

 	spinlock_t		lock;		/* Mutex */

 	int			flags;		/* Host attributes */
 #define SDHCI_USE_DMA		(1<<0)		/* Host is DMA capable */
 #define SDHCI_USE_ADMA		(1<<1)		/* Host is ADMA capable */
 #define SDHCI_REQ_USE_DMA	(1<<2)		/* Use DMA for this req. */
 #define SDHCI_DEVICE_DEAD	(1<<3)		/* Device unresponsive */

 	unsigned int		version;	/* SDHCI spec. version */

 	unsigned int		max_clk;	/* Max possible freq (MHz) */
 	unsigned int		timeout_clk;	/* Timeout freq (KHz) */

 	unsigned int		clock;		/* Current clock (MHz) */
 	u8			pwr;		/* Current voltage */

 	struct mmc_request	*mrq;		/* Current request */
 	struct mmc_command	*cmd;		/* Current command */
 	struct mmc_data		*data;		/* Current data request */
 	unsigned int		data_early:1;	/* Data finished before cmd */

 	struct sg_mapping_iter	sg_miter;	/* SG state for PIO */
 	unsigned int		blocks;		/* remaining PIO blocks */

 	int			sg_count;	/* Mapped sg entries */

 	u8			*adma_desc;	/* ADMA descriptor table */
 	u8			*align_buffer;	/* Bounce buffer */

 	dma_addr_t		adma_addr;	/* Mapped ADMA descr. table */
 	dma_addr_t		align_addr;	/* Mapped bounce buffer */

 	struct tasklet_struct	card_tasklet;	/* Tasklet structures */
 	struct tasklet_struct	finish_tasklet;

 	struct timer_list	timer;		/* Timer for timeouts */

 	unsigned long		private[0] ____cacheline_aligned;
 };


 struct sdhci_ops {
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 	u32		(*readl)(struct sdhci_host *host, int reg);
 	u16		(*readw)(struct sdhci_host *host, int reg);
 	u8		(*readb)(struct sdhci_host *host, int reg);
 	void		(*writel)(struct sdhci_host *host, u32 val, int reg);
 	void		(*writew)(struct sdhci_host *host, u16 val, int reg);
 	void		(*writeb)(struct sdhci_host *host, u8 val, int reg);
 #endif

 	void	(*set_clock)(struct sdhci_host *host, unsigned int clock);

 	int		(*enable_dma)(struct sdhci_host *host);
 	unsigned int	(*get_max_clock)(struct sdhci_host *host);
 	unsigned int	(*get_min_clock)(struct sdhci_host *host);
 	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
 };

 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS

 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 {
 	if (unlikely(host->ops->writel))
 		host->ops->writel(host, val, reg);
 	else
 		writel(val, host->ioaddr + reg);
 }

 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 {
 	if (unlikely(host->ops->writew))
 		host->ops->writew(host, val, reg);
 	else
 		writew(val, host->ioaddr + reg);
 }

 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 {
 	if (unlikely(host->ops->writeb))
 		host->ops->writeb(host, val, reg);
 	else
 		writeb(val, host->ioaddr + reg);
 }

 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 {
 	if (unlikely(host->ops->readl))
 		return host->ops->readl(host, reg);
 	else
 		return readl(host->ioaddr + reg);
 }

 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 {
 	if (unlikely(host->ops->readw))
 		return host->ops->readw(host, reg);
 	else
 		return readw(host->ioaddr + reg);
 }

 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 {
 	if (unlikely(host->ops->readb))
 		return host->ops->readb(host, reg);
 	else
 		return readb(host->ioaddr + reg);
 }

 #else

 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 {
 	writel(val, host->ioaddr + reg);
 }

 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 {
 	writew(val, host->ioaddr + reg);
 }

 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 {
 	writeb(val, host->ioaddr + reg);
 }

 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 {
 	return readl(host->ioaddr + reg);
 }

 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 {
 	return readw(host->ioaddr + reg);
 }

 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 {
 	return readb(host->ioaddr + reg);
 }

 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */

 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
 	size_t priv_size);
 extern void sdhci_free_host(struct sdhci_host *host);

 static inline void *sdhci_priv(struct sdhci_host *host)
 {
 	return (void *)host->private;
 }

 extern int sdhci_add_host(struct sdhci_host *host);
 extern void sdhci_remove_host(struct sdhci_host *host, int dead);

 #ifdef CONFIG_PM
 extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
 extern int sdhci_resume_host(struct sdhci_host *host);
 #endif
	/*
	* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
	*
	* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License as published by
	* the Free Software Foundation; either version 2 of the License, or (at
	* your option) any later version.
	*/

	#include <linux/scatterlist.h>
	#include <linux/compiler.h>
	#include <linux/types.h>
	#include <linux/io.h>

	/*
	* Controller registers
	*/

	#define SDHCI_DMA_ADDRESS 0x00

	#define SDHCI_BLOCK_SIZE 0x04
	#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) \| (blksz & 0xFFF))

	#define SDHCI_BLOCK_COUNT 0x06

	#define SDHCI_ARGUMENT 0x08

	#define SDHCI_TRANSFER_MODE 0x0C
	#define SDHCI_TRNS_DMA 0x01
	#define SDHCI_TRNS_BLK_CNT_EN 0x02
	#define SDHCI_TRNS_ACMD12 0x04
	#define SDHCI_TRNS_READ 0x10
	#define SDHCI_TRNS_MULTI 0x20

	#define SDHCI_COMMAND 0x0E
	#define SDHCI_CMD_RESP_MASK 0x03
	#define SDHCI_CMD_CRC 0x08
	#define SDHCI_CMD_INDEX 0x10
	#define SDHCI_CMD_DATA 0x20

	#define SDHCI_CMD_RESP_NONE 0x00
	#define SDHCI_CMD_RESP_LONG 0x01
	#define SDHCI_CMD_RESP_SHORT 0x02
	#define SDHCI_CMD_RESP_SHORT_BUSY 0x03

	#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) \| (f & 0xff))

	#define SDHCI_RESPONSE 0x10

	#define SDHCI_BUFFER 0x20

	#define SDHCI_PRESENT_STATE 0x24
	#define SDHCI_CMD_INHIBIT 0x00000001
	#define SDHCI_DATA_INHIBIT 0x00000002
	#define SDHCI_DOING_WRITE 0x00000100
	#define SDHCI_DOING_READ 0x00000200
	#define SDHCI_SPACE_AVAILABLE 0x00000400
	#define SDHCI_DATA_AVAILABLE 0x00000800
	#define SDHCI_CARD_PRESENT 0x00010000
	#define SDHCI_WRITE_PROTECT 0x00080000

	#define SDHCI_HOST_CONTROL 0x28
	#define SDHCI_CTRL_LED 0x01
	#define SDHCI_CTRL_4BITBUS 0x02
	#define SDHCI_CTRL_HISPD 0x04
	#define SDHCI_CTRL_DMA_MASK 0x18
	#define SDHCI_CTRL_SDMA 0x00
	#define SDHCI_CTRL_ADMA1 0x08
	#define SDHCI_CTRL_ADMA32 0x10
	#define SDHCI_CTRL_ADMA64 0x18

	#define SDHCI_POWER_CONTROL 0x29
	#define SDHCI_POWER_ON 0x01
	#define SDHCI_POWER_180 0x0A
	#define SDHCI_POWER_300 0x0C
	#define SDHCI_POWER_330 0x0E

	#define SDHCI_BLOCK_GAP_CONTROL 0x2A

	#define SDHCI_WAKE_UP_CONTROL 0x2B

	#define SDHCI_CLOCK_CONTROL 0x2C
	#define SDHCI_DIVIDER_SHIFT 8
	#define SDHCI_CLOCK_CARD_EN 0x0004
	#define SDHCI_CLOCK_INT_STABLE 0x0002
	#define SDHCI_CLOCK_INT_EN 0x0001

	#define SDHCI_TIMEOUT_CONTROL 0x2E

	#define SDHCI_SOFTWARE_RESET 0x2F
	#define SDHCI_RESET_ALL 0x01
	#define SDHCI_RESET_CMD 0x02
	#define SDHCI_RESET_DATA 0x04

	#define SDHCI_INT_STATUS 0x30
	#define SDHCI_INT_ENABLE 0x34
	#define SDHCI_SIGNAL_ENABLE 0x38
	#define SDHCI_INT_RESPONSE 0x00000001
	#define SDHCI_INT_DATA_END 0x00000002
	#define SDHCI_INT_DMA_END 0x00000008
	#define SDHCI_INT_SPACE_AVAIL 0x00000010
	#define SDHCI_INT_DATA_AVAIL 0x00000020
	#define SDHCI_INT_CARD_INSERT 0x00000040
	#define SDHCI_INT_CARD_REMOVE 0x00000080
	#define SDHCI_INT_CARD_INT 0x00000100
	#define SDHCI_INT_ERROR 0x00008000
	#define SDHCI_INT_TIMEOUT 0x00010000
	#define SDHCI_INT_CRC 0x00020000
	#define SDHCI_INT_END_BIT 0x00040000
	#define SDHCI_INT_INDEX 0x00080000
	#define SDHCI_INT_DATA_TIMEOUT 0x00100000
	#define SDHCI_INT_DATA_CRC 0x00200000
	#define SDHCI_INT_DATA_END_BIT 0x00400000
	#define SDHCI_INT_BUS_POWER 0x00800000
	#define SDHCI_INT_ACMD12ERR 0x01000000
	#define SDHCI_INT_ADMA_ERROR 0x02000000

	#define SDHCI_INT_NORMAL_MASK 0x00007FFF
	#define SDHCI_INT_ERROR_MASK 0xFFFF8000

	#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE \| SDHCI_INT_TIMEOUT \| \
	SDHCI_INT_CRC \| SDHCI_INT_END_BIT \| SDHCI_INT_INDEX)
	#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END \| SDHCI_INT_DMA_END \| \
	SDHCI_INT_DATA_AVAIL \| SDHCI_INT_SPACE_AVAIL \| \
	SDHCI_INT_DATA_TIMEOUT \| SDHCI_INT_DATA_CRC \| \
	SDHCI_INT_DATA_END_BIT \| SDHCI_ADMA_ERROR)
	#define SDHCI_INT_ALL_MASK ((unsigned int)-1)

	#define SDHCI_ACMD12_ERR 0x3C

	/* 3E-3F reserved */

	#define SDHCI_CAPABILITIES 0x40
	#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
	#define SDHCI_TIMEOUT_CLK_SHIFT 0
	#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
	#define SDHCI_CLOCK_BASE_MASK 0x00003F00
	#define SDHCI_CLOCK_BASE_SHIFT 8
	#define SDHCI_MAX_BLOCK_MASK 0x00030000
	#define SDHCI_MAX_BLOCK_SHIFT 16
	#define SDHCI_CAN_DO_ADMA2 0x00080000
	#define SDHCI_CAN_DO_ADMA1 0x00100000
	#define SDHCI_CAN_DO_HISPD 0x00200000
	#define SDHCI_CAN_DO_DMA 0x00400000
	#define SDHCI_CAN_VDD_330 0x01000000
	#define SDHCI_CAN_VDD_300 0x02000000
	#define SDHCI_CAN_VDD_180 0x04000000
	#define SDHCI_CAN_64BIT 0x10000000

	/* 44-47 reserved for more caps */

	#define SDHCI_MAX_CURRENT 0x48

	/* 4C-4F reserved for more max current */

	#define SDHCI_SET_ACMD12_ERROR 0x50
	#define SDHCI_SET_INT_ERROR 0x52

	#define SDHCI_ADMA_ERROR 0x54

	/* 55-57 reserved */

	#define SDHCI_ADMA_ADDRESS 0x58

	/* 60-FB reserved */

	#define SDHCI_SLOT_INT_STATUS 0xFC

	#define SDHCI_HOST_VERSION 0xFE
	#define SDHCI_VENDOR_VER_MASK 0xFF00
	#define SDHCI_VENDOR_VER_SHIFT 8
	#define SDHCI_SPEC_VER_MASK 0x00FF
	#define SDHCI_SPEC_VER_SHIFT 0
	#define SDHCI_SPEC_100 0
	#define SDHCI_SPEC_200 1

	struct sdhci_ops;

	struct sdhci_host {
	/* Data set by hardware interface driver */
	const char hw_name; / Hardware bus name */

	unsigned int quirks; /* Deviations from spec. */

	/* Controller doesn't honor resets unless we touch the clock register */
	#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
	/* Controller has bad caps bits, but really supports DMA */
	#define SDHCI_QUIRK_FORCE_DMA (1<<1)
	/* Controller doesn't like to be reset when there is no card inserted. */
	#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
	/* Controller doesn't like clearing the power reg before a change */
	#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
	/* Controller has flaky internal state so reset it on each ios change */
	#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
	/* Controller has an unusable DMA engine */
	#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
	/* Controller has an unusable ADMA engine */
	#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
	/* Controller can only DMA from 32-bit aligned addresses */
	#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
	/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
	#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
	/* Controller can only ADMA chunks that are a multiple of 32 bits */
	#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
	/* Controller needs to be reset after each request to stay stable */
	#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
	/* Controller needs voltage and power writes to happen separately */
	#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
	/* Controller provides an incorrect timeout value for transfers */
	#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
	/* Controller has an issue with buffer bits for small transfers */
	#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
	/* Controller does not provide transfer-complete interrupt when not busy */
	#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
	/* Controller has unreliable card detection */
	#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
	/* Controller reports inverted write-protect state */
	#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
	/* Controller has nonstandard clock management */
	#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
	/* Controller does not like fast PIO transfers */
	#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
	/* Controller losing signal/interrupt enable states after reset */
	#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
	/* Controller has to be forced to use block size of 2048 bytes */
	#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
	/* Controller cannot do multi-block transfers */
	#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
	/* Controller can only handle 1-bit data transfers */
	#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
	/* Controller needs 10ms delay between applying power and clock */
	#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)

	int irq; /* Device IRQ */
	void __iomem * ioaddr; /* Mapped address */

	const struct sdhci_ops ops; / Low level hw interface */

	/* Internal data */
	struct mmc_host mmc; / MMC structure */
	u64 dma_mask; /* custom DMA mask */

	#if defined(CONFIG_LEDS_CLASS) \|\| defined(CONFIG_LEDS_CLASS_MODULE)
	struct led_classdev led; /* LED control */
	char led_name[32];
	#endif

	spinlock_t lock; /* Mutex */

	int flags; /* Host attributes */
	#define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */
	#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
	#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
	#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */

	unsigned int version; /* SDHCI spec. version */

	unsigned int max_clk; /* Max possible freq (MHz) */
	unsigned int timeout_clk; /* Timeout freq (KHz) */

	unsigned int clock; /* Current clock (MHz) */
	u8 pwr; /* Current voltage */

	struct mmc_request mrq; / Current request */
	struct mmc_command cmd; / Current command */
	struct mmc_data data; / Current data request */
	unsigned int data_early:1; /* Data finished before cmd */

	struct sg_mapping_iter sg_miter; /* SG state for PIO */
	unsigned int blocks; /* remaining PIO blocks */

	int sg_count; /* Mapped sg entries */

	u8 adma_desc; / ADMA descriptor table */
	u8 align_buffer; / Bounce buffer */

	dma_addr_t adma_addr; /* Mapped ADMA descr. table */
	dma_addr_t align_addr; /* Mapped bounce buffer */

	struct tasklet_struct card_tasklet; /* Tasklet structures */
	struct tasklet_struct finish_tasklet;

	struct timer_list timer; /* Timer for timeouts */

	unsigned long private[0] ____cacheline_aligned;
	};


	struct sdhci_ops {
	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	u32 (readl)(struct sdhci_host host, int reg);
	u16 (readw)(struct sdhci_host host, int reg);
	u8 (readb)(struct sdhci_host host, int reg);
	void (writel)(struct sdhci_host host, u32 val, int reg);
	void (writew)(struct sdhci_host host, u16 val, int reg);
	void (writeb)(struct sdhci_host host, u8 val, int reg);
	#endif

	void (set_clock)(struct sdhci_host host, unsigned int clock);

	int (enable_dma)(struct sdhci_host host);
	unsigned int (get_max_clock)(struct sdhci_host host);
	unsigned int (get_min_clock)(struct sdhci_host host);
	unsigned int (get_timeout_clock)(struct sdhci_host host);
	};

	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS

	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	{
	if (unlikely(host->ops->writel))
	host->ops->writel(host, val, reg);
	else
	writel(val, host->ioaddr + reg);
	}

	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	{
	if (unlikely(host->ops->writew))
	host->ops->writew(host, val, reg);
	else
	writew(val, host->ioaddr + reg);
	}

	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
	{
	if (unlikely(host->ops->writeb))
	host->ops->writeb(host, val, reg);
	else
	writeb(val, host->ioaddr + reg);
	}

	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
	{
	if (unlikely(host->ops->readl))
	return host->ops->readl(host, reg);
	else
	return readl(host->ioaddr + reg);
	}

	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
	{
	if (unlikely(host->ops->readw))
	return host->ops->readw(host, reg);
	else
	return readw(host->ioaddr + reg);
	}

	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
	{
	if (unlikely(host->ops->readb))
	return host->ops->readb(host, reg);
	else
	return readb(host->ioaddr + reg);
	}

	#else

	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	{
	writel(val, host->ioaddr + reg);
	}

	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	{
	writew(val, host->ioaddr + reg);
	}

	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
	{
	writeb(val, host->ioaddr + reg);
	}

	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
	{
	return readl(host->ioaddr + reg);
	}

	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
	{
	return readw(host->ioaddr + reg);
	}

	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
	{
	return readb(host->ioaddr + reg);
	}

	#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */

	extern struct sdhci_host sdhci_alloc_host(struct device dev,
	size_t priv_size);
	extern void sdhci_free_host(struct sdhci_host *host);

	static inline void sdhci_priv(struct sdhci_host host)
	{
	return (void *)host->private;
	}

	extern int sdhci_add_host(struct sdhci_host *host);
	extern void sdhci_remove_host(struct sdhci_host *host, int dead);

	#ifdef CONFIG_PM
	extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
	extern int sdhci_resume_host(struct sdhci_host *host);
	#endif