| #ifndef _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H |
| #define _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H |
| |
| #include <mach/stmp3xxx_regs.h> |
| |
| #define REGS_CLKCTRL_BASE (REGS_BASE + 0x00040000) |
| |
| #define HW_CLKCTRL_PLLCTRL0_ADDR (REGS_CLKCTRL_BASE + 0x00) |
| HW_REGISTER(HW_CLKCTRL_PLLCTRL0, REGS_CLKCTRL_BASE, 0x00) |
| #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 |
| #define HW_CLKCTRL_PLLCTRL1_ADDR (REGS_CLKCTRL_BASE + 0x10) |
| HW_REGISTER(HW_CLKCTRL_PLLCTRL1, REGS_CLKCTRL_BASE, 0x10) |
| |
| #define HW_CLKCTRL_CPU_ADDR (REGS_CLKCTRL_BASE + 0x20) |
| HW_REGISTER(HW_CLKCTRL_CPU, REGS_CLKCTRL_BASE, 0x20) |
| #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F |
| #define BF_CLKCTRL_CPU_DIV_CPU(v) \ |
| (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) |
| |
| #define HW_CLKCTRL_HBUS_ADDR (REGS_CLKCTRL_BASE + 0x30) |
| HW_REGISTER(HW_CLKCTRL_HBUS, REGS_CLKCTRL_BASE, 0x30) |
| #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0 /* for compatitibility */ |
| #define BM_CLKCTRL_HBUS_DIV 0x0000001F |
| #define BF_CLKCTRL_HBUS_DIV(v) \ |
| (((v) << 0) & BM_CLKCTRL_HBUS_DIV) |
| #define HW_CLKCTRL_XBUS_ADDR (REGS_CLKCTRL_BASE + 0x40) |
| HW_REGISTER(HW_CLKCTRL_XBUS, REGS_CLKCTRL_BASE, 0x40) |
| #define HW_CLKCTRL_XTAL_ADDR (REGS_CLKCTRL_BASE + 0x50) |
| HW_REGISTER(HW_CLKCTRL_XTAL, REGS_CLKCTRL_BASE, 0x50) |
| #define HW_CLKCTRL_PIX_ADDR (REGS_CLKCTRL_BASE + 0x60) |
| HW_REGISTER(HW_CLKCTRL_PIX, REGS_CLKCTRL_BASE, 0x60) |
| #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 |
| #define BM_CLKCTRL_PIX_BUSY 0x20000000 |
| #define BM_CLKCTRL_PIX_DIV 0x00007FFF |
| #define BP_CLKCTRL_PIX_DIV 0 |
| #define BF_CLKCTRL_PIX_DIV(v) \ |
| (((v) << BP_CLKCTRL_PIX_DIV) & BM_CLKCTRL_PIX_DIV) |
| #define HW_CLKCTRL_SSP_ADDR (REGS_CLKCTRL_BASE + 0x70) |
| HW_REGISTER(HW_CLKCTRL_SSP, REGS_CLKCTRL_BASE, 0x70) |
| #define HW_CLKCTRL_GPMI_ADDR (REGS_CLKCTRL_BASE + 0x80) |
| HW_REGISTER(HW_CLKCTRL_GPMI, REGS_CLKCTRL_BASE, 0x80) |
| #define HW_CLKCTRL_SPDIF_ADDR (REGS_CLKCTRL_BASE + 0x90) |
| HW_REGISTER(HW_CLKCTRL_SPDIF, REGS_CLKCTRL_BASE, 0x90) |
| #define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + 0xA0) |
| HW_REGISTER(HW_CLKCTRL_EMI, REGS_CLKCTRL_BASE, 0xA0) |
| #define HW_CLKCTRL_IR_ADDR (REGS_CLKCTRL_BASE + 0xB0) |
| HW_REGISTER(HW_CLKCTRL_IR, REGS_CLKCTRL_BASE, 0xB0) |
| #define HW_CLKCTRL_SAIF_ADDR (REGS_CLKCTRL_BASE + 0xC0) |
| HW_REGISTER(HW_CLKCTRL_SAIF, REGS_CLKCTRL_BASE, 0xC0) |
| #define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + 0xD0) |
| HW_REGISTER(HW_CLKCTRL_FRAC, REGS_CLKCTRL_BASE, 0xD0) |
| #define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 |
| #define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 |
| #define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000 |
| #define BP_CLKCTRL_FRAC_IOFRAC 24 |
| #define BF_CLKCTRL_FRAC_IOFRAC(v) \ |
| (((v) << BP_CLKCTRL_FRAC_IOFRAC) & BM_CLKCTRL_FRAC_IOFRAC) |
| #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 |
| #define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 |
| #define BP_CLKCTRL_FRAC_PIXFRAC 16 |
| #define BF_CLKCTRL_FRAC_PIXFRAC(v) \ |
| (((v) << BP_CLKCTRL_FRAC_PIXFRAC) & BM_CLKCTRL_FRAC_PIXFRAC) |
| #define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 |
| #define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 |
| #define BP_CLKCTRL_FRAC_EMIFRAC 8 |
| #define BF_CLKCTRL_FRAC_EMIFRAC(v) \ |
| (((v) << BP_CLKCTRL_FRAC_EMIFRAC) & BM_CLKCTRL_FRAC_EMIFRAC) |
| #define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080 |
| #define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F |
| #define BP_CLKCTRL_FRAC_CPUFRAC 0 |
| #define BF_CLKCTRL_FRAC_CPUFRAC(v) \ |
| (((v) << BP_CLKCTRL_FRAC_CPUFRAC) & BM_CLKCTRL_FRAC_CPUFRAC) |
| #define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + 0xE0) |
| HW_REGISTER(HW_CLKCTRL_CLKSEQ, REGS_CLKCTRL_BASE, 0xE0) |
| #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 |
| #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 |
| #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 |
| #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 |
| #define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 |
| #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 |
| #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 |
| HW_REGISTER_WO(HW_CLKCTRL_RESET, REGS_CLKCTRL_BASE, 0xF0) |
| #define BM_CLKCTRL_RESET_CHIP 0x00000002 |
| #define BM_CLKCTRL_RESET_DIG 0x00000001 |
| #endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */ |