| /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| */ |
| /* |
| * |
| * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation the rights to use, copy, modify, merge, publish, |
| * distribute, sub license, and/or sell copies of the Software, and to |
| * permit persons to whom the Software is furnished to do so, subject to |
| * the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial portions |
| * of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| * |
| */ |
| |
| #ifndef _I915_DRV_H_ |
| #define _I915_DRV_H_ |
| |
| /* General customization: |
| */ |
| |
| #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
| |
| #define DRIVER_NAME "i915" |
| #define DRIVER_DESC "Intel Graphics" |
| #define DRIVER_DATE "20060119" |
| |
| /* Interface history: |
| * |
| * 1.1: Original. |
| * 1.2: Add Power Management |
| * 1.3: Add vblank support |
| * 1.4: Fix cmdbuffer path, add heap destroy |
| * 1.5: Add vblank pipe configuration |
| * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
| * - Support vertical blank on secondary display pipe |
| */ |
| #define DRIVER_MAJOR 1 |
| #define DRIVER_MINOR 6 |
| #define DRIVER_PATCHLEVEL 0 |
| |
| typedef struct _drm_i915_ring_buffer { |
| int tail_mask; |
| unsigned long Start; |
| unsigned long End; |
| unsigned long Size; |
| u8 *virtual_start; |
| int head; |
| int tail; |
| int space; |
| drm_local_map_t map; |
| } drm_i915_ring_buffer_t; |
| |
| struct mem_block { |
| struct mem_block *next; |
| struct mem_block *prev; |
| int start; |
| int size; |
| struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
| }; |
| |
| typedef struct _drm_i915_vbl_swap { |
| struct list_head head; |
| drm_drawable_t drw_id; |
| unsigned int pipe; |
| unsigned int sequence; |
| } drm_i915_vbl_swap_t; |
| |
| typedef struct drm_i915_private { |
| drm_local_map_t *sarea; |
| drm_local_map_t *mmio_map; |
| |
| drm_i915_sarea_t *sarea_priv; |
| drm_i915_ring_buffer_t ring; |
| |
| drm_dma_handle_t *status_page_dmah; |
| void *hw_status_page; |
| dma_addr_t dma_status_page; |
| unsigned long counter; |
| unsigned int status_gfx_addr; |
| drm_local_map_t hws_map; |
| |
| unsigned int cpp; |
| int back_offset; |
| int front_offset; |
| int current_page; |
| int page_flipping; |
| int use_mi_batchbuffer_start; |
| |
| wait_queue_head_t irq_queue; |
| atomic_t irq_received; |
| atomic_t irq_emitted; |
| |
| int tex_lru_log_granularity; |
| int allow_batchbuffer; |
| struct mem_block *agp_heap; |
| unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
| int vblank_pipe; |
| |
| spinlock_t swaps_lock; |
| drm_i915_vbl_swap_t vbl_swaps; |
| unsigned int swaps_pending; |
| |
| /* Register state */ |
| u8 saveLBB; |
| u32 saveDSPACNTR; |
| u32 saveDSPBCNTR; |
| u32 savePIPEACONF; |
| u32 savePIPEBCONF; |
| u32 savePIPEASRC; |
| u32 savePIPEBSRC; |
| u32 saveFPA0; |
| u32 saveFPA1; |
| u32 saveDPLL_A; |
| u32 saveDPLL_A_MD; |
| u32 saveHTOTAL_A; |
| u32 saveHBLANK_A; |
| u32 saveHSYNC_A; |
| u32 saveVTOTAL_A; |
| u32 saveVBLANK_A; |
| u32 saveVSYNC_A; |
| u32 saveBCLRPAT_A; |
| u32 saveDSPASTRIDE; |
| u32 saveDSPASIZE; |
| u32 saveDSPAPOS; |
| u32 saveDSPABASE; |
| u32 saveDSPASURF; |
| u32 saveDSPATILEOFF; |
| u32 savePFIT_PGM_RATIOS; |
| u32 saveBLC_PWM_CTL; |
| u32 saveBLC_PWM_CTL2; |
| u32 saveFPB0; |
| u32 saveFPB1; |
| u32 saveDPLL_B; |
| u32 saveDPLL_B_MD; |
| u32 saveHTOTAL_B; |
| u32 saveHBLANK_B; |
| u32 saveHSYNC_B; |
| u32 saveVTOTAL_B; |
| u32 saveVBLANK_B; |
| u32 saveVSYNC_B; |
| u32 saveBCLRPAT_B; |
| u32 saveDSPBSTRIDE; |
| u32 saveDSPBSIZE; |
| u32 saveDSPBPOS; |
| u32 saveDSPBBASE; |
| u32 saveDSPBSURF; |
| u32 saveDSPBTILEOFF; |
| u32 saveVCLK_DIVISOR_VGA0; |
| u32 saveVCLK_DIVISOR_VGA1; |
| u32 saveVCLK_POST_DIV; |
| u32 saveVGACNTRL; |
| u32 saveADPA; |
| u32 saveLVDS; |
| u32 saveLVDSPP_ON; |
| u32 saveLVDSPP_OFF; |
| u32 saveDVOA; |
| u32 saveDVOB; |
| u32 saveDVOC; |
| u32 savePP_ON; |
| u32 savePP_OFF; |
| u32 savePP_CONTROL; |
| u32 savePP_CYCLE; |
| u32 savePFIT_CONTROL; |
| u32 save_palette_a[256]; |
| u32 save_palette_b[256]; |
| u32 saveFBC_CFB_BASE; |
| u32 saveFBC_LL_BASE; |
| u32 saveFBC_CONTROL; |
| u32 saveFBC_CONTROL2; |
| u32 saveSWF0[16]; |
| u32 saveSWF1[16]; |
| u32 saveSWF2[3]; |
| u8 saveMSR; |
| u8 saveSR[8]; |
| u8 saveGR[24]; |
| u8 saveAR_INDEX; |
| u8 saveAR[20]; |
| u8 saveDACMASK; |
| u8 saveDACDATA[256*3]; /* 256 3-byte colors */ |
| u8 saveCR[36]; |
| } drm_i915_private_t; |
| |
| extern struct drm_ioctl_desc i915_ioctls[]; |
| extern int i915_max_ioctl; |
| |
| /* i915_dma.c */ |
| extern void i915_kernel_lost_context(struct drm_device * dev); |
| extern int i915_driver_load(struct drm_device *, unsigned long flags); |
| extern int i915_driver_unload(struct drm_device *); |
| extern void i915_driver_lastclose(struct drm_device * dev); |
| extern void i915_driver_preclose(struct drm_device *dev, |
| struct drm_file *file_priv); |
| extern int i915_driver_device_is_agp(struct drm_device * dev); |
| extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
| unsigned long arg); |
| |
| /* i915_irq.c */ |
| extern int i915_irq_emit(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| extern int i915_irq_wait(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| |
| extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence); |
| extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence); |
| extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); |
| extern void i915_driver_irq_preinstall(struct drm_device * dev); |
| extern void i915_driver_irq_postinstall(struct drm_device * dev); |
| extern void i915_driver_irq_uninstall(struct drm_device * dev); |
| extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| extern int i915_vblank_swap(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| |
| /* i915_mem.c */ |
| extern int i915_mem_alloc(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| extern int i915_mem_free(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| extern int i915_mem_init_heap(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| extern void i915_mem_takedown(struct mem_block **heap); |
| extern void i915_mem_release(struct drm_device * dev, |
| struct drm_file *file_priv, struct mem_block *heap); |
| |
| #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) |
| #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) |
| #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) |
| #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) |
| |
| #define I915_VERBOSE 0 |
| |
| #define RING_LOCALS unsigned int outring, ringmask, outcount; \ |
| volatile char *virt; |
| |
| #define BEGIN_LP_RING(n) do { \ |
| if (I915_VERBOSE) \ |
| DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ |
| if (dev_priv->ring.space < (n)*4) \ |
| i915_wait_ring(dev, (n)*4, __FUNCTION__); \ |
| outcount = 0; \ |
| outring = dev_priv->ring.tail; \ |
| ringmask = dev_priv->ring.tail_mask; \ |
| virt = dev_priv->ring.virtual_start; \ |
| } while (0) |
| |
| #define OUT_RING(n) do { \ |
| if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ |
| *(volatile unsigned int *)(virt + outring) = (n); \ |
| outcount++; \ |
| outring += 4; \ |
| outring &= ringmask; \ |
| } while (0) |
| |
| #define ADVANCE_LP_RING() do { \ |
| if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ |
| dev_priv->ring.tail = outring; \ |
| dev_priv->ring.space -= outcount * 4; \ |
| I915_WRITE(LP_RING + RING_TAIL, outring); \ |
| } while(0) |
| |
| extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); |
| |
| /* Extended config space */ |
| #define LBB 0xf4 |
| |
| /* VGA stuff */ |
| |
| #define VGA_ST01_MDA 0x3ba |
| #define VGA_ST01_CGA 0x3da |
| |
| #define VGA_MSR_WRITE 0x3c2 |
| #define VGA_MSR_READ 0x3cc |
| #define VGA_MSR_MEM_EN (1<<1) |
| #define VGA_MSR_CGA_MODE (1<<0) |
| |
| #define VGA_SR_INDEX 0x3c4 |
| #define VGA_SR_DATA 0x3c5 |
| |
| #define VGA_AR_INDEX 0x3c0 |
| #define VGA_AR_VID_EN (1<<5) |
| #define VGA_AR_DATA_WRITE 0x3c0 |
| #define VGA_AR_DATA_READ 0x3c1 |
| |
| #define VGA_GR_INDEX 0x3ce |
| #define VGA_GR_DATA 0x3cf |
| /* GR05 */ |
| #define VGA_GR_MEM_READ_MODE_SHIFT 3 |
| #define VGA_GR_MEM_READ_MODE_PLANE 1 |
| /* GR06 */ |
| #define VGA_GR_MEM_MODE_MASK 0xc |
| #define VGA_GR_MEM_MODE_SHIFT 2 |
| #define VGA_GR_MEM_A0000_AFFFF 0 |
| #define VGA_GR_MEM_A0000_BFFFF 1 |
| #define VGA_GR_MEM_B0000_B7FFF 2 |
| #define VGA_GR_MEM_B0000_BFFFF 3 |
| |
| #define VGA_DACMASK 0x3c6 |
| #define VGA_DACRX 0x3c7 |
| #define VGA_DACWX 0x3c8 |
| #define VGA_DACDATA 0x3c9 |
| |
| #define VGA_CR_INDEX_MDA 0x3b4 |
| #define VGA_CR_DATA_MDA 0x3b5 |
| #define VGA_CR_INDEX_CGA 0x3d4 |
| #define VGA_CR_DATA_CGA 0x3d5 |
| |
| #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) |
| #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) |
| #define CMD_REPORT_HEAD (7<<23) |
| #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) |
| #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) |
| |
| #define INST_PARSER_CLIENT 0x00000000 |
| #define INST_OP_FLUSH 0x02000000 |
| #define INST_FLUSH_MAP_CACHE 0x00000001 |
| |
| #define BB1_START_ADDR_MASK (~0x7) |
| #define BB1_PROTECTED (1<<0) |
| #define BB1_UNPROTECTED (0<<0) |
| #define BB2_END_ADDR_MASK (~0x7) |
| |
| /* Framebuffer compression */ |
| #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ |
| #define FBC_LL_BASE 0x03204 /* 4k page aligned */ |
| #define FBC_CONTROL 0x03208 |
| #define FBC_CTL_EN (1<<31) |
| #define FBC_CTL_PERIODIC (1<<30) |
| #define FBC_CTL_INTERVAL_SHIFT (16) |
| #define FBC_CTL_UNCOMPRESSIBLE (1<<14) |
| #define FBC_CTL_STRIDE_SHIFT (5) |
| #define FBC_CTL_FENCENO (1<<0) |
| #define FBC_COMMAND 0x0320c |
| #define FBC_CMD_COMPRESS (1<<0) |
| #define FBC_STATUS 0x03210 |
| #define FBC_STAT_COMPRESSING (1<<31) |
| #define FBC_STAT_COMPRESSED (1<<30) |
| #define FBC_STAT_MODIFIED (1<<29) |
| #define FBC_STAT_CURRENT_LINE (1<<0) |
| #define FBC_CONTROL2 0x03214 |
| #define FBC_CTL_FENCE_DBL (0<<4) |
| #define FBC_CTL_IDLE_IMM (0<<2) |
| #define FBC_CTL_IDLE_FULL (1<<2) |
| #define FBC_CTL_IDLE_LINE (2<<2) |
| #define FBC_CTL_IDLE_DEBUG (3<<2) |
| #define FBC_CTL_CPU_FENCE (1<<1) |
| #define FBC_CTL_PLANEA (0<<0) |
| #define FBC_CTL_PLANEB (1<<0) |
| #define FBC_FENCE_OFF 0x0321b |
| |
| #define FBC_LL_SIZE (1536) |
| #define FBC_LL_PAD (32) |
| |
| /* Interrupt bits: |
| */ |
| #define USER_INT_FLAG (1<<1) |
| #define VSYNC_PIPEB_FLAG (1<<5) |
| #define VSYNC_PIPEA_FLAG (1<<7) |
| #define HWB_OOM_FLAG (1<<13) /* binner out of memory */ |
| |
| #define I915REG_HWSTAM 0x02098 |
| #define I915REG_INT_IDENTITY_R 0x020a4 |
| #define I915REG_INT_MASK_R 0x020a8 |
| #define I915REG_INT_ENABLE_R 0x020a0 |
| |
| #define I915REG_PIPEASTAT 0x70024 |
| #define I915REG_PIPEBSTAT 0x71024 |
| |
| #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
| #define I915_VBLANK_CLEAR (1UL<<1) |
| |
| #define SRX_INDEX 0x3c4 |
| #define SRX_DATA 0x3c5 |
| #define SR01 1 |
| #define SR01_SCREEN_OFF (1<<5) |
| |
| #define PPCR 0x61204 |
| #define PPCR_ON (1<<0) |
| |
| #define DVOB 0x61140 |
| #define DVOB_ON (1<<31) |
| #define DVOC 0x61160 |
| #define DVOC_ON (1<<31) |
| #define LVDS 0x61180 |
| #define LVDS_ON (1<<31) |
| |
| #define ADPA 0x61100 |
| #define ADPA_DPMS_MASK (~(3<<10)) |
| #define ADPA_DPMS_ON (0<<10) |
| #define ADPA_DPMS_SUSPEND (1<<10) |
| #define ADPA_DPMS_STANDBY (2<<10) |
| #define ADPA_DPMS_OFF (3<<10) |
| |
| #define NOPID 0x2094 |
| #define LP_RING 0x2030 |
| #define HP_RING 0x2040 |
| /* The binner has its own ring buffer: |
| */ |
| #define HWB_RING 0x2400 |
| |
| #define RING_TAIL 0x00 |
| #define TAIL_ADDR 0x001FFFF8 |
| #define RING_HEAD 0x04 |
| #define HEAD_WRAP_COUNT 0xFFE00000 |
| #define HEAD_WRAP_ONE 0x00200000 |
| #define HEAD_ADDR 0x001FFFFC |
| #define RING_START 0x08 |
| #define START_ADDR 0x0xFFFFF000 |
| #define RING_LEN 0x0C |
| #define RING_NR_PAGES 0x001FF000 |
| #define RING_REPORT_MASK 0x00000006 |
| #define RING_REPORT_64K 0x00000002 |
| #define RING_REPORT_128K 0x00000004 |
| #define RING_NO_REPORT 0x00000000 |
| #define RING_VALID_MASK 0x00000001 |
| #define RING_VALID 0x00000001 |
| #define RING_INVALID 0x00000000 |
| |
| /* Instruction parser error reg: |
| */ |
| #define IPEIR 0x2088 |
| |
| /* Scratch pad debug 0 reg: |
| */ |
| #define SCPD0 0x209c |
| |
| /* Error status reg: |
| */ |
| #define ESR 0x20b8 |
| |
| /* Secondary DMA fetch address debug reg: |
| */ |
| #define DMA_FADD_S 0x20d4 |
| |
| /* Cache mode 0 reg. |
| * - Manipulating render cache behaviour is central |
| * to the concept of zone rendering, tuning this reg can help avoid |
| * unnecessary render cache reads and even writes (for z/stencil) |
| * at beginning and end of scene. |
| * |
| * - To change a bit, write to this reg with a mask bit set and the |
| * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. |
| */ |
| #define Cache_Mode_0 0x2120 |
| #define CM0_MASK_SHIFT 16 |
| #define CM0_IZ_OPT_DISABLE (1<<6) |
| #define CM0_ZR_OPT_DISABLE (1<<5) |
| #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
| #define CM0_COLOR_EVICT_DISABLE (1<<3) |
| #define CM0_DEPTH_WRITE_DISABLE (1<<1) |
| #define CM0_RC_OP_FLUSH_DISABLE (1<<0) |
| |
| |
| /* Graphics flush control. A CPU write flushes the GWB of all writes. |
| * The data is discarded. |
| */ |
| #define GFX_FLSH_CNTL 0x2170 |
| |
| /* Binner control. Defines the location of the bin pointer list: |
| */ |
| #define BINCTL 0x2420 |
| #define BC_MASK (1 << 9) |
| |
| /* Binned scene info. |
| */ |
| #define BINSCENE 0x2428 |
| #define BS_OP_LOAD (1 << 8) |
| #define BS_MASK (1 << 22) |
| |
| /* Bin command parser debug reg: |
| */ |
| #define BCPD 0x2480 |
| |
| /* Bin memory control debug reg: |
| */ |
| #define BMCD 0x2484 |
| |
| /* Bin data cache debug reg: |
| */ |
| #define BDCD 0x2488 |
| |
| /* Binner pointer cache debug reg: |
| */ |
| #define BPCD 0x248c |
| |
| /* Binner scratch pad debug reg: |
| */ |
| #define BINSKPD 0x24f0 |
| |
| /* HWB scratch pad debug reg: |
| */ |
| #define HWBSKPD 0x24f4 |
| |
| /* Binner memory pool reg: |
| */ |
| #define BMP_BUFFER 0x2430 |
| #define BMP_PAGE_SIZE_4K (0 << 10) |
| #define BMP_BUFFER_SIZE_SHIFT 1 |
| #define BMP_ENABLE (1 << 0) |
| |
| /* Get/put memory from the binner memory pool: |
| */ |
| #define BMP_GET 0x2438 |
| #define BMP_PUT 0x2440 |
| #define BMP_OFFSET_SHIFT 5 |
| |
| /* 3D state packets: |
| */ |
| #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) |
| |
| #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
| #define SC_UPDATE_SCISSOR (0x1<<1) |
| #define SC_ENABLE_MASK (0x1<<0) |
| #define SC_ENABLE (0x1<<0) |
| |
| #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) |
| |
| #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
| #define SCI_YMIN_MASK (0xffff<<16) |
| #define SCI_XMIN_MASK (0xffff<<0) |
| #define SCI_YMAX_MASK (0xffff<<16) |
| #define SCI_XMAX_MASK (0xffff<<0) |
| |
| #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
| #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) |
| #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) |
| #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) |
| #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) |
| #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) |
| #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
| |
| #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) |
| |
| #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) |
| #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
| #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) |
| #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) |
| |
| #define MI_BATCH_BUFFER ((0x30<<23)|1) |
| #define MI_BATCH_BUFFER_START (0x31<<23) |
| #define MI_BATCH_BUFFER_END (0xA<<23) |
| #define MI_BATCH_NON_SECURE (1) |
| #define MI_BATCH_NON_SECURE_I965 (1<<8) |
| |
| #define MI_WAIT_FOR_EVENT ((0x3<<23)) |
| #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
| #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) |
| #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) |
| |
| #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) |
| |
| #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) |
| #define ASYNC_FLIP (1<<22) |
| #define DISPLAY_PLANE_A (0<<20) |
| #define DISPLAY_PLANE_B (1<<20) |
| |
| /* Display regs */ |
| #define DSPACNTR 0x70180 |
| #define DSPBCNTR 0x71180 |
| #define DISPPLANE_SEL_PIPE_MASK (1<<24) |
| |
| /* Define the region of interest for the binner: |
| */ |
| #define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4) |
| |
| #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) |
| |
| #define CMD_MI_FLUSH (0x04 << 23) |
| #define MI_NO_WRITE_FLUSH (1 << 2) |
| #define MI_READ_FLUSH (1 << 0) |
| #define MI_EXE_FLUSH (1 << 1) |
| #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ |
| #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ |
| |
| #define BREADCRUMB_BITS 31 |
| #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1) |
| |
| #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5]) |
| #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) |
| |
| #define BLC_PWM_CTL 0x61254 |
| #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
| |
| #define BLC_PWM_CTL2 0x61250 |
| /** |
| * This is the most significant 15 bits of the number of backlight cycles in a |
| * complete cycle of the modulated backlight control. |
| * |
| * The actual value is this field multiplied by two. |
| */ |
| #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) |
| #define BLM_LEGACY_MODE (1 << 16) |
| /** |
| * This is the number of cycles out of the backlight modulation cycle for which |
| * the backlight is on. |
| * |
| * This field must be no greater than the number of cycles in the complete |
| * backlight modulation cycle. |
| */ |
| #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) |
| #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
| |
| #define I915_GCFGC 0xf0 |
| #define I915_LOW_FREQUENCY_ENABLE (1 << 7) |
| #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) |
| #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) |
| #define I915_DISPLAY_CLOCK_MASK (7 << 4) |
| |
| #define I855_HPLLCC 0xc0 |
| #define I855_CLOCK_CONTROL_MASK (3 << 0) |
| #define I855_CLOCK_133_200 (0 << 0) |
| #define I855_CLOCK_100_200 (1 << 0) |
| #define I855_CLOCK_100_133 (2 << 0) |
| #define I855_CLOCK_166_250 (3 << 0) |
| |
| /* p317, 319 |
| */ |
| #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */ |
| #define VCLK2_VCO_N 0x600a |
| #define VCLK2_VCO_DIV_SEL 0x6012 |
| |
| #define VCLK_DIVISOR_VGA0 0x6000 |
| #define VCLK_DIVISOR_VGA1 0x6004 |
| #define VCLK_POST_DIV 0x6010 |
| /** Selects a post divisor of 4 instead of 2. */ |
| # define VGA1_PD_P2_DIV_4 (1 << 15) |
| /** Overrides the p2 post divisor field */ |
| # define VGA1_PD_P1_DIV_2 (1 << 13) |
| # define VGA1_PD_P1_SHIFT 8 |
| /** P1 value is 2 greater than this field */ |
| # define VGA1_PD_P1_MASK (0x1f << 8) |
| /** Selects a post divisor of 4 instead of 2. */ |
| # define VGA0_PD_P2_DIV_4 (1 << 7) |
| /** Overrides the p2 post divisor field */ |
| # define VGA0_PD_P1_DIV_2 (1 << 5) |
| # define VGA0_PD_P1_SHIFT 0 |
| /** P1 value is 2 greater than this field */ |
| # define VGA0_PD_P1_MASK (0x1f << 0) |
| |
| /* I830 CRTC registers */ |
| #define HTOTAL_A 0x60000 |
| #define HBLANK_A 0x60004 |
| #define HSYNC_A 0x60008 |
| #define VTOTAL_A 0x6000c |
| #define VBLANK_A 0x60010 |
| #define VSYNC_A 0x60014 |
| #define PIPEASRC 0x6001c |
| #define BCLRPAT_A 0x60020 |
| #define VSYNCSHIFT_A 0x60028 |
| |
| #define HTOTAL_B 0x61000 |
| #define HBLANK_B 0x61004 |
| #define HSYNC_B 0x61008 |
| #define VTOTAL_B 0x6100c |
| #define VBLANK_B 0x61010 |
| #define VSYNC_B 0x61014 |
| #define PIPEBSRC 0x6101c |
| #define BCLRPAT_B 0x61020 |
| #define VSYNCSHIFT_B 0x61028 |
| |
| #define PP_STATUS 0x61200 |
| # define PP_ON (1 << 31) |
| /** |
| * Indicates that all dependencies of the panel are on: |
| * |
| * - PLL enabled |
| * - pipe enabled |
| * - LVDS/DVOB/DVOC on |
| */ |
| # define PP_READY (1 << 30) |
| # define PP_SEQUENCE_NONE (0 << 28) |
| # define PP_SEQUENCE_ON (1 << 28) |
| # define PP_SEQUENCE_OFF (2 << 28) |
| # define PP_SEQUENCE_MASK 0x30000000 |
| #define PP_CONTROL 0x61204 |
| # define POWER_TARGET_ON (1 << 0) |
| |
| #define LVDSPP_ON 0x61208 |
| #define LVDSPP_OFF 0x6120c |
| #define PP_CYCLE 0x61210 |
| |
| #define PFIT_CONTROL 0x61230 |
| # define PFIT_ENABLE (1 << 31) |
| # define PFIT_PIPE_MASK (3 << 29) |
| # define PFIT_PIPE_SHIFT 29 |
| # define VERT_INTERP_DISABLE (0 << 10) |
| # define VERT_INTERP_BILINEAR (1 << 10) |
| # define VERT_INTERP_MASK (3 << 10) |
| # define VERT_AUTO_SCALE (1 << 9) |
| # define HORIZ_INTERP_DISABLE (0 << 6) |
| # define HORIZ_INTERP_BILINEAR (1 << 6) |
| # define HORIZ_INTERP_MASK (3 << 6) |
| # define HORIZ_AUTO_SCALE (1 << 5) |
| # define PANEL_8TO6_DITHER_ENABLE (1 << 3) |
| |
| #define PFIT_PGM_RATIOS 0x61234 |
| # define PFIT_VERT_SCALE_MASK 0xfff00000 |
| # define PFIT_HORIZ_SCALE_MASK 0x0000fff0 |
| |
| #define PFIT_AUTO_RATIOS 0x61238 |
| |
| |
| #define DPLL_A 0x06014 |
| #define DPLL_B 0x06018 |
| # define DPLL_VCO_ENABLE (1 << 31) |
| # define DPLL_DVO_HIGH_SPEED (1 << 30) |
| # define DPLL_SYNCLOCK_ENABLE (1 << 29) |
| # define DPLL_VGA_MODE_DIS (1 << 28) |
| # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
| # define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
| # define DPLL_MODE_MASK (3 << 26) |
| # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
| # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ |
| # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ |
| # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
| # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
| # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
| /** |
| * The i830 generation, in DAC/serial mode, defines p1 as two plus this |
| * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. |
| */ |
| # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
| /** |
| * The i830 generation, in LVDS mode, defines P1 as the bit number set within |
| * this field (only one bit may be set). |
| */ |
| # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 |
| # define DPLL_FPA01_P1_POST_DIV_SHIFT 16 |
| # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ |
| # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ |
| # define PLL_REF_INPUT_DREFCLK (0 << 13) |
| # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ |
| # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ |
| # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) |
| # define PLL_REF_INPUT_MASK (3 << 13) |
| # define PLL_LOAD_PULSE_PHASE_SHIFT 9 |
| /* |
| * Parallel to Serial Load Pulse phase selection. |
| * Selects the phase for the 10X DPLL clock for the PCIe |
| * digital display port. The range is 4 to 13; 10 or more |
| * is just a flip delay. The default is 6 |
| */ |
| # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) |
| # define DISPLAY_RATE_SELECT_FPA1 (1 << 8) |
| |
| /** |
| * SDVO multiplier for 945G/GM. Not used on 965. |
| * |
| * \sa DPLL_MD_UDI_MULTIPLIER_MASK |
| */ |
| # define SDVO_MULTIPLIER_MASK 0x000000ff |
| # define SDVO_MULTIPLIER_SHIFT_HIRES 4 |
| # define SDVO_MULTIPLIER_SHIFT_VGA 0 |
| |
| /** @defgroup DPLL_MD |
| * @{ |
| */ |
| /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ |
| #define DPLL_A_MD 0x0601c |
| /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ |
| #define DPLL_B_MD 0x06020 |
| /** |
| * UDI pixel divider, controlling how many pixels are stuffed into a packet. |
| * |
| * Value is pixels minus 1. Must be set to 1 pixel for SDVO. |
| */ |
| # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 |
| # define DPLL_MD_UDI_DIVIDER_SHIFT 24 |
| /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ |
| # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 |
| # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 |
| /** |
| * SDVO/UDI pixel multiplier. |
| * |
| * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus |
| * clock rate is 10 times the DPLL clock. At low resolution/refresh rate |
| * modes, the bus rate would be below the limits, so SDVO allows for stuffing |
| * dummy bytes in the datastream at an increased clock rate, with both sides of |
| * the link knowing how many bytes are fill. |
| * |
| * So, for a mode with a dotclock of 65Mhz, we would want to double the clock |
| * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be |
| * set to 130Mhz, and the SDVO multiplier set to 2x in this register and |
| * through an SDVO command. |
| * |
| * This register field has values of multiplication factor minus 1, with |
| * a maximum multiplier of 5 for SDVO. |
| */ |
| # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 |
| # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 |
| /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. |
| * This best be set to the default value (3) or the CRT won't work. No, |
| * I don't entirely understand what this does... |
| */ |
| # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
| # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
| /** @} */ |
| |
| #define DPLL_TEST 0x606c |
| # define DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
| # define DPLLB_TEST_SDVO_DIV_2 (1 << 22) |
| # define DPLLB_TEST_SDVO_DIV_4 (2 << 22) |
| # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) |
| # define DPLLB_TEST_N_BYPASS (1 << 19) |
| # define DPLLB_TEST_M_BYPASS (1 << 18) |
| # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) |
| # define DPLLA_TEST_N_BYPASS (1 << 3) |
| # define DPLLA_TEST_M_BYPASS (1 << 2) |
| # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) |
| |
| #define ADPA 0x61100 |
| #define ADPA_DAC_ENABLE (1<<31) |
| #define ADPA_DAC_DISABLE 0 |
| #define ADPA_PIPE_SELECT_MASK (1<<30) |
| #define ADPA_PIPE_A_SELECT 0 |
| #define ADPA_PIPE_B_SELECT (1<<30) |
| #define ADPA_USE_VGA_HVPOLARITY (1<<15) |
| #define ADPA_SETS_HVPOLARITY 0 |
| #define ADPA_VSYNC_CNTL_DISABLE (1<<11) |
| #define ADPA_VSYNC_CNTL_ENABLE 0 |
| #define ADPA_HSYNC_CNTL_DISABLE (1<<10) |
| #define ADPA_HSYNC_CNTL_ENABLE 0 |
| #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) |
| #define ADPA_VSYNC_ACTIVE_LOW 0 |
| #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) |
| #define ADPA_HSYNC_ACTIVE_LOW 0 |
| |
| #define FPA0 0x06040 |
| #define FPA1 0x06044 |
| #define FPB0 0x06048 |
| #define FPB1 0x0604c |
| # define FP_N_DIV_MASK 0x003f0000 |
| # define FP_N_DIV_SHIFT 16 |
| # define FP_M1_DIV_MASK 0x00003f00 |
| # define FP_M1_DIV_SHIFT 8 |
| # define FP_M2_DIV_MASK 0x0000003f |
| # define FP_M2_DIV_SHIFT 0 |
| |
| |
| #define PORT_HOTPLUG_EN 0x61110 |
| # define SDVOB_HOTPLUG_INT_EN (1 << 26) |
| # define SDVOC_HOTPLUG_INT_EN (1 << 25) |
| # define TV_HOTPLUG_INT_EN (1 << 18) |
| # define CRT_HOTPLUG_INT_EN (1 << 9) |
| # define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
| |
| #define PORT_HOTPLUG_STAT 0x61114 |
| # define CRT_HOTPLUG_INT_STATUS (1 << 11) |
| # define TV_HOTPLUG_INT_STATUS (1 << 10) |
| # define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
| # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
| # define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
| # define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
| # define SDVOC_HOTPLUG_INT_STATUS (1 << 7) |
| # define SDVOB_HOTPLUG_INT_STATUS (1 << 6) |
| |
| #define SDVOB 0x61140 |
| #define SDVOC 0x61160 |
| #define SDVO_ENABLE (1 << 31) |
| #define SDVO_PIPE_B_SELECT (1 << 30) |
| #define SDVO_STALL_SELECT (1 << 29) |
| #define SDVO_INTERRUPT_ENABLE (1 << 26) |
| /** |
| * 915G/GM SDVO pixel multiplier. |
| * |
| * Programmed value is multiplier - 1, up to 5x. |
| * |
| * \sa DPLL_MD_UDI_MULTIPLIER_MASK |
| */ |
| #define SDVO_PORT_MULTIPLY_MASK (7 << 23) |
| #define SDVO_PORT_MULTIPLY_SHIFT 23 |
| #define SDVO_PHASE_SELECT_MASK (15 << 19) |
| #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) |
| #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) |
| #define SDVOC_GANG_MODE (1 << 16) |
| #define SDVO_BORDER_ENABLE (1 << 7) |
| #define SDVOB_PCIE_CONCURRENCY (1 << 3) |
| #define SDVO_DETECTED (1 << 2) |
| /* Bits to be preserved when writing */ |
| #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) |
| #define SDVOC_PRESERVE_MASK (1 << 17) |
| |
| /** @defgroup LVDS |
| * @{ |
| */ |
| /** |
| * This register controls the LVDS output enable, pipe selection, and data |
| * format selection. |
| * |
| * All of the clock/data pairs are force powered down by power sequencing. |
| */ |
| #define LVDS 0x61180 |
| /** |
| * Enables the LVDS port. This bit must be set before DPLLs are enabled, as |
| * the DPLL semantics change when the LVDS is assigned to that pipe. |
| */ |
| # define LVDS_PORT_EN (1 << 31) |
| /** Selects pipe B for LVDS data. Must be set on pre-965. */ |
| # define LVDS_PIPEB_SELECT (1 << 30) |
| |
| /** |
| * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per |
| * pixel. |
| */ |
| # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) |
| # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) |
| # define LVDS_A0A2_CLKA_POWER_UP (3 << 8) |
| /** |
| * Controls the A3 data pair, which contains the additional LSBs for 24 bit |
| * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be |
| * on. |
| */ |
| # define LVDS_A3_POWER_MASK (3 << 6) |
| # define LVDS_A3_POWER_DOWN (0 << 6) |
| # define LVDS_A3_POWER_UP (3 << 6) |
| /** |
| * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP |
| * is set. |
| */ |
| # define LVDS_CLKB_POWER_MASK (3 << 4) |
| # define LVDS_CLKB_POWER_DOWN (0 << 4) |
| # define LVDS_CLKB_POWER_UP (3 << 4) |
| |
| /** |
| * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 |
| * setting for whether we are in dual-channel mode. The B3 pair will |
| * additionally only be powered up when LVDS_A3_POWER_UP is set. |
| */ |
| # define LVDS_B0B3_POWER_MASK (3 << 2) |
| # define LVDS_B0B3_POWER_DOWN (0 << 2) |
| # define LVDS_B0B3_POWER_UP (3 << 2) |
| |
| #define PIPEACONF 0x70008 |
| #define PIPEACONF_ENABLE (1<<31) |
| #define PIPEACONF_DISABLE 0 |
| #define PIPEACONF_DOUBLE_WIDE (1<<30) |
| #define I965_PIPECONF_ACTIVE (1<<30) |
| #define PIPEACONF_SINGLE_WIDE 0 |
| #define PIPEACONF_PIPE_UNLOCKED 0 |
| #define PIPEACONF_PIPE_LOCKED (1<<25) |
| #define PIPEACONF_PALETTE 0 |
| #define PIPEACONF_GAMMA (1<<24) |
| #define PIPECONF_FORCE_BORDER (1<<25) |
| #define PIPECONF_PROGRESSIVE (0 << 21) |
| #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) |
| #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) |
| |
| #define PIPEBCONF 0x71008 |
| #define PIPEBCONF_ENABLE (1<<31) |
| #define PIPEBCONF_DISABLE 0 |
| #define PIPEBCONF_DOUBLE_WIDE (1<<30) |
| #define PIPEBCONF_DISABLE 0 |
| #define PIPEBCONF_GAMMA (1<<24) |
| #define PIPEBCONF_PALETTE 0 |
| |
| #define PIPEBGCMAXRED 0x71010 |
| #define PIPEBGCMAXGREEN 0x71014 |
| #define PIPEBGCMAXBLUE 0x71018 |
| #define PIPEBSTAT 0x71024 |
| #define PIPEBFRAMEHIGH 0x71040 |
| #define PIPEBFRAMEPIXEL 0x71044 |
| |
| #define DSPACNTR 0x70180 |
| #define DSPBCNTR 0x71180 |
| #define DISPLAY_PLANE_ENABLE (1<<31) |
| #define DISPLAY_PLANE_DISABLE 0 |
| #define DISPPLANE_GAMMA_ENABLE (1<<30) |
| #define DISPPLANE_GAMMA_DISABLE 0 |
| #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) |
| #define DISPPLANE_8BPP (0x2<<26) |
| #define DISPPLANE_15_16BPP (0x4<<26) |
| #define DISPPLANE_16BPP (0x5<<26) |
| #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) |
| #define DISPPLANE_32BPP (0x7<<26) |
| #define DISPPLANE_STEREO_ENABLE (1<<25) |
| #define DISPPLANE_STEREO_DISABLE 0 |
| #define DISPPLANE_SEL_PIPE_MASK (1<<24) |
| #define DISPPLANE_SEL_PIPE_A 0 |
| #define DISPPLANE_SEL_PIPE_B (1<<24) |
| #define DISPPLANE_SRC_KEY_ENABLE (1<<22) |
| #define DISPPLANE_SRC_KEY_DISABLE 0 |
| #define DISPPLANE_LINE_DOUBLE (1<<20) |
| #define DISPPLANE_NO_LINE_DOUBLE 0 |
| #define DISPPLANE_STEREO_POLARITY_FIRST 0 |
| #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) |
| /* plane B only */ |
| #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
| #define DISPPLANE_ALPHA_TRANS_DISABLE 0 |
| #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 |
| #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) |
| |
| #define DSPABASE 0x70184 |
| #define DSPASTRIDE 0x70188 |
| |
| #define DSPBBASE 0x71184 |
| #define DSPBADDR DSPBBASE |
| #define DSPBSTRIDE 0x71188 |
| |
| #define DSPAKEYVAL 0x70194 |
| #define DSPAKEYMASK 0x70198 |
| |
| #define DSPAPOS 0x7018C /* reserved */ |
| #define DSPASIZE 0x70190 |
| #define DSPBPOS 0x7118C |
| #define DSPBSIZE 0x71190 |
| |
| #define DSPASURF 0x7019C |
| #define DSPATILEOFF 0x701A4 |
| |
| #define DSPBSURF 0x7119C |
| #define DSPBTILEOFF 0x711A4 |
| |
| #define VGACNTRL 0x71400 |
| # define VGA_DISP_DISABLE (1 << 31) |
| # define VGA_2X_MODE (1 << 30) |
| # define VGA_PIPE_B_SELECT (1 << 29) |
| |
| /* |
| * Some BIOS scratch area registers. The 845 (and 830?) store the amount |
| * of video memory available to the BIOS in SWF1. |
| */ |
| |
| #define SWF0 0x71410 |
| |
| /* |
| * 855 scratch registers. |
| */ |
| #define SWF10 0x70410 |
| |
| #define SWF30 0x72414 |
| |
| /* |
| * Overlay registers. These are overlay registers accessed via MMIO. |
| * Those loaded via the overlay register page are defined in i830_video.c. |
| */ |
| #define OVADD 0x30000 |
| |
| #define DOVSTA 0x30008 |
| #define OC_BUF (0x3<<20) |
| |
| #define OGAMC5 0x30010 |
| #define OGAMC4 0x30014 |
| #define OGAMC3 0x30018 |
| #define OGAMC2 0x3001c |
| #define OGAMC1 0x30020 |
| #define OGAMC0 0x30024 |
| /* |
| * Palette registers |
| */ |
| #define PALETTE_A 0x0a000 |
| #define PALETTE_B 0x0a800 |
| |
| #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
| #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
| #define IS_I85X(dev) ((dev)->pci_device == 0x3582) |
| #define IS_I855(dev) ((dev)->pci_device == 0x3582) |
| #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
| |
| #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) |
| #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
| #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
| #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2) |
| |
| #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ |
| (dev)->pci_device == 0x2982 || \ |
| (dev)->pci_device == 0x2992 || \ |
| (dev)->pci_device == 0x29A2 || \ |
| (dev)->pci_device == 0x2A02 || \ |
| (dev)->pci_device == 0x2A12) |
| |
| #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) |
| |
| #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ |
| (dev)->pci_device == 0x29B2 || \ |
| (dev)->pci_device == 0x29D2) |
| |
| #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ |
| IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) |
| |
| #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ |
| IS_I945GM(dev) || IS_I965GM(dev)) |
| |
| #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
| |
| #endif |