| #ifndef _ASM_I386_DMA_MAPPING_H |
| #define _ASM_I386_DMA_MAPPING_H |
| |
| #include <linux/mm.h> |
| #include <linux/scatterlist.h> |
| |
| #include <asm/cache.h> |
| #include <asm/io.h> |
| #include <asm/bug.h> |
| |
| static inline int |
| dma_mapping_error(dma_addr_t dma_addr) |
| { |
| return 0; |
| } |
| |
| extern int forbid_dac; |
| |
| static inline int |
| dma_supported(struct device *dev, u64 mask) |
| { |
| /* |
| * we fall back to GFP_DMA when the mask isn't all 1s, |
| * so we can't guarantee allocations that must be |
| * within a tighter range than GFP_DMA.. |
| */ |
| if(mask < 0x00ffffff) |
| return 0; |
| |
| /* Work around chipset bugs */ |
| if (forbid_dac > 0 && mask > 0xffffffffULL) |
| return 0; |
| |
| return 1; |
| } |
| |
| static inline int |
| dma_set_mask(struct device *dev, u64 mask) |
| { |
| if(!dev->dma_mask || !dma_supported(dev, mask)) |
| return -EIO; |
| |
| *dev->dma_mask = mask; |
| |
| return 0; |
| } |
| |
| static inline int |
| dma_get_cache_alignment(void) |
| { |
| /* no easy way to get cache size on all x86, so return the |
| * maximum possible, to be safe */ |
| return (1 << INTERNODE_CACHE_SHIFT); |
| } |
| |
| #define dma_is_consistent(d, h) (1) |
| |
| #define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY |
| extern int |
| dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, |
| dma_addr_t device_addr, size_t size, int flags); |
| |
| extern void |
| dma_release_declared_memory(struct device *dev); |
| |
| extern void * |
| dma_mark_declared_memory_occupied(struct device *dev, |
| dma_addr_t device_addr, size_t size); |
| |
| #endif |