| * Marvell MBUS common definitions. |
| * Copyright (C) 2008 Marvell Semiconductor |
| * This file is licensed under the terms of the GNU General Public |
| * License version 2. This program is licensed "as is" without any |
| * warranty of any kind, whether express or implied. |
| struct mbus_dram_target_info |
| * The 4-bit MBUS target ID of the DRAM controller. |
| * The base address, size, and MBUS attribute ID for each |
| * of the possible DRAM chip selects. Peripherals are |
| * required to support at least 4 decode windows. |
| struct mbus_dram_window { |
| * The Marvell mbus is to be found only on SOCs from the Orion family |
| * at the moment. Provide a dummy stub for other architectures. |
| extern const struct mbus_dram_target_info *mv_mbus_dram_info(void); |
| static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void) |