drivers/rtc/rtc-pm8xxx.c - LeafOS-Devices/android_kernel_samsung_gta4xl - Gitiles

 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
  * only version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
 #include <linux/of.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/rtc.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/regmap.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>

 /* RTC Register offsets from RTC CTRL REG */
 #define PM8XXX_ALARM_CTRL_OFFSET	0x01
 #define PM8XXX_RTC_WRITE_OFFSET		0x02
 #define PM8XXX_RTC_READ_OFFSET		0x06
 #define PM8XXX_ALARM_RW_OFFSET		0x0A

 /* RTC_CTRL register bit fields */
 #define PM8xxx_RTC_ENABLE		BIT(7)
 #define PM8xxx_RTC_ALARM_ENABLE		BIT(1)
 #define PM8xxx_RTC_ALARM_CLEAR		BIT(0)

 #define NUM_8_BIT_RTC_REGS		0x4

 /**
  * struct pm8xxx_rtc -  rtc driver internal structure
  * @rtc:		rtc device for this driver.
  * @regmap:		regmap used to access RTC registers
  * @allow_set_time:	indicates whether writing to the RTC is allowed
  * @rtc_alarm_irq:	rtc alarm irq number.
  * @rtc_base:		address of rtc control register.
  * @rtc_read_base:	base address of read registers.
  * @rtc_write_base:	base address of write registers.
  * @alarm_rw_base:	base address of alarm registers.
  * @ctrl_reg:		rtc control register.
  * @rtc_dev:		device structure.
  * @ctrl_reg_lock:	spinlock protecting access to ctrl_reg.
  */
 struct pm8xxx_rtc {
 	struct rtc_device *rtc;
 	struct regmap *regmap;
 	bool allow_set_time;
 	int rtc_alarm_irq;
 	int rtc_base;
 	int rtc_read_base;
 	int rtc_write_base;
 	int alarm_rw_base;
 	u8 ctrl_reg;
 	struct device *rtc_dev;
 	spinlock_t ctrl_reg_lock;
 };

 /*
  * Steps to write the RTC registers.
  * 1. Disable alarm if enabled.
  * 2. Write 0x00 to LSB.
  * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0].
  * 4. Enable alarm if disabled in step 1.
  */
 static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
 {
 	int rc, i;
 	unsigned long secs, irq_flags;
 	u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, ctrl_reg;
 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

 	if (!rtc_dd->allow_set_time)
 		return -EACCES;

 	rtc_tm_to_time(tm, &secs);

 	for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
 		value[i] = secs & 0xFF;
 		secs >>= 8;
 	}

 	dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);

 	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
 	ctrl_reg = rtc_dd->ctrl_reg;

 	if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) {
 		alarm_enabled = 1;
 		ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
 		rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
 		if (rc) {
 			dev_err(dev, "Write to RTC control register failed\n");
 			goto rtc_rw_fail;
 		}
 		rtc_dd->ctrl_reg = ctrl_reg;
 	} else {
 		spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
 	}

 	/* Write 0 to Byte[0] */
 	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, 0);
 	if (rc) {
 		dev_err(dev, "Write to RTC write data register failed\n");
 		goto rtc_rw_fail;
 	}

 	/* Write Byte[1], Byte[2], Byte[3] */
 	rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->rtc_write_base + 1,
 			       &value[1], sizeof(value) - 1);
 	if (rc) {
 		dev_err(dev, "Write to RTC write data register failed\n");
 		goto rtc_rw_fail;
 	}

 	/* Write Byte[0] */
 	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, value[0]);
 	if (rc) {
 		dev_err(dev, "Write to RTC write data register failed\n");
 		goto rtc_rw_fail;
 	}

 	if (alarm_enabled) {
 		ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
 		rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
 		if (rc) {
 			dev_err(dev, "Write to RTC control register failed\n");
 			goto rtc_rw_fail;
 		}
 		rtc_dd->ctrl_reg = ctrl_reg;
 	}

 rtc_rw_fail:
 	if (alarm_enabled)
 		spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);

 	return rc;
 }

 static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
 {
 	int rc;
 	u8 value[NUM_8_BIT_RTC_REGS];
 	unsigned long secs;
 	unsigned int reg;
 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

 	rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base,
 			      value, sizeof(value));
 	if (rc) {
 		dev_err(dev, "RTC read data register failed\n");
 		return rc;
 	}

 	/*
 	 * Read the LSB again and check if there has been a carry over.
 	 * If there is, redo the read operation.
 	 */
 	rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_read_base, &reg);
 	if (rc < 0) {
 		dev_err(dev, "RTC read data register failed\n");
 		return rc;
 	}

 	if (unlikely(reg < value[0])) {
 		rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base,
 				      value, sizeof(value));
 		if (rc) {
 			dev_err(dev, "RTC read data register failed\n");
 			return rc;
 		}
 	}

 	secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);

 	rtc_time_to_tm(secs, tm);

 	rc = rtc_valid_tm(tm);
 	if (rc < 0) {
 		dev_err(dev, "Invalid time read from RTC\n");
 		return rc;
 	}

 	dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
 		secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
 		tm->tm_mday, tm->tm_mon, tm->tm_year);

 	return 0;
 }

 static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 {
 	int rc, i;
 	u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg;
 	unsigned long secs, irq_flags;
 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

 	rtc_tm_to_time(&alarm->time, &secs);

 	for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
 		value[i] = secs & 0xFF;
 		secs >>= 8;
 	}

 	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);

 	rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->alarm_rw_base, value,
 			       sizeof(value));
 	if (rc) {
 		dev_err(dev, "Write to RTC ALARM register failed\n");
 		goto rtc_rw_fail;
 	}

 	ctrl_reg = rtc_dd->ctrl_reg;

 	if (alarm->enabled)
 		ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
 	else
 		ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;

 	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
 	if (rc) {
 		dev_err(dev, "Write to RTC control register failed\n");
 		goto rtc_rw_fail;
 	}

 	rtc_dd->ctrl_reg = ctrl_reg;

 	dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
 		alarm->time.tm_hour, alarm->time.tm_min,
 		alarm->time.tm_sec, alarm->time.tm_mday,
 		alarm->time.tm_mon, alarm->time.tm_year);
 rtc_rw_fail:
 	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
 	return rc;
 }

 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 {
 	int rc;
 	u8 value[NUM_8_BIT_RTC_REGS];
 	unsigned long secs;
 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

 	rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->alarm_rw_base, value,
 			      sizeof(value));
 	if (rc) {
 		dev_err(dev, "RTC alarm time read failed\n");
 		return rc;
 	}

 	secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);

 	rtc_time_to_tm(secs, &alarm->time);

 	rc = rtc_valid_tm(&alarm->time);
 	if (rc < 0) {
 		dev_err(dev, "Invalid alarm time read from RTC\n");
 		return rc;
 	}

 	dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
 		alarm->time.tm_hour, alarm->time.tm_min,
 		alarm->time.tm_sec, alarm->time.tm_mday,
 		alarm->time.tm_mon, alarm->time.tm_year);

 	return 0;
 }

 static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 {
 	int rc;
 	unsigned long irq_flags;
 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
 	u8 ctrl_reg;

 	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);

 	ctrl_reg = rtc_dd->ctrl_reg;

 	if (enable)
 		ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
 	else
 		ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;

 	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
 	if (rc) {
 		dev_err(dev, "Write to RTC control register failed\n");
 		goto rtc_rw_fail;
 	}

 	rtc_dd->ctrl_reg = ctrl_reg;

 rtc_rw_fail:
 	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
 	return rc;
 }

 static const struct rtc_class_ops pm8xxx_rtc_ops = {
 	.read_time	= pm8xxx_rtc_read_time,
 	.set_time	= pm8xxx_rtc_set_time,
 	.set_alarm	= pm8xxx_rtc_set_alarm,
 	.read_alarm	= pm8xxx_rtc_read_alarm,
 	.alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
 };

 static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
 {
 	struct pm8xxx_rtc *rtc_dd = dev_id;
 	unsigned int ctrl_reg;
 	int rc;
 	unsigned long irq_flags;

 	rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);

 	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);

 	/* Clear the alarm enable bit */
 	ctrl_reg = rtc_dd->ctrl_reg;
 	ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;

 	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
 	if (rc) {
 		spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
 		dev_err(rtc_dd->rtc_dev,
 			"Write to RTC control register failed\n");
 		goto rtc_alarm_handled;
 	}

 	rtc_dd->ctrl_reg = ctrl_reg;
 	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);

 	/* Clear RTC alarm register */
 	rc = regmap_read(rtc_dd->regmap,
 			 rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET,
 			 &ctrl_reg);
 	if (rc) {
 		dev_err(rtc_dd->rtc_dev,
 			"RTC Alarm control register read failed\n");
 		goto rtc_alarm_handled;
 	}

 	ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR;
 	rc = regmap_write(rtc_dd->regmap,
 			  rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET,
 			  ctrl_reg);
 	if (rc)
 		dev_err(rtc_dd->rtc_dev,
 			"Write to RTC Alarm control register failed\n");

 rtc_alarm_handled:
 	return IRQ_HANDLED;
 }

 /*
  * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
  */
 static const struct of_device_id pm8xxx_id_table[] = {
 	{ .compatible = "qcom,pm8921-rtc", .data = (void *) 0x11D },
 	{ .compatible = "qcom,pm8058-rtc", .data = (void *) 0x1E8 },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);

 static int pm8xxx_rtc_probe(struct platform_device *pdev)
 {
 	int rc;
 	unsigned int ctrl_reg;
 	struct pm8xxx_rtc *rtc_dd;
 	const struct of_device_id *match;

 	match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
 	if (!match)
 		return -ENXIO;

 	rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
 	if (rtc_dd == NULL)
 		return -ENOMEM;

 	/* Initialise spinlock to protect RTC control register */
 	spin_lock_init(&rtc_dd->ctrl_reg_lock);

 	rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
 	if (!rtc_dd->regmap) {
 		dev_err(&pdev->dev, "Parent regmap unavailable.\n");
 		return -ENXIO;
 	}

 	rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
 	if (rtc_dd->rtc_alarm_irq < 0) {
 		dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
 		return -ENXIO;
 	}

 	rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
 						      "allow-set-time");

 	rtc_dd->rtc_base = (long) match->data;

 	/* Setup RTC register addresses */
 	rtc_dd->rtc_write_base = rtc_dd->rtc_base + PM8XXX_RTC_WRITE_OFFSET;
 	rtc_dd->rtc_read_base = rtc_dd->rtc_base + PM8XXX_RTC_READ_OFFSET;
 	rtc_dd->alarm_rw_base = rtc_dd->rtc_base + PM8XXX_ALARM_RW_OFFSET;

 	rtc_dd->rtc_dev = &pdev->dev;

 	/* Check if the RTC is on, else turn it on */
 	rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_base, &ctrl_reg);
 	if (rc) {
 		dev_err(&pdev->dev, "RTC control register read failed!\n");
 		return rc;
 	}

 	if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
 		ctrl_reg |= PM8xxx_RTC_ENABLE;
 		rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
 		if (rc) {
 			dev_err(&pdev->dev,
 				"Write to RTC control register failed\n");
 			return rc;
 		}
 	}

 	rtc_dd->ctrl_reg = ctrl_reg;

 	platform_set_drvdata(pdev, rtc_dd);

 	device_init_wakeup(&pdev->dev, 1);

 	/* Register the RTC device */
 	rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
 					       &pm8xxx_rtc_ops, THIS_MODULE);
 	if (IS_ERR(rtc_dd->rtc)) {
 		dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
 			__func__, PTR_ERR(rtc_dd->rtc));
 		return PTR_ERR(rtc_dd->rtc);
 	}

 	/* Request the alarm IRQ */
 	rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
 					  pm8xxx_alarm_trigger,
 					  IRQF_TRIGGER_RISING,
 					  "pm8xxx_rtc_alarm", rtc_dd);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
 		return rc;
 	}

 	dev_dbg(&pdev->dev, "Probe success !!\n");

 	return 0;
 }

 #ifdef CONFIG_PM_SLEEP
 static int pm8xxx_rtc_resume(struct device *dev)
 {
 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

 	if (device_may_wakeup(dev))
 		disable_irq_wake(rtc_dd->rtc_alarm_irq);

 	return 0;
 }

 static int pm8xxx_rtc_suspend(struct device *dev)
 {
 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

 	if (device_may_wakeup(dev))
 		enable_irq_wake(rtc_dd->rtc_alarm_irq);

 	return 0;
 }
 #endif

 static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
 			 pm8xxx_rtc_suspend,
 			 pm8xxx_rtc_resume);

 static struct platform_driver pm8xxx_rtc_driver = {
 	.probe		= pm8xxx_rtc_probe,
 	.driver	= {
 		.name		= "rtc-pm8xxx",
 		.pm		= &pm8xxx_rtc_pm_ops,
 		.of_match_table	= pm8xxx_id_table,
 	},
 };

 module_platform_driver(pm8xxx_rtc_driver);

 MODULE_ALIAS("platform:rtc-pm8xxx");
 MODULE_DESCRIPTION("PMIC8xxx RTC driver");
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
	/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 and
	* only version 2 as published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*/
	#include <linux/of.h>
	#include <linux/module.h>
	#include <linux/init.h>
	#include <linux/rtc.h>
	#include <linux/platform_device.h>
	#include <linux/pm.h>
	#include <linux/regmap.h>
	#include <linux/slab.h>
	#include <linux/spinlock.h>

	/* RTC Register offsets from RTC CTRL REG */
	#define PM8XXX_ALARM_CTRL_OFFSET 0x01
	#define PM8XXX_RTC_WRITE_OFFSET 0x02
	#define PM8XXX_RTC_READ_OFFSET 0x06
	#define PM8XXX_ALARM_RW_OFFSET 0x0A

	/* RTC_CTRL register bit fields */
	#define PM8xxx_RTC_ENABLE BIT(7)
	#define PM8xxx_RTC_ALARM_ENABLE BIT(1)
	#define PM8xxx_RTC_ALARM_CLEAR BIT(0)

	#define NUM_8_BIT_RTC_REGS 0x4

	/**
	* struct pm8xxx_rtc - rtc driver internal structure
	* @rtc: rtc device for this driver.
	* @regmap: regmap used to access RTC registers
	* @allow_set_time: indicates whether writing to the RTC is allowed
	* @rtc_alarm_irq: rtc alarm irq number.
	* @rtc_base: address of rtc control register.
	* @rtc_read_base: base address of read registers.
	* @rtc_write_base: base address of write registers.
	* @alarm_rw_base: base address of alarm registers.
	* @ctrl_reg: rtc control register.
	* @rtc_dev: device structure.
	* @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
	*/
	struct pm8xxx_rtc {
	struct rtc_device *rtc;
	struct regmap *regmap;
	bool allow_set_time;
	int rtc_alarm_irq;
	int rtc_base;
	int rtc_read_base;
	int rtc_write_base;
	int alarm_rw_base;
	u8 ctrl_reg;
	struct device *rtc_dev;
	spinlock_t ctrl_reg_lock;
	};

	/*
	* Steps to write the RTC registers.
	* 1. Disable alarm if enabled.
	* 2. Write 0x00 to LSB.
	* 3. Write Byte[1], Byte[2], Byte[3] then Byte[0].
	* 4. Enable alarm if disabled in step 1.
	*/
	static int pm8xxx_rtc_set_time(struct device dev, struct rtc_time tm)
	{
	int rc, i;
	unsigned long secs, irq_flags;
	u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, ctrl_reg;
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

	if (!rtc_dd->allow_set_time)
	return -EACCES;

	rtc_tm_to_time(tm, &secs);

	for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
	value[i] = secs & 0xFF;
	secs >>= 8;
	}

	dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);

	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
	ctrl_reg = rtc_dd->ctrl_reg;

	if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) {
	alarm_enabled = 1;
	ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
	if (rc) {
	dev_err(dev, "Write to RTC control register failed\n");
	goto rtc_rw_fail;
	}
	rtc_dd->ctrl_reg = ctrl_reg;
	} else {
	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
	}

	/* Write 0 to Byte[0] */
	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, 0);
	if (rc) {
	dev_err(dev, "Write to RTC write data register failed\n");
	goto rtc_rw_fail;
	}

	/* Write Byte[1], Byte[2], Byte[3] */
	rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->rtc_write_base + 1,
	&value[1], sizeof(value) - 1);
	if (rc) {
	dev_err(dev, "Write to RTC write data register failed\n");
	goto rtc_rw_fail;
	}

	/* Write Byte[0] */
	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, value[0]);
	if (rc) {
	dev_err(dev, "Write to RTC write data register failed\n");
	goto rtc_rw_fail;
	}

	if (alarm_enabled) {
	ctrl_reg \|= PM8xxx_RTC_ALARM_ENABLE;
	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
	if (rc) {
	dev_err(dev, "Write to RTC control register failed\n");
	goto rtc_rw_fail;
	}
	rtc_dd->ctrl_reg = ctrl_reg;
	}

	rtc_rw_fail:
	if (alarm_enabled)
	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);

	return rc;
	}

	static int pm8xxx_rtc_read_time(struct device dev, struct rtc_time tm)
	{
	int rc;
	u8 value[NUM_8_BIT_RTC_REGS];
	unsigned long secs;
	unsigned int reg;
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

	rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base,
	value, sizeof(value));
	if (rc) {
	dev_err(dev, "RTC read data register failed\n");
	return rc;
	}

	/*
	* Read the LSB again and check if there has been a carry over.
	* If there is, redo the read operation.
	*/
	rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_read_base, &reg);
	if (rc < 0) {
	dev_err(dev, "RTC read data register failed\n");
	return rc;
	}

	if (unlikely(reg < value[0])) {
	rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base,
	value, sizeof(value));
	if (rc) {
	dev_err(dev, "RTC read data register failed\n");
	return rc;
	}
	}

	secs = value[0] \| (value[1] << 8) \| (value[2] << 16) \| (value[3] << 24);

	rtc_time_to_tm(secs, tm);

	rc = rtc_valid_tm(tm);
	if (rc < 0) {
	dev_err(dev, "Invalid time read from RTC\n");
	return rc;
	}

	dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
	secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
	tm->tm_mday, tm->tm_mon, tm->tm_year);

	return 0;
	}

	static int pm8xxx_rtc_set_alarm(struct device dev, struct rtc_wkalrm alarm)
	{
	int rc, i;
	u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg;
	unsigned long secs, irq_flags;
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

	rtc_tm_to_time(&alarm->time, &secs);

	for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
	value[i] = secs & 0xFF;
	secs >>= 8;
	}

	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);

	rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->alarm_rw_base, value,
	sizeof(value));
	if (rc) {
	dev_err(dev, "Write to RTC ALARM register failed\n");
	goto rtc_rw_fail;
	}

	ctrl_reg = rtc_dd->ctrl_reg;

	if (alarm->enabled)
	ctrl_reg \|= PM8xxx_RTC_ALARM_ENABLE;
	else
	ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;

	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
	if (rc) {
	dev_err(dev, "Write to RTC control register failed\n");
	goto rtc_rw_fail;
	}

	rtc_dd->ctrl_reg = ctrl_reg;

	dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
	alarm->time.tm_hour, alarm->time.tm_min,
	alarm->time.tm_sec, alarm->time.tm_mday,
	alarm->time.tm_mon, alarm->time.tm_year);
	rtc_rw_fail:
	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
	return rc;
	}

	static int pm8xxx_rtc_read_alarm(struct device dev, struct rtc_wkalrm alarm)
	{
	int rc;
	u8 value[NUM_8_BIT_RTC_REGS];
	unsigned long secs;
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

	rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->alarm_rw_base, value,
	sizeof(value));
	if (rc) {
	dev_err(dev, "RTC alarm time read failed\n");
	return rc;
	}

	secs = value[0] \| (value[1] << 8) \| (value[2] << 16) \| (value[3] << 24);

	rtc_time_to_tm(secs, &alarm->time);

	rc = rtc_valid_tm(&alarm->time);
	if (rc < 0) {
	dev_err(dev, "Invalid alarm time read from RTC\n");
	return rc;
	}

	dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
	alarm->time.tm_hour, alarm->time.tm_min,
	alarm->time.tm_sec, alarm->time.tm_mday,
	alarm->time.tm_mon, alarm->time.tm_year);

	return 0;
	}

	static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
	{
	int rc;
	unsigned long irq_flags;
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
	u8 ctrl_reg;

	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);

	ctrl_reg = rtc_dd->ctrl_reg;

	if (enable)
	ctrl_reg \|= PM8xxx_RTC_ALARM_ENABLE;
	else
	ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;

	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
	if (rc) {
	dev_err(dev, "Write to RTC control register failed\n");
	goto rtc_rw_fail;
	}

	rtc_dd->ctrl_reg = ctrl_reg;

	rtc_rw_fail:
	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
	return rc;
	}

	static const struct rtc_class_ops pm8xxx_rtc_ops = {
	.read_time = pm8xxx_rtc_read_time,
	.set_time = pm8xxx_rtc_set_time,
	.set_alarm = pm8xxx_rtc_set_alarm,
	.read_alarm = pm8xxx_rtc_read_alarm,
	.alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
	};

	static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
	{
	struct pm8xxx_rtc *rtc_dd = dev_id;
	unsigned int ctrl_reg;
	int rc;
	unsigned long irq_flags;

	rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF \| RTC_AF);

	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);

	/* Clear the alarm enable bit */
	ctrl_reg = rtc_dd->ctrl_reg;
	ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;

	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
	if (rc) {
	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
	dev_err(rtc_dd->rtc_dev,
	"Write to RTC control register failed\n");
	goto rtc_alarm_handled;
	}

	rtc_dd->ctrl_reg = ctrl_reg;
	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);

	/* Clear RTC alarm register */
	rc = regmap_read(rtc_dd->regmap,
	rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET,
	&ctrl_reg);
	if (rc) {
	dev_err(rtc_dd->rtc_dev,
	"RTC Alarm control register read failed\n");
	goto rtc_alarm_handled;
	}

	ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR;
	rc = regmap_write(rtc_dd->regmap,
	rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET,
	ctrl_reg);
	if (rc)
	dev_err(rtc_dd->rtc_dev,
	"Write to RTC Alarm control register failed\n");

	rtc_alarm_handled:
	return IRQ_HANDLED;
	}

	/*
	* Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
	*/
	static const struct of_device_id pm8xxx_id_table[] = {
	{ .compatible = "qcom,pm8921-rtc", .data = (void *) 0x11D },
	{ .compatible = "qcom,pm8058-rtc", .data = (void *) 0x1E8 },
	{ },
	};
	MODULE_DEVICE_TABLE(of, pm8xxx_id_table);

	static int pm8xxx_rtc_probe(struct platform_device *pdev)
	{
	int rc;
	unsigned int ctrl_reg;
	struct pm8xxx_rtc *rtc_dd;
	const struct of_device_id *match;

	match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
	if (!match)
	return -ENXIO;

	rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
	if (rtc_dd == NULL)
	return -ENOMEM;

	/* Initialise spinlock to protect RTC control register */
	spin_lock_init(&rtc_dd->ctrl_reg_lock);

	rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
	if (!rtc_dd->regmap) {
	dev_err(&pdev->dev, "Parent regmap unavailable.\n");
	return -ENXIO;
	}

	rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
	if (rtc_dd->rtc_alarm_irq < 0) {
	dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
	return -ENXIO;
	}

	rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
	"allow-set-time");

	rtc_dd->rtc_base = (long) match->data;

	/* Setup RTC register addresses */
	rtc_dd->rtc_write_base = rtc_dd->rtc_base + PM8XXX_RTC_WRITE_OFFSET;
	rtc_dd->rtc_read_base = rtc_dd->rtc_base + PM8XXX_RTC_READ_OFFSET;
	rtc_dd->alarm_rw_base = rtc_dd->rtc_base + PM8XXX_ALARM_RW_OFFSET;

	rtc_dd->rtc_dev = &pdev->dev;

	/* Check if the RTC is on, else turn it on */
	rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_base, &ctrl_reg);
	if (rc) {
	dev_err(&pdev->dev, "RTC control register read failed!\n");
	return rc;
	}

	if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
	ctrl_reg \|= PM8xxx_RTC_ENABLE;
	rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
	if (rc) {
	dev_err(&pdev->dev,
	"Write to RTC control register failed\n");
	return rc;
	}
	}

	rtc_dd->ctrl_reg = ctrl_reg;

	platform_set_drvdata(pdev, rtc_dd);

	device_init_wakeup(&pdev->dev, 1);

	/* Register the RTC device */
	rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
	&pm8xxx_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc_dd->rtc)) {
	dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
	__func__, PTR_ERR(rtc_dd->rtc));
	return PTR_ERR(rtc_dd->rtc);
	}

	/* Request the alarm IRQ */
	rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
	pm8xxx_alarm_trigger,
	IRQF_TRIGGER_RISING,
	"pm8xxx_rtc_alarm", rtc_dd);
	if (rc < 0) {
	dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
	return rc;
	}

	dev_dbg(&pdev->dev, "Probe success !!\n");

	return 0;
	}

	#ifdef CONFIG_PM_SLEEP
	static int pm8xxx_rtc_resume(struct device *dev)
	{
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
	disable_irq_wake(rtc_dd->rtc_alarm_irq);

	return 0;
	}

	static int pm8xxx_rtc_suspend(struct device *dev)
	{
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
	enable_irq_wake(rtc_dd->rtc_alarm_irq);

	return 0;
	}
	#endif

	static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
	pm8xxx_rtc_suspend,
	pm8xxx_rtc_resume);

	static struct platform_driver pm8xxx_rtc_driver = {
	.probe = pm8xxx_rtc_probe,
	.driver = {
	.name = "rtc-pm8xxx",
	.pm = &pm8xxx_rtc_pm_ops,
	.of_match_table = pm8xxx_id_table,
	},
	};

	module_platform_driver(pm8xxx_rtc_driver);

	MODULE_ALIAS("platform:rtc-pm8xxx");
	MODULE_DESCRIPTION("PMIC8xxx RTC driver");
	MODULE_LICENSE("GPL v2");
	MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");