| Srinidhi Kasagar | ffae4e0 | 2009-11-28 08:10:40 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2008 STMicroelectronics |
| 3 | * Copyright (C) 2009 ST-Ericsson. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | */ |
| 10 | #ifndef ASM_ARCH_IRQS_H |
| 11 | #define ASM_ARCH_IRQS_H |
| 12 | |
| 13 | #include <mach/hardware.h> |
| 14 | |
| 15 | #define IRQ_LOCALTIMER 29 |
| 16 | #define IRQ_LOCALWDOG 30 |
| 17 | |
| 18 | /* Shared Peripheral Interrupt (SHPI) */ |
| 19 | #define IRQ_SHPI_START 32 |
| 20 | |
| 21 | /* Interrupt numbers generic for shared peripheral */ |
| 22 | #define IRQ_MTU0 (IRQ_SHPI_START + 4) |
| 23 | #define IRQ_SPI2 (IRQ_SHPI_START + 6) |
| 24 | #define IRQ_SPI0 (IRQ_SHPI_START + 8) |
| 25 | #define IRQ_UART0 (IRQ_SHPI_START + 11) |
| 26 | #define IRQ_I2C3 (IRQ_SHPI_START + 12) |
| 27 | #define IRQ_SSP0 (IRQ_SHPI_START + 14) |
| 28 | #define IRQ_MTU1 (IRQ_SHPI_START + 17) |
| 29 | #define IRQ_RTC_RTT (IRQ_SHPI_START + 18) |
| 30 | #define IRQ_UART1 (IRQ_SHPI_START + 19) |
| 31 | #define IRQ_I2C0 (IRQ_SHPI_START + 21) |
| 32 | #define IRQ_I2C1 (IRQ_SHPI_START + 22) |
| 33 | #define IRQ_USBOTG (IRQ_SHPI_START + 23) |
| 34 | #define IRQ_DMA (IRQ_SHPI_START + 25) |
| 35 | #define IRQ_UART2 (IRQ_SHPI_START + 26) |
| 36 | #define IRQ_HSIR_EXCEP (IRQ_SHPI_START + 29) |
| 37 | #define IRQ_MSP0 (IRQ_SHPI_START + 31) |
| 38 | #define IRQ_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32) |
| 39 | #define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) |
| 40 | #define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) |
| 41 | #define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) |
| 42 | #define IRQ_AB4500 (IRQ_SHPI_START + 40) |
| 43 | #define IRQ_DISP (IRQ_SHPI_START + 48) |
| 44 | #define IRQ_SiPI3 (IRQ_SHPI_START + 49) |
| 45 | #define IRQ_SSP1 (IRQ_SHPI_START + 52) |
| 46 | #define IRQ_I2C2 (IRQ_SHPI_START + 55) |
| 47 | #define IRQ_SDMMC0 (IRQ_SHPI_START + 60) |
| 48 | #define IRQ_MSP1 (IRQ_SHPI_START + 62) |
| 49 | #define IRQ_SPI1 (IRQ_SHPI_START + 96) |
| 50 | #define IRQ_MSP2 (IRQ_SHPI_START + 98) |
| 51 | #define IRQ_SDMMC4 (IRQ_SHPI_START + 99) |
| 52 | #define IRQ_HSIRD0 (IRQ_SHPI_START + 104) |
| 53 | #define IRQ_HSIRD1 (IRQ_SHPI_START + 105) |
| 54 | #define IRQ_HSITD0 (IRQ_SHPI_START + 106) |
| 55 | #define IRQ_HSITD1 (IRQ_SHPI_START + 107) |
| 56 | #define IRQ_GPIO0 (IRQ_SHPI_START + 119) |
| 57 | #define IRQ_GPIO1 (IRQ_SHPI_START + 120) |
| 58 | #define IRQ_GPIO2 (IRQ_SHPI_START + 121) |
| 59 | #define IRQ_GPIO3 (IRQ_SHPI_START + 122) |
| 60 | #define IRQ_GPIO4 (IRQ_SHPI_START + 123) |
| 61 | #define IRQ_GPIO5 (IRQ_SHPI_START + 124) |
| 62 | #define IRQ_GPIO6 (IRQ_SHPI_START + 125) |
| 63 | #define IRQ_GPIO7 (IRQ_SHPI_START + 126) |
| 64 | #define IRQ_GPIO8 (IRQ_SHPI_START + 127) |
| 65 | |
| 66 | /* There are 128 shared peripheral interrupts assigned to |
| 67 | * INTID[160:32]. The first 32 interrupts are reserved. |
| 68 | */ |
| 69 | #define NR_IRQS 161 |
| 70 | |
| 71 | #endif /*ASM_ARCH_IRQS_H*/ |